1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2015-2019 Solarflare Communications Inc.
11 #if EFSYS_OPT_MEDFORD2
13 static __checkReturn efx_rc_t
14 medford2_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
21 /* FIXME: support new Medford2 dynamic port modes */
23 if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
27 *bandwidth_mbpsp = bandwidth;
32 EFSYS_PROBE1(fail1, efx_rc_t, rc);
37 __checkReturn efx_rc_t
41 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
42 uint32_t sysclk, dpcpu_clk;
48 * Event queue creation is complete when an
49 * EVQ_INIT_DONE_EV event is received.
51 encp->enc_evq_init_done_ev_supported = B_TRUE;
54 * Enable firmware workarounds for hardware errata.
55 * Expected responses are:
57 * Success: workaround enabled or disabled as requested.
58 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
59 * Firmware does not support the MC_CMD_WORKAROUND request.
60 * (assume that the workaround is not supported).
61 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
62 * Firmware does not support the requested workaround.
63 * - MC_CMD_ERR_EPERM (reported as EACCES):
64 * Unprivileged function cannot enable/disable workarounds.
66 * See efx_mcdi_request_errcode() for MCDI error translations.
70 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
72 * Interrupt testing does not work for VFs on Medford2.
73 * See bug50084 and bug71432 comment 21.
75 encp->enc_bug41750_workaround = B_TRUE;
79 * If the bug61265 workaround is enabled, then interrupt holdoff timers
80 * cannot be controlled by timer table writes, so MCDI must be used
81 * (timer table writes can still be used for wakeup timers).
83 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
85 if ((rc == 0) || (rc == EACCES))
86 encp->enc_bug61265_workaround = B_TRUE;
87 else if ((rc == ENOTSUP) || (rc == ENOENT))
88 encp->enc_bug61265_workaround = B_FALSE;
92 /* Checksums for TSO sends should always be correct on Medford2. */
93 encp->enc_bug61297_workaround = B_FALSE;
95 /* Get clock frequencies (in MHz). */
96 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
100 * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
101 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
103 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
104 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
105 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
107 encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
108 encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
109 encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
111 /* Alignment for receive packet DMA buffers */
112 encp->enc_rx_buf_align_start = 1;
114 /* Get the RX DMA end padding alignment configuration */
115 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
119 /* Assume largest tail padding size supported by hardware */
122 encp->enc_rx_buf_align_end = end_padding;
124 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
125 encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
127 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
128 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
131 * The maximum supported transmit queue size is 2048. TXQs with 4096
132 * descriptors are not supported as the top bit is used for vfifo
135 encp->enc_txq_max_ndescs = MEDFORD2_TXQ_MAXNDESCS;
136 encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
138 EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
139 encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
140 encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
141 encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
144 * Medford2 stores a single global copy of VPD, not per-PF as on
147 encp->enc_vpd_is_global = B_TRUE;
149 rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
152 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
153 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
164 EFSYS_PROBE1(fail1, efx_rc_t, rc);
169 #endif /* EFSYS_OPT_MEDFORD2 */