1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2015-2019 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
14 medford_nic_get_required_pcie_bandwidth(
16 __out uint32_t *bandwidth_mbpsp)
21 if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
25 *bandwidth_mbpsp = bandwidth;
30 EFSYS_PROBE1(fail1, efx_rc_t, rc);
35 __checkReturn efx_rc_t
39 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
40 uint32_t sysclk, dpcpu_clk;
46 * Event queue creation is complete when an
47 * EVQ_INIT_DONE_EV event is received.
49 encp->enc_evq_init_done_ev_supported = B_TRUE;
52 * Enable firmware workarounds for hardware errata.
53 * Expected responses are:
55 * Success: workaround enabled or disabled as requested.
56 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
57 * Firmware does not support the MC_CMD_WORKAROUND request.
58 * (assume that the workaround is not supported).
59 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
60 * Firmware does not support the requested workaround.
61 * - MC_CMD_ERR_EPERM (reported as EACCES):
62 * Unprivileged function cannot enable/disable workarounds.
64 * See efx_mcdi_request_errcode() for MCDI error translations.
68 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
70 * Interrupt testing does not work for VFs. See bug50084 and
71 * bug71432 comment 21.
73 encp->enc_bug41750_workaround = B_TRUE;
77 * If the bug61265 workaround is enabled, then interrupt holdoff timers
78 * cannot be controlled by timer table writes, so MCDI must be used
79 * (timer table writes can still be used for wakeup timers).
81 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
83 if ((rc == 0) || (rc == EACCES))
84 encp->enc_bug61265_workaround = B_TRUE;
85 else if ((rc == ENOTSUP) || (rc == ENOENT))
86 encp->enc_bug61265_workaround = B_FALSE;
90 /* Checksums for TSO sends can be incorrect on Medford. */
91 encp->enc_bug61297_workaround = B_TRUE;
93 /* Get clock frequencies (in MHz). */
94 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
98 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
99 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
101 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
102 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
103 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
105 encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
106 encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
107 encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
109 /* Alignment for receive packet DMA buffers */
110 encp->enc_rx_buf_align_start = 1;
112 /* Get the RX DMA end padding alignment configuration */
113 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
117 /* Assume largest tail padding size supported by hardware */
120 encp->enc_rx_buf_align_end = end_padding;
122 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
123 encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
125 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
126 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
129 * The maximum supported transmit queue size is 2048. TXQs with 4096
130 * descriptors are not supported as the top bit is used for vfifo
133 encp->enc_txq_max_ndescs = MEDFORD_TXQ_MAXNDESCS;
134 encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
136 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
137 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
138 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
139 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
142 * Medford stores a single global copy of VPD, not per-PF as on
145 encp->enc_vpd_is_global = B_TRUE;
147 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
150 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
151 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
162 EFSYS_PROBE1(fail1, efx_rc_t, rc);
167 #endif /* EFSYS_OPT_MEDFORD */