1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2018-2019 Solarflare Communications Inc.
10 #if EFSYS_OPT_RIVERHEAD
13 * Non-interrupting event queue requires interrupting event queue to
14 * refer to for wake-up events even if wake ups are never used.
15 * It could be even non-allocated event queue.
17 #define EFX_RHEAD_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
20 __checkReturn efx_rc_t
36 __checkReturn efx_rc_t
39 __in unsigned int index,
40 __in efsys_mem_t *esmp,
50 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
52 /* Set up the handler table */
53 eep->ee_rx = NULL; /* FIXME */
54 eep->ee_tx = NULL; /* FIXME */
55 eep->ee_driver = NULL; /* FIXME */
56 eep->ee_drv_gen = NULL; /* FIXME */
57 eep->ee_mcdi = NULL; /* FIXME */
59 /* Set up the event queue */
60 /* INIT_EVQ expects function-relative vector number */
61 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
62 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
64 } else if (index == EFX_RHEAD_ALWAYS_INTERRUPTING_EVQ_INDEX) {
66 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
67 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
69 irq = EFX_RHEAD_ALWAYS_INTERRUPTING_EVQ_INDEX;
73 * Interrupts may be raised for events immediately after the queue is
74 * created. See bug58606.
76 rc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,
84 EFSYS_PROBE1(fail1, efx_rc_t, rc);
93 efx_nic_t *enp = eep->ee_enp;
95 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_RIVERHEAD);
97 (void) efx_mcdi_fini_evq(enp, eep->ee_index);
100 __checkReturn efx_rc_t
103 __in unsigned int count)
105 efx_nic_t *enp = eep->ee_enp;
109 rptr = count & eep->ee_mask;
111 EFX_POPULATE_DWORD_2(dword, ERF_GZ_EVQ_ID, eep->ee_index,
113 /* EVQ_INT_PRIME lives function control window only on Riverhead */
114 EFX_BAR_WRITED(enp, ER_GZ_EVQ_INT_PRIME, &dword, B_FALSE);
124 _NOTE(ARGUNUSED(eep, data))
126 /* Not implemented yet */
127 EFSYS_ASSERT(B_FALSE);
131 * Poll event queue in batches. Size of the batch is equal to cache line
132 * size divided by event size.
134 * Event queue is written by NIC and read by CPU. If CPU starts reading
135 * of events on the cache line, read all remaining events in a tight
136 * loop while event is present.
138 #define EF100_EV_BATCH 8
141 * Check if event is present.
143 * Riverhead EvQs use a phase bit to indicate the presence of valid events,
144 * by flipping the phase bit on each wrap of the write index.
146 #define EF100_EV_PRESENT(_qword, _phase_bit) \
147 (EFX_QWORD_FIELD((_qword), ESF_GZ_EV_EVQ_PHASE) == _phase_bit)
152 __inout unsigned int *countp,
153 __in const efx_ev_callbacks_t *eecp,
156 efx_qword_t ev[EF100_EV_BATCH];
158 unsigned int phase_bit;
164 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
165 EFSYS_ASSERT(countp != NULL);
166 EFSYS_ASSERT(eecp != NULL);
170 /* Read up until the end of the batch period */
171 batch = EF100_EV_BATCH - (count & (EF100_EV_BATCH - 1));
172 phase_bit = (count & (eep->ee_mask + 1)) != 0;
173 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
174 for (total = 0; total < batch; ++total) {
175 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
177 if (!EF100_EV_PRESENT(ev[total], phase_bit))
180 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
181 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
182 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
184 offset += sizeof (efx_qword_t);
187 /* Process the batch of events */
188 for (index = 0; index < total; ++index) {
189 boolean_t should_abort;
192 EFX_EV_QSTAT_INCR(eep, EV_ALL);
194 code = EFX_QWORD_FIELD(ev[index], ESF_GZ_E_TYPE);
197 EFSYS_PROBE3(bad_event,
198 unsigned int, eep->ee_index,
200 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
202 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
204 EFSYS_ASSERT(eecp->eec_exception != NULL);
205 (void) eecp->eec_exception(arg,
206 EFX_EXCEPTION_EV_ERROR, code);
207 should_abort = B_TRUE;
210 /* Ignore subsequent events */
214 * Poison batch to ensure the outer
215 * loop is broken out of.
217 EFSYS_ASSERT(batch <= EF100_EV_BATCH);
218 batch += (EF100_EV_BATCH << 1);
219 EFSYS_ASSERT(total != batch);
225 * There is no necessity to clear processed events since
226 * phase bit which is flipping on each write index wrap
227 * is used for event presence indication.
232 } while (total == batch);
237 __checkReturn efx_rc_t
240 __in unsigned int us)
242 _NOTE(ARGUNUSED(eep, us))
250 rhead_ev_qstats_update(
252 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
256 for (id = 0; id < EV_NQSTATS; id++) {
257 efsys_stat_t *essp = &stat[id];
259 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
260 eep->ee_stat[id] = 0;
263 #endif /* EFSYS_OPT_QSTATS */
265 #endif /* EFSYS_OPT_RIVERHEAD */