1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2018-2019 Solarflare Communications Inc.
7 #ifndef _SYS_RHEAD_IMPL_H
8 #define _SYS_RHEAD_IMPL_H
16 * Riverhead requires physically contiguous event rings (so, just one
17 * DMA address is sufficient to represent it), but MCDI interface is still
18 * in terms of 4k size 4k-aligned DMA buffers.
20 #define RHEAD_EVQ_MAXNBUFS 32
22 #define RHEAD_EVQ_MAXNEVS 16384
23 #define RHEAD_EVQ_MINNEVS 256
25 #define RHEAD_RXQ_MAXNDESCS 16384
26 #define RHEAD_RXQ_MINNDESCS 256
28 #define RHEAD_TXQ_MAXNDESCS 16384
29 #define RHEAD_TXQ_MINNDESCS 256
31 #define RHEAD_EVQ_DESC_SIZE (sizeof (efx_qword_t))
32 #define RHEAD_RXQ_DESC_SIZE (sizeof (efx_qword_t))
33 #define RHEAD_TXQ_DESC_SIZE (sizeof (efx_oword_t))
35 #if EFSYS_OPT_EV_EXTENDED_WIDTH
36 #define RHEAD_EVQ_EW_DESC_SIZE (sizeof (efx_xword_t))
43 extern __checkReturn efx_rc_t
48 extern __checkReturn efx_rc_t
53 extern __checkReturn efx_rc_t
54 rhead_nic_set_drv_limits(
55 __inout efx_nic_t *enp,
56 __in efx_drv_limits_t *edlp);
59 extern __checkReturn efx_rc_t
60 rhead_nic_get_vi_pool(
62 __out uint32_t *vi_countp);
65 extern __checkReturn efx_rc_t
66 rhead_nic_get_bar_region(
68 __in efx_nic_region_t region,
69 __out uint32_t *offsetp,
73 extern __checkReturn efx_rc_t
78 extern __checkReturn efx_rc_t
83 extern __checkReturn boolean_t
84 rhead_nic_hw_unavailable(
89 rhead_nic_set_hw_unavailable(
95 extern __checkReturn efx_rc_t
96 rhead_nic_register_test(
99 #endif /* EFSYS_OPT_DIAG */
104 __in efx_nic_t *enp);
109 __in efx_nic_t *enp);
115 extern __checkReturn efx_rc_t
117 __in efx_nic_t *enp);
122 __in efx_nic_t *enp);
125 extern __checkReturn efx_rc_t
128 __in unsigned int index,
129 __in efsys_mem_t *esmp,
134 __in efx_evq_t *eep);
139 __in efx_evq_t *eep);
142 extern __checkReturn efx_rc_t
145 __in unsigned int count);
157 __inout unsigned int *countp,
158 __in const efx_ev_callbacks_t *eecp,
162 extern __checkReturn efx_rc_t
165 __in unsigned int us);
171 rhead_ev_qstats_update(
173 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
175 #endif /* EFSYS_OPT_QSTATS */
181 extern __checkReturn efx_rc_t
184 __in efx_intr_type_t type,
185 __in efsys_mem_t *esmp);
190 __in efx_nic_t *enp);
195 __in efx_nic_t *enp);
199 rhead_intr_disable_unlocked(
200 __in efx_nic_t *enp);
203 extern __checkReturn efx_rc_t
206 __in unsigned int level);
210 rhead_intr_status_line(
212 __out boolean_t *fatalp,
213 __out uint32_t *qmaskp);
217 rhead_intr_status_message(
219 __in unsigned int message,
220 __out boolean_t *fatalp);
225 __in efx_nic_t *enp);
230 __in efx_nic_t *enp);
236 extern __checkReturn efx_rc_t
238 __in efx_nic_t *enp);
243 __in efx_nic_t *enp);
245 #if EFSYS_OPT_RX_SCATTER
248 extern __checkReturn efx_rc_t
249 rhead_rx_scatter_enable(
251 __in unsigned int buf_size);
253 #endif /* EFSYS_OPT_RX_SCATTER */
255 #if EFSYS_OPT_RX_SCALE
258 extern __checkReturn efx_rc_t
259 rhead_rx_scale_context_alloc(
261 __in efx_rx_scale_context_type_t type,
262 __in uint32_t num_queues,
263 __out uint32_t *rss_contextp);
266 extern __checkReturn efx_rc_t
267 rhead_rx_scale_context_free(
269 __in uint32_t rss_context);
272 extern __checkReturn efx_rc_t
273 rhead_rx_scale_mode_set(
275 __in uint32_t rss_context,
276 __in efx_rx_hash_alg_t alg,
277 __in efx_rx_hash_type_t type,
278 __in boolean_t insert);
281 extern __checkReturn efx_rc_t
282 rhead_rx_scale_key_set(
284 __in uint32_t rss_context,
285 __in_ecount(n) uint8_t *key,
289 extern __checkReturn efx_rc_t
290 rhead_rx_scale_tbl_set(
292 __in uint32_t rss_context,
293 __in_ecount(n) unsigned int *table,
297 extern __checkReturn uint32_t
298 rhead_rx_prefix_hash(
300 __in efx_rx_hash_alg_t func,
301 __in uint8_t *buffer);
303 #endif /* EFSYS_OPT_RX_SCALE */
306 extern __checkReturn efx_rc_t
307 rhead_rx_prefix_pktlen(
309 __in uint8_t *buffer,
310 __out uint16_t *lengthp);
316 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
318 __in unsigned int ndescs,
319 __in unsigned int completed,
320 __in unsigned int added);
326 __in unsigned int added,
327 __inout unsigned int *pushedp);
330 extern __checkReturn efx_rc_t
332 __in efx_rxq_t *erp);
337 __in efx_rxq_t *erp);
339 union efx_rxq_type_data_u;
342 extern __checkReturn efx_rc_t
345 __in unsigned int index,
346 __in unsigned int label,
347 __in efx_rxq_type_t type,
348 __in const union efx_rxq_type_data_u *type_data,
349 __in efsys_mem_t *esmp,
352 __in unsigned int flags,
354 __in efx_rxq_t *erp);
359 __in efx_rxq_t *erp);
365 extern __checkReturn efx_rc_t
367 __in efx_nic_t *enp);
372 __in efx_nic_t *enp);
375 extern __checkReturn efx_rc_t
378 __in unsigned int index,
379 __in unsigned int label,
380 __in efsys_mem_t *esmp,
386 __out unsigned int *addedp);
391 __in efx_txq_t *etp);
394 extern __checkReturn efx_rc_t
397 __in_ecount(ndescs) efx_buffer_t *ebp,
398 __in unsigned int ndescs,
399 __in unsigned int completed,
400 __inout unsigned int *addedp);
406 __in unsigned int added,
407 __in unsigned int pushed);
410 extern __checkReturn efx_rc_t
413 __in unsigned int ns);
416 extern __checkReturn efx_rc_t
418 __in efx_txq_t *etp);
423 __in efx_txq_t *etp);
426 extern __checkReturn efx_rc_t
429 __in_ecount(n) efx_desc_t *ed,
431 __in unsigned int completed,
432 __inout unsigned int *addedp);
438 rhead_tx_qstats_update(
440 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
442 #endif /* EFSYS_OPT_QSTATS */
447 extern __checkReturn efx_rc_t
448 rhead_tunnel_reconfigure(
449 __in efx_nic_t *enp);
454 __in efx_nic_t *enp);
456 #endif /* EFSYS_OPT_TUNNEL */
461 * Perform discovery of function control window by looking for a
462 * EF100 locator in Xilinx capabilities tables.
465 extern __checkReturn efx_rc_t
466 rhead_pci_nic_membar_lookup(
467 __in efsys_pci_config_t *espcp,
468 __in const efx_pci_ops_t *epop,
469 __out efx_bar_region_t *ebrp);
471 #endif /* EFSYS_OPT_PCI */
474 extern __checkReturn efx_rc_t
475 rhead_nic_xilinx_cap_tbl_read_ef100_locator(
476 __in efsys_bar_t *esbp,
477 __in efsys_dma_addr_t offset,
478 __out efx_bar_region_t *ebrp);
484 #endif /* _SYS_RHEAD_IMPL_H */