1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2018-2019 Solarflare Communications Inc.
7 #ifndef _SYS_RHEAD_IMPL_H
8 #define _SYS_RHEAD_IMPL_H
16 * Riverhead requires physically contiguous event rings (so, just one
17 * DMA address is sufficient to represent it), but MCDI interface is still
18 * in terms of 4k size 4k-aligned DMA buffers.
20 #define RHEAD_EVQ_MAXNBUFS 32
22 #define RHEAD_EVQ_MAXNEVS 16384
23 #define RHEAD_EVQ_MINNEVS 256
25 #define RHEAD_RXQ_MAXNDESCS 16384
26 #define RHEAD_RXQ_MINNDESCS 256
28 #define RHEAD_TXQ_MAXNDESCS 16384
29 #define RHEAD_TXQ_MINNDESCS 256
31 #define RHEAD_EVQ_DESC_SIZE (sizeof (efx_qword_t))
32 #define RHEAD_RXQ_DESC_SIZE (sizeof (efx_qword_t))
33 #define RHEAD_TXQ_DESC_SIZE (sizeof (efx_oword_t))
39 extern __checkReturn efx_rc_t
44 extern __checkReturn efx_rc_t
49 extern __checkReturn efx_rc_t
50 rhead_nic_set_drv_limits(
51 __inout efx_nic_t *enp,
52 __in efx_drv_limits_t *edlp);
55 extern __checkReturn efx_rc_t
56 rhead_nic_get_vi_pool(
58 __out uint32_t *vi_countp);
61 extern __checkReturn efx_rc_t
62 rhead_nic_get_bar_region(
64 __in efx_nic_region_t region,
65 __out uint32_t *offsetp,
69 extern __checkReturn efx_rc_t
74 extern __checkReturn efx_rc_t
79 extern __checkReturn boolean_t
80 rhead_nic_hw_unavailable(
85 rhead_nic_set_hw_unavailable(
91 extern __checkReturn efx_rc_t
92 rhead_nic_register_test(
95 #endif /* EFSYS_OPT_DIAG */
100 __in efx_nic_t *enp);
105 __in efx_nic_t *enp);
111 extern __checkReturn efx_rc_t
113 __in efx_nic_t *enp);
118 __in efx_nic_t *enp);
121 extern __checkReturn efx_rc_t
124 __in unsigned int index,
125 __in efsys_mem_t *esmp,
130 __in efx_evq_t *eep);
135 __in efx_evq_t *eep);
138 extern __checkReturn efx_rc_t
141 __in unsigned int count);
153 __inout unsigned int *countp,
154 __in const efx_ev_callbacks_t *eecp,
158 extern __checkReturn efx_rc_t
161 __in unsigned int us);
167 rhead_ev_qstats_update(
169 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
171 #endif /* EFSYS_OPT_QSTATS */
177 extern __checkReturn efx_rc_t
180 __in efx_intr_type_t type,
181 __in efsys_mem_t *esmp);
186 __in efx_nic_t *enp);
191 __in efx_nic_t *enp);
195 rhead_intr_disable_unlocked(
196 __in efx_nic_t *enp);
199 extern __checkReturn efx_rc_t
202 __in unsigned int level);
206 rhead_intr_status_line(
208 __out boolean_t *fatalp,
209 __out uint32_t *qmaskp);
213 rhead_intr_status_message(
215 __in unsigned int message,
216 __out boolean_t *fatalp);
221 __in efx_nic_t *enp);
226 __in efx_nic_t *enp);
232 extern __checkReturn efx_rc_t
234 __in efx_nic_t *enp);
239 __in efx_nic_t *enp);
241 #if EFSYS_OPT_RX_SCATTER
244 extern __checkReturn efx_rc_t
245 rhead_rx_scatter_enable(
247 __in unsigned int buf_size);
249 #endif /* EFSYS_OPT_RX_SCATTER */
251 #if EFSYS_OPT_RX_SCALE
254 extern __checkReturn efx_rc_t
255 rhead_rx_scale_context_alloc(
257 __in efx_rx_scale_context_type_t type,
258 __in uint32_t num_queues,
259 __out uint32_t *rss_contextp);
262 extern __checkReturn efx_rc_t
263 rhead_rx_scale_context_free(
265 __in uint32_t rss_context);
268 extern __checkReturn efx_rc_t
269 rhead_rx_scale_mode_set(
271 __in uint32_t rss_context,
272 __in efx_rx_hash_alg_t alg,
273 __in efx_rx_hash_type_t type,
274 __in boolean_t insert);
277 extern __checkReturn efx_rc_t
278 rhead_rx_scale_key_set(
280 __in uint32_t rss_context,
281 __in_ecount(n) uint8_t *key,
285 extern __checkReturn efx_rc_t
286 rhead_rx_scale_tbl_set(
288 __in uint32_t rss_context,
289 __in_ecount(n) unsigned int *table,
293 extern __checkReturn uint32_t
294 rhead_rx_prefix_hash(
296 __in efx_rx_hash_alg_t func,
297 __in uint8_t *buffer);
299 #endif /* EFSYS_OPT_RX_SCALE */
302 extern __checkReturn efx_rc_t
303 rhead_rx_prefix_pktlen(
305 __in uint8_t *buffer,
306 __out uint16_t *lengthp);
312 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
314 __in unsigned int ndescs,
315 __in unsigned int completed,
316 __in unsigned int added);
322 __in unsigned int added,
323 __inout unsigned int *pushedp);
326 extern __checkReturn efx_rc_t
328 __in efx_rxq_t *erp);
333 __in efx_rxq_t *erp);
335 union efx_rxq_type_data_u;
338 extern __checkReturn efx_rc_t
341 __in unsigned int index,
342 __in unsigned int label,
343 __in efx_rxq_type_t type,
344 __in const union efx_rxq_type_data_u *type_data,
345 __in efsys_mem_t *esmp,
348 __in unsigned int flags,
350 __in efx_rxq_t *erp);
355 __in efx_rxq_t *erp);
361 extern __checkReturn efx_rc_t
363 __in efx_nic_t *enp);
368 __in efx_nic_t *enp);
371 extern __checkReturn efx_rc_t
374 __in unsigned int index,
375 __in unsigned int label,
376 __in efsys_mem_t *esmp,
382 __out unsigned int *addedp);
387 __in efx_txq_t *etp);
390 extern __checkReturn efx_rc_t
393 __in_ecount(ndescs) efx_buffer_t *ebp,
394 __in unsigned int ndescs,
395 __in unsigned int completed,
396 __inout unsigned int *addedp);
402 __in unsigned int added,
403 __in unsigned int pushed);
406 extern __checkReturn efx_rc_t
409 __in unsigned int ns);
412 extern __checkReturn efx_rc_t
414 __in efx_txq_t *etp);
419 __in efx_txq_t *etp);
422 extern __checkReturn efx_rc_t
425 __in_ecount(n) efx_desc_t *ed,
427 __in unsigned int completed,
428 __inout unsigned int *addedp);
434 rhead_tx_qstats_update(
436 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
438 #endif /* EFSYS_OPT_QSTATS */
443 extern __checkReturn efx_rc_t
444 rhead_tunnel_reconfigure(
445 __in efx_nic_t *enp);
450 __in efx_nic_t *enp);
452 #endif /* EFSYS_OPT_TUNNEL */
457 * Perform discovery of function control window by looking for a
458 * EF100 locator in Xilinx capabilities tables.
461 extern __checkReturn efx_rc_t
462 rhead_pci_nic_membar_lookup(
463 __in efsys_pci_config_t *espcp,
464 __in const efx_pci_ops_t *epop,
465 __out efx_bar_region_t *ebrp);
467 #endif /* EFSYS_OPT_PCI */
470 extern __checkReturn efx_rc_t
471 rhead_nic_xilinx_cap_tbl_read_ef100_locator(
472 __in efsys_bar_t *esbp,
473 __in efsys_dma_addr_t offset,
474 __out efx_bar_region_t *ebrp);
480 #endif /* _SYS_RHEAD_IMPL_H */