1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2018-2019 Solarflare Communications Inc.
11 #if EFSYS_OPT_RIVERHEAD
13 __checkReturn efx_rc_t
17 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
22 if ((rc = efx_mcdi_nic_board_cfg(enp)) != 0)
25 encp->enc_clk_mult = 1; /* not used for Riverhead */
28 * FIXME There are TxSend and TxSeg descriptors on Riverhead.
29 * TxSeg is bigger than TxSend.
31 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_GZ_TX_SEND_LEN);
32 /* No boundary crossing limits */
33 encp->enc_tx_dma_desc_boundary = 0;
36 * Initialise design parameters to either a runtime value read from
37 * the design parameters area or the well known default value
38 * (see SF-119689-TC section 4.4 for details).
39 * FIXME: Read design parameters area values.
41 encp->enc_tx_tso_max_header_ndescs =
42 ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT;
43 encp->enc_tx_tso_max_header_length =
44 ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
45 encp->enc_tx_tso_max_payload_ndescs =
46 ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
47 encp->enc_tx_tso_max_payload_length =
48 ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
49 encp->enc_tx_tso_max_nframes =
50 ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
53 * Riverhead does not put any restrictions on TCP header offset limit.
55 encp->enc_tx_tso_tcp_header_offset_limit = UINT32_MAX;
58 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
59 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
60 * resources (allocated to this PCIe function), which is zero until
61 * after we have allocated VIs.
63 encp->enc_evq_limit = 1024;
64 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
65 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
67 encp->enc_buftbl_limit = UINT32_MAX;
70 * Riverhead event queue creation completes
71 * immediately (no initial event).
73 encp->enc_evq_init_done_ev_supported = B_FALSE;
76 * Enable firmware workarounds for hardware errata.
77 * Expected responses are:
79 * Success: workaround enabled or disabled as requested.
80 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
81 * Firmware does not support the MC_CMD_WORKAROUND request.
82 * (assume that the workaround is not supported).
83 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
84 * Firmware does not support the requested workaround.
85 * - MC_CMD_ERR_EPERM (reported as EACCES):
86 * Unprivileged function cannot enable/disable workarounds.
88 * See efx_mcdi_request_errcode() for MCDI error translations.
92 * Replay engine on Riverhead should suppress duplicate packets
93 * (e.g. because of exact multicast and all-multicast filters
94 * match) to the same RxQ.
96 encp->enc_bug26807_workaround = B_FALSE;
99 * Checksums for TSO sends should always be correct on Riverhead.
100 * FIXME: revisit when TSO support is implemented.
102 encp->enc_bug61297_workaround = B_FALSE;
104 encp->enc_evq_max_nevs = RHEAD_EVQ_MAXNEVS;
105 encp->enc_evq_min_nevs = RHEAD_EVQ_MINNEVS;
106 encp->enc_rxq_max_ndescs = RHEAD_RXQ_MAXNDESCS;
107 encp->enc_rxq_min_ndescs = RHEAD_RXQ_MINNDESCS;
108 encp->enc_txq_max_ndescs = RHEAD_TXQ_MAXNDESCS;
109 encp->enc_txq_min_ndescs = RHEAD_TXQ_MINNDESCS;
111 /* Riverhead FW does not support event queue timers yet. */
112 encp->enc_evq_timer_quantum_ns = 0;
113 encp->enc_evq_timer_max_us = 0;
115 encp->enc_ev_desc_size = RHEAD_EVQ_DESC_SIZE;
116 encp->enc_rx_desc_size = RHEAD_RXQ_DESC_SIZE;
117 encp->enc_tx_desc_size = RHEAD_TXQ_DESC_SIZE;
119 /* No required alignment for WPTR updates */
120 encp->enc_rx_push_align = 1;
122 /* Riverhead supports a single Rx prefix size. */
123 encp->enc_rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN;
125 /* Alignment for receive packet DMA buffers. */
126 encp->enc_rx_buf_align_start = 1;
128 /* Get the RX DMA end padding alignment configuration. */
129 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
133 /* Assume largest tail padding size supported by hardware. */
136 encp->enc_rx_buf_align_end = end_padding;
139 * Riverhead stores a single global copy of VPD, not per-PF as on
142 encp->enc_vpd_is_global = B_TRUE;
144 rc = ef10_nic_get_port_mode_bandwidth(enp, &bandwidth);
147 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
148 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
157 EFSYS_PROBE1(fail1, efx_rc_t, rc);
162 __checkReturn efx_rc_t
166 const efx_nic_ops_t *enop = enp->en_enop;
167 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
168 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
171 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp));
173 /* Read and clear any assertion state */
174 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
177 /* Exit the assertion handler */
178 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
182 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
185 /* Get remaining controller-specific board config */
186 if ((rc = enop->eno_board_cfg(enp)) != 0)
190 * Set default driver config limits (based on board config).
192 * FIXME: For now allocate a fixed number of VIs which is likely to be
193 * sufficient and small enough to allow multiple functions on the same
196 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
197 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
200 * The client driver must configure and enable PIO buffer support,
201 * but there is no PIO support on Riverhead anyway.
203 edcp->edc_max_piobuf_count = 0;
204 edcp->edc_pio_alloc_size = 0;
206 #if EFSYS_OPT_MAC_STATS
207 /* Wipe the MAC statistics */
208 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
212 #if EFSYS_OPT_LOOPBACK
213 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
219 #if EFSYS_OPT_LOOPBACK
223 #if EFSYS_OPT_MAC_STATS
234 EFSYS_PROBE1(fail1, efx_rc_t, rc);
239 __checkReturn efx_rc_t
240 rhead_nic_set_drv_limits(
241 __inout efx_nic_t *enp,
242 __in efx_drv_limits_t *edlp)
244 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
245 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
246 uint32_t min_evq_count, max_evq_count;
247 uint32_t min_rxq_count, max_rxq_count;
248 uint32_t min_txq_count, max_txq_count;
256 /* Get minimum required and maximum usable VI limits */
257 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
258 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
259 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
261 edcp->edc_min_vi_count =
262 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
264 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
265 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
266 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
268 edcp->edc_max_vi_count =
269 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
271 /* There is no PIO support on Riverhead */
272 edcp->edc_max_piobuf_count = 0;
273 edcp->edc_pio_alloc_size = 0;
278 EFSYS_PROBE1(fail1, efx_rc_t, rc);
283 __checkReturn efx_rc_t
289 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
290 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
292 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
295 if ((rc = efx_mcdi_entity_reset(enp)) != 0)
298 /* Clear RX/TX DMA queue errors */
299 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
308 EFSYS_PROBE1(fail1, efx_rc_t, rc);
313 __checkReturn efx_rc_t
317 const efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
318 uint32_t min_vi_count, max_vi_count;
319 uint32_t vi_count, vi_base, vi_shift;
320 uint32_t vi_window_size;
323 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp));
324 EFSYS_ASSERT3U(edcp->edc_max_piobuf_count, ==, 0);
326 /* Enable reporting of some events (e.g. link change) */
327 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
330 min_vi_count = edcp->edc_min_vi_count;
331 max_vi_count = edcp->edc_max_vi_count;
333 /* Ensure that the previously attached driver's VIs are freed */
334 if ((rc = efx_mcdi_free_vis(enp)) != 0)
338 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
339 * fails then retrying the request for fewer VI resources may succeed.
342 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
343 &vi_base, &vi_count, &vi_shift)) != 0)
346 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
348 if (vi_count < min_vi_count) {
353 enp->en_arch.ef10.ena_vi_base = vi_base;
354 enp->en_arch.ef10.ena_vi_count = vi_count;
355 enp->en_arch.ef10.ena_vi_shift = vi_shift;
357 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
358 EFX_VI_WINDOW_SHIFT_INVALID);
359 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
360 EFX_VI_WINDOW_SHIFT_64K);
361 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
363 /* Save UC memory mapping details */
364 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
365 enp->en_arch.ef10.ena_uc_mem_map_size =
366 vi_window_size * enp->en_arch.ef10.ena_vi_count;
368 /* No WC memory mapping since PIO is not supported */
369 enp->en_arch.ef10.ena_pio_write_vi_base = 0;
370 enp->en_arch.ef10.ena_wc_mem_map_offset = 0;
371 enp->en_arch.ef10.ena_wc_mem_map_size = 0;
373 enp->en_vport_id = EVB_PORT_ID_NULL;
375 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
382 (void) efx_mcdi_free_vis(enp);
389 EFSYS_PROBE1(fail1, efx_rc_t, rc);
394 __checkReturn efx_rc_t
395 rhead_nic_get_vi_pool(
397 __out uint32_t *vi_countp)
400 * Report VIs that the client driver can use.
401 * Do not include VIs used for PIO buffer writes.
403 *vi_countp = enp->en_arch.ef10.ena_vi_count;
408 __checkReturn efx_rc_t
409 rhead_nic_get_bar_region(
411 __in efx_nic_region_t region,
412 __out uint32_t *offsetp,
417 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp));
420 * TODO: Specify host memory mapping alignment and granularity
421 * in efx_drv_limits_t so that they can be taken into account
422 * when allocating extra VIs for PIO writes.
426 /* UC mapped memory BAR region for VI registers */
427 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
428 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
431 case EFX_REGION_PIO_WRITE_VI:
432 /* WC mapped memory BAR region for piobuf writes */
433 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
434 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
445 EFSYS_PROBE1(fail1, efx_rc_t, rc);
450 __checkReturn boolean_t
451 rhead_nic_hw_unavailable(
456 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
459 EFX_BAR_FCW_READD(enp, ER_GZ_MC_SFT_STATUS, &dword);
460 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
466 rhead_nic_set_hw_unavailable(enp);
472 rhead_nic_set_hw_unavailable(
475 EFSYS_PROBE(hw_unavail);
476 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
483 (void) efx_mcdi_free_vis(enp);
484 enp->en_arch.ef10.ena_vi_count = 0;
491 (void) efx_mcdi_drv_attach(enp, B_FALSE);
496 __checkReturn efx_rc_t
497 rhead_nic_register_test(
503 _NOTE(ARGUNUSED(enp))
504 _NOTE(CONSTANTCONDITION)
514 EFSYS_PROBE1(fail1, efx_rc_t, rc);
519 #endif /* EFSYS_OPT_DIAG */
521 #endif /* EFSYS_OPT_RIVERHEAD */