1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2018-2019 Solarflare Communications Inc.
11 #if EFSYS_OPT_RIVERHEAD
13 __checkReturn efx_rc_t
17 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
22 if ((rc = efx_mcdi_nic_board_cfg(enp)) != 0)
26 * The tunnel encapsulation initialization happens unconditionally
29 encp->enc_tunnel_encapsulations_supported =
30 (1u << EFX_TUNNEL_PROTOCOL_VXLAN) |
31 (1u << EFX_TUNNEL_PROTOCOL_GENEVE) |
32 (1u << EFX_TUNNEL_PROTOCOL_NVGRE);
35 * Software limitation inherited from EF10. This limit is not
36 * increased since the hardware does not report this limit, it is
37 * handled internally resulting in a tunnel add error when there is no
38 * space for more UDP tunnels.
40 encp->enc_tunnel_config_udp_entries_max = EFX_TUNNEL_MAXNENTRIES;
42 encp->enc_clk_mult = 1; /* not used for Riverhead */
45 * FIXME There are TxSend and TxSeg descriptors on Riverhead.
46 * TxSeg is bigger than TxSend.
48 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_GZ_TX_SEND_LEN);
49 /* No boundary crossing limits */
50 encp->enc_tx_dma_desc_boundary = 0;
53 * Initialise design parameters to either a runtime value read from
54 * the design parameters area or the well known default value
55 * (see SF-119689-TC section 4.4 for details).
56 * FIXME: Read design parameters area values.
58 encp->enc_tx_tso_max_header_ndescs =
59 ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT;
60 encp->enc_tx_tso_max_header_length =
61 ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
62 encp->enc_tx_tso_max_payload_ndescs =
63 ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
64 encp->enc_tx_tso_max_payload_length =
65 ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
66 encp->enc_tx_tso_max_nframes =
67 ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
70 * Riverhead does not put any restrictions on TCP header offset limit.
72 encp->enc_tx_tso_tcp_header_offset_limit = UINT32_MAX;
75 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
76 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
77 * resources (allocated to this PCIe function), which is zero until
78 * after we have allocated VIs.
80 encp->enc_evq_limit = 1024;
81 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
82 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
84 encp->enc_buftbl_limit = UINT32_MAX;
87 * Riverhead event queue creation completes
88 * immediately (no initial event).
90 encp->enc_evq_init_done_ev_supported = B_FALSE;
93 * Enable firmware workarounds for hardware errata.
94 * Expected responses are:
96 * Success: workaround enabled or disabled as requested.
97 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
98 * Firmware does not support the MC_CMD_WORKAROUND request.
99 * (assume that the workaround is not supported).
100 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
101 * Firmware does not support the requested workaround.
102 * - MC_CMD_ERR_EPERM (reported as EACCES):
103 * Unprivileged function cannot enable/disable workarounds.
105 * See efx_mcdi_request_errcode() for MCDI error translations.
109 * Replay engine on Riverhead should suppress duplicate packets
110 * (e.g. because of exact multicast and all-multicast filters
111 * match) to the same RxQ.
113 encp->enc_bug26807_workaround = B_FALSE;
116 * Checksums for TSO sends should always be correct on Riverhead.
117 * FIXME: revisit when TSO support is implemented.
119 encp->enc_bug61297_workaround = B_FALSE;
121 encp->enc_evq_max_nevs = RHEAD_EVQ_MAXNEVS;
122 encp->enc_evq_min_nevs = RHEAD_EVQ_MINNEVS;
123 encp->enc_rxq_max_ndescs = RHEAD_RXQ_MAXNDESCS;
124 encp->enc_rxq_min_ndescs = RHEAD_RXQ_MINNDESCS;
125 encp->enc_txq_max_ndescs = RHEAD_TXQ_MAXNDESCS;
126 encp->enc_txq_min_ndescs = RHEAD_TXQ_MINNDESCS;
128 /* Riverhead FW does not support event queue timers yet. */
129 encp->enc_evq_timer_quantum_ns = 0;
130 encp->enc_evq_timer_max_us = 0;
132 #if EFSYS_OPT_EV_EXTENDED_WIDTH
133 encp->enc_ev_ew_desc_size = RHEAD_EVQ_EW_DESC_SIZE;
135 encp->enc_ev_ew_desc_size = 0;
138 encp->enc_ev_desc_size = RHEAD_EVQ_DESC_SIZE;
139 encp->enc_rx_desc_size = RHEAD_RXQ_DESC_SIZE;
140 encp->enc_tx_desc_size = RHEAD_TXQ_DESC_SIZE;
142 /* No required alignment for WPTR updates */
143 encp->enc_rx_push_align = 1;
145 /* Riverhead supports a single Rx prefix size. */
146 encp->enc_rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN;
148 /* Alignment for receive packet DMA buffers. */
149 encp->enc_rx_buf_align_start = 1;
151 /* Get the RX DMA end padding alignment configuration. */
152 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
156 /* Assume largest tail padding size supported by hardware. */
159 encp->enc_rx_buf_align_end = end_padding;
161 /* FIXME: It should be extracted from design parameters (Bug 86844) */
162 encp->enc_rx_scatter_max = 7;
165 * Riverhead stores a single global copy of VPD, not per-PF as on
168 encp->enc_vpd_is_global = B_TRUE;
170 rc = ef10_nic_get_port_mode_bandwidth(enp, &bandwidth);
173 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
174 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
183 EFSYS_PROBE1(fail1, efx_rc_t, rc);
188 __checkReturn efx_rc_t
192 const efx_nic_ops_t *enop = enp->en_enop;
193 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
194 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
197 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp));
199 /* Read and clear any assertion state */
200 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
203 /* Exit the assertion handler */
204 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
208 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
211 /* Get remaining controller-specific board config */
212 if ((rc = enop->eno_board_cfg(enp)) != 0)
216 * Set default driver config limits (based on board config).
218 * FIXME: For now allocate a fixed number of VIs which is likely to be
219 * sufficient and small enough to allow multiple functions on the same
222 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
223 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
226 * The client driver must configure and enable PIO buffer support,
227 * but there is no PIO support on Riverhead anyway.
229 edcp->edc_max_piobuf_count = 0;
230 edcp->edc_pio_alloc_size = 0;
232 #if EFSYS_OPT_MAC_STATS
233 /* Wipe the MAC statistics */
234 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
238 #if EFSYS_OPT_LOOPBACK
239 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
245 #if EFSYS_OPT_LOOPBACK
249 #if EFSYS_OPT_MAC_STATS
260 EFSYS_PROBE1(fail1, efx_rc_t, rc);
265 __checkReturn efx_rc_t
266 rhead_nic_set_drv_limits(
267 __inout efx_nic_t *enp,
268 __in efx_drv_limits_t *edlp)
270 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
271 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
272 uint32_t min_evq_count, max_evq_count;
273 uint32_t min_rxq_count, max_rxq_count;
274 uint32_t min_txq_count, max_txq_count;
282 /* Get minimum required and maximum usable VI limits */
283 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
284 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
285 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
287 edcp->edc_min_vi_count =
288 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
290 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
291 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
292 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
294 edcp->edc_max_vi_count =
295 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
297 /* There is no PIO support on Riverhead */
298 edcp->edc_max_piobuf_count = 0;
299 edcp->edc_pio_alloc_size = 0;
304 EFSYS_PROBE1(fail1, efx_rc_t, rc);
309 __checkReturn efx_rc_t
315 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
316 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
318 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
321 if ((rc = efx_mcdi_entity_reset(enp)) != 0)
324 /* Clear RX/TX DMA queue errors */
325 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
334 EFSYS_PROBE1(fail1, efx_rc_t, rc);
339 __checkReturn efx_rc_t
343 const efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
344 uint32_t min_vi_count, max_vi_count;
345 uint32_t vi_count, vi_base, vi_shift;
346 uint32_t vi_window_size;
348 boolean_t alloc_vadaptor = B_TRUE;
350 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp));
351 EFSYS_ASSERT3U(edcp->edc_max_piobuf_count, ==, 0);
353 /* Enable reporting of some events (e.g. link change) */
354 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
357 min_vi_count = edcp->edc_min_vi_count;
358 max_vi_count = edcp->edc_max_vi_count;
360 /* Ensure that the previously attached driver's VIs are freed */
361 if ((rc = efx_mcdi_free_vis(enp)) != 0)
365 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
366 * fails then retrying the request for fewer VI resources may succeed.
369 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
370 &vi_base, &vi_count, &vi_shift)) != 0)
373 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
375 if (vi_count < min_vi_count) {
380 enp->en_arch.ef10.ena_vi_base = vi_base;
381 enp->en_arch.ef10.ena_vi_count = vi_count;
382 enp->en_arch.ef10.ena_vi_shift = vi_shift;
384 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, !=,
385 EFX_VI_WINDOW_SHIFT_INVALID);
386 EFSYS_ASSERT3U(enp->en_nic_cfg.enc_vi_window_shift, <=,
387 EFX_VI_WINDOW_SHIFT_64K);
388 vi_window_size = 1U << enp->en_nic_cfg.enc_vi_window_shift;
390 /* Save UC memory mapping details */
391 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
392 enp->en_arch.ef10.ena_uc_mem_map_size =
393 vi_window_size * enp->en_arch.ef10.ena_vi_count;
395 /* No WC memory mapping since PIO is not supported */
396 enp->en_arch.ef10.ena_pio_write_vi_base = 0;
397 enp->en_arch.ef10.ena_wc_mem_map_offset = 0;
398 enp->en_arch.ef10.ena_wc_mem_map_size = 0;
400 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
403 * For SR-IOV use case, vAdaptor is allocated for PF and associated VFs
404 * during NIC initialization when vSwitch is created and vPorts are
405 * allocated. Hence, skip vAdaptor allocation for EVB and update vPort
406 * ID in NIC structure with the one allocated for PF.
409 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
411 if ((enp->en_vswitchp != NULL) && (enp->en_vswitchp->ev_evcp != NULL)) {
412 /* For EVB use vPort allocated on vSwitch */
413 enp->en_vport_id = enp->en_vswitchp->ev_evcp->evc_vport_id;
414 alloc_vadaptor = B_FALSE;
417 if (alloc_vadaptor != B_FALSE) {
418 /* Allocate a vAdaptor attached to our upstream vPort/pPort */
419 if ((rc = ef10_upstream_port_vadaptor_alloc(enp)) != 0)
431 (void) efx_mcdi_free_vis(enp);
438 EFSYS_PROBE1(fail1, efx_rc_t, rc);
443 __checkReturn efx_rc_t
444 rhead_nic_get_vi_pool(
446 __out uint32_t *vi_countp)
449 * Report VIs that the client driver can use.
450 * Do not include VIs used for PIO buffer writes.
452 *vi_countp = enp->en_arch.ef10.ena_vi_count;
457 __checkReturn efx_rc_t
458 rhead_nic_get_bar_region(
460 __in efx_nic_region_t region,
461 __out uint32_t *offsetp,
466 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp));
469 * TODO: Specify host memory mapping alignment and granularity
470 * in efx_drv_limits_t so that they can be taken into account
471 * when allocating extra VIs for PIO writes.
475 /* UC mapped memory BAR region for VI registers */
476 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
477 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
480 case EFX_REGION_PIO_WRITE_VI:
481 /* WC mapped memory BAR region for piobuf writes */
482 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
483 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
494 EFSYS_PROBE1(fail1, efx_rc_t, rc);
499 __checkReturn boolean_t
500 rhead_nic_hw_unavailable(
505 if (enp->en_reset_flags & EFX_RESET_HW_UNAVAIL)
508 EFX_BAR_FCW_READD(enp, ER_GZ_MC_SFT_STATUS, &dword);
509 if (EFX_DWORD_FIELD(dword, EFX_DWORD_0) == 0xffffffff)
515 rhead_nic_set_hw_unavailable(enp);
521 rhead_nic_set_hw_unavailable(
524 EFSYS_PROBE(hw_unavail);
525 enp->en_reset_flags |= EFX_RESET_HW_UNAVAIL;
532 boolean_t do_vadaptor_free = B_TRUE;
535 if (enp->en_vswitchp != NULL) {
537 * For SR-IOV the vAdaptor is freed with the vSwitch,
538 * so do not free it here.
540 do_vadaptor_free = B_FALSE;
543 if (do_vadaptor_free != B_FALSE) {
544 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
545 enp->en_vport_id = EVB_PORT_ID_NULL;
548 (void) efx_mcdi_free_vis(enp);
549 enp->en_arch.ef10.ena_vi_count = 0;
556 (void) efx_mcdi_drv_attach(enp, B_FALSE);
561 __checkReturn efx_rc_t
562 rhead_nic_register_test(
568 _NOTE(ARGUNUSED(enp))
569 _NOTE(CONSTANTCONDITION)
579 EFSYS_PROBE1(fail1, efx_rc_t, rc);
584 #endif /* EFSYS_OPT_DIAG */
586 __checkReturn efx_rc_t
587 rhead_nic_xilinx_cap_tbl_read_ef100_locator(
588 __in efsys_bar_t *esbp,
589 __in efsys_dma_addr_t offset,
590 __out efx_bar_region_t *ebrp)
598 * Xilinx Capabilities Table requires 32bit aligned reads.
599 * See SF-119689-TC section 4.2.2 "Discovery Steps".
601 EFSYS_BAR_READD(esbp, offset +
602 (EFX_LOW_BIT(ESF_GZ_CFGBAR_ENTRY_FORMAT) / 8),
603 &entry.eo_dword[0], B_FALSE);
604 EFSYS_BAR_READD(esbp, offset +
605 (EFX_LOW_BIT(ESF_GZ_CFGBAR_ENTRY_SIZE) / 8),
606 &entry.eo_dword[1], B_FALSE);
608 rev = EFX_OWORD_FIELD32(entry, ESF_GZ_CFGBAR_ENTRY_REV);
609 len = EFX_OWORD_FIELD32(entry, ESF_GZ_CFGBAR_ENTRY_SIZE);
611 if (rev != ESE_GZ_CFGBAR_ENTRY_REV_EF100 ||
612 len < ESE_GZ_CFGBAR_ENTRY_SIZE_EF100) {
617 EFSYS_BAR_READD(esbp, offset +
618 (EFX_LOW_BIT(ESF_GZ_CFGBAR_EF100_BAR) / 8),
619 &entry.eo_dword[2], B_FALSE);
621 ebrp->ebr_index = EFX_OWORD_FIELD32(entry, ESF_GZ_CFGBAR_EF100_BAR);
622 ebrp->ebr_offset = EFX_OWORD_FIELD32(entry,
623 ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF) <<
624 ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT;
625 ebrp->ebr_type = EFX_BAR_TYPE_MEM;
626 ebrp->ebr_length = 0;
631 EFSYS_PROBE1(fail1, efx_rc_t, rc);
636 #endif /* EFSYS_OPT_RIVERHEAD */