1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2019 Solarflare Communications Inc.
10 #if EFSYS_OPT_RIVERHEAD && EFSYS_OPT_PCI
12 __checkReturn efx_rc_t
13 rhead_pci_nic_membar_lookup(
14 __in efsys_pci_config_t *espcp,
15 __out efx_bar_region_t *ebrp)
17 boolean_t xilinx_tbl_found = B_FALSE;
18 unsigned int xilinx_tbl_bar;
19 efsys_dma_addr_t xilinx_tbl_offset;
20 size_t pci_capa_offset = 0;
21 boolean_t bar_found = B_FALSE;
26 * SF-119689-TC Riverhead Host Interface section 4.2.2. describes
27 * the following discovery steps.
30 rc = efx_pci_find_next_xilinx_cap_table(espcp, &pci_capa_offset,
35 * SF-119689-TC Riverhead Host Interface section 4.2.2.
36 * defines the following fallbacks for the memory bar
37 * and the offset when no Xilinx capabilities table is
40 if (rc == ENOENT && xilinx_tbl_found == B_FALSE) {
41 ebrp->ebr_type = EFX_BAR_TYPE_MEM;
42 ebrp->ebr_index = EFX_MEM_BAR_RIVERHEAD;
53 xilinx_tbl_found = B_TRUE;
55 EFSYS_PCI_FIND_MEM_BAR(espcp, xilinx_tbl_bar, &xil_eb, &rc);
60 if (bar_found == B_FALSE)
70 EFSYS_PROBE1(fail1, efx_rc_t, rc);
75 #endif /* EFSYS_OPT_RIVERHEAD && EFSYS_OPT_PCI */