1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2009-2019 Solarflare Communications Inc.
13 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
15 static __checkReturn efx_rc_t
16 siena_nic_get_partn_mask(
18 __out unsigned int *maskp)
21 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_NVRAM_TYPES_IN_LEN,
22 MC_CMD_NVRAM_TYPES_OUT_LEN);
25 req.emr_cmd = MC_CMD_NVRAM_TYPES;
26 req.emr_in_buf = payload;
27 req.emr_in_length = MC_CMD_NVRAM_TYPES_IN_LEN;
28 req.emr_out_buf = payload;
29 req.emr_out_length = MC_CMD_NVRAM_TYPES_OUT_LEN;
31 efx_mcdi_execute(enp, &req);
33 if (req.emr_rc != 0) {
38 if (req.emr_out_length_used < MC_CMD_NVRAM_TYPES_OUT_LEN) {
43 *maskp = MCDI_OUT_DWORD(req, NVRAM_TYPES_OUT_TYPES);
50 EFSYS_PROBE1(fail1, efx_rc_t, rc);
55 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
57 static __checkReturn efx_rc_t
61 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
63 efx_dword_t capabilities;
65 uint32_t nevq, nrxq, ntxq;
68 /* Siena has a fixed 8Kbyte VI window size */
69 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
70 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
72 /* External port identifier using one-based port numbering */
73 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
75 /* Board configuration */
76 if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
77 &capabilities, mac_addr)) != 0)
80 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
82 encp->enc_board_type = board_type;
85 * There is no possibility to determine the number of PFs on Siena
86 * by issuing MCDI request, and it is not an easy task to find the
87 * value based on the board type, so 'enc_hw_pf_count' is set to 1
89 encp->enc_hw_pf_count = 1;
91 /* Additional capabilities */
92 encp->enc_clk_mult = 1;
93 if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
94 enp->en_features |= EFX_FEATURE_TURBO;
96 if (EFX_DWORD_FIELD(capabilities,
97 MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
98 encp->enc_clk_mult = 2;
102 encp->enc_evq_timer_quantum_ns =
103 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
104 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
105 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
107 encp->enc_ev_desc_size = SIENA_EVQ_DESC_SIZE;
108 encp->enc_rx_desc_size = SIENA_RXQ_DESC_SIZE;
109 encp->enc_tx_desc_size = SIENA_TXQ_DESC_SIZE;
111 /* When hash header insertion is enabled, Siena inserts 16 bytes */
112 encp->enc_rx_prefix_size = 16;
114 /* Alignment for receive packet DMA buffers */
115 encp->enc_rx_buf_align_start = 1;
116 encp->enc_rx_buf_align_end = 1;
118 /* Alignment for WPTR updates */
119 encp->enc_rx_push_align = 1;
121 #if EFSYS_OPT_RX_SCALE
122 /* There is one RSS context per function */
123 encp->enc_rx_scale_max_exclusive_contexts = 1;
125 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_LFSR);
126 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_TOEPLITZ);
129 * It is always possible to use port numbers
130 * as the input data for hash computation.
132 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
134 /* There is no support for additional RSS modes */
135 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
136 #endif /* EFSYS_OPT_RX_SCALE */
139 * Event queue creation is complete when an
140 * EVQ_INIT_DONE_EV event is received.
142 encp->enc_evq_init_done_ev_supported = B_TRUE;
144 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
145 /* Fragments must not span 4k boundaries. */
146 encp->enc_tx_dma_desc_boundary = 4096;
148 /* Resource limits */
149 rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
155 nrxq = EFX_RXQ_LIMIT_TARGET;
156 ntxq = EFX_TXQ_LIMIT_TARGET;
158 encp->enc_evq_limit = nevq;
159 encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
160 encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
162 encp->enc_evq_max_nevs = SIENA_EVQ_MAXNEVS;
163 encp->enc_evq_min_nevs = SIENA_EVQ_MINNEVS;
165 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
166 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
168 encp->enc_txq_max_ndescs = SIENA_TXQ_MAXNDESCS;
169 encp->enc_txq_min_ndescs = SIENA_TXQ_MINNDESCS;
171 encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
172 (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
173 (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
175 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
176 encp->enc_fw_assisted_tso_enabled = B_FALSE;
177 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
178 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
179 encp->enc_tso_v3_enabled = B_FALSE;
180 encp->enc_rx_scatter_max = -1;
181 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
182 encp->enc_rx_packed_stream_supported = B_FALSE;
183 encp->enc_rx_var_packed_stream_supported = B_FALSE;
184 encp->enc_rx_es_super_buffer_supported = B_FALSE;
185 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
187 /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
188 encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
189 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
191 encp->enc_nvram_update_verify_result_supported = B_FALSE;
193 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
195 encp->enc_filter_action_flag_supported = B_FALSE;
196 encp->enc_filter_action_mark_supported = B_FALSE;
197 encp->enc_filter_action_mark_max = 0;
204 EFSYS_PROBE1(fail1, efx_rc_t, rc);
209 static __checkReturn efx_rc_t
213 #if EFSYS_OPT_PHY_STATS
214 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
215 #endif /* EFSYS_OPT_PHY_STATS */
218 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
219 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
222 #if EFSYS_OPT_PHY_STATS
223 /* Convert the MCDI statistic mask into the EFX_PHY_STAT mask */
224 siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,
225 NULL, &encp->enc_phy_stat_mask, NULL);
226 #endif /* EFSYS_OPT_PHY_STATS */
231 EFSYS_PROBE1(fail1, efx_rc_t, rc);
236 #define SIENA_BIU_MAGIC0 0x01234567
237 #define SIENA_BIU_MAGIC1 0xfedcba98
239 static __checkReturn efx_rc_t
247 * Write magic values to scratch registers 0 and 1, then
248 * verify that the values were written correctly. Interleave
249 * the accesses to ensure that the BIU is not just reading
250 * back the cached value that was last written.
252 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
253 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
255 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
256 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
258 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
259 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
264 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
265 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
271 * Perform the same test, with the values swapped. This
272 * ensures that subsequent tests don't start with the correct
273 * values already written into the scratch registers.
275 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
276 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
278 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
279 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
281 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
282 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
287 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
288 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
302 EFSYS_PROBE1(fail1, efx_rc_t, rc);
307 __checkReturn efx_rc_t
311 efx_port_t *epp = &(enp->en_port);
312 siena_link_state_t sls;
317 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
320 if ((rc = siena_nic_biu_test(enp)) != 0)
323 /* Clear the region register */
324 EFX_POPULATE_OWORD_4(oword,
325 FRF_AZ_ADR_REGION0, 0,
326 FRF_AZ_ADR_REGION1, (1 << 16),
327 FRF_AZ_ADR_REGION2, (2 << 16),
328 FRF_AZ_ADR_REGION3, (3 << 16));
329 EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
331 /* Read clear any assertion state */
332 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
335 /* Exit the assertion handler */
336 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
339 /* Wrestle control from the BMC */
340 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
343 if ((rc = siena_board_cfg(enp)) != 0)
346 if ((rc = siena_phy_cfg(enp)) != 0)
349 /* Obtain the default PHY advertised capabilities */
350 if ((rc = siena_nic_reset(enp)) != 0)
352 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
354 epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;
355 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
357 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
358 if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0)
360 enp->en_u.siena.enu_partn_mask = mask;
363 #if EFSYS_OPT_MAC_STATS
364 /* Wipe the MAC statistics */
365 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
369 #if EFSYS_OPT_LOOPBACK
370 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
374 #if EFSYS_OPT_MON_STATS
375 if ((rc = mcdi_mon_cfg_build(enp)) != 0)
381 #if EFSYS_OPT_MON_STATS
385 #if EFSYS_OPT_LOOPBACK
389 #if EFSYS_OPT_MAC_STATS
393 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
412 EFSYS_PROBE1(fail1, efx_rc_t, rc);
417 __checkReturn efx_rc_t
424 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
426 /* siena_nic_reset() is called to recover from BADASSERT failures. */
427 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
429 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
433 * Bug24908: ENTITY_RESET_IN_LEN is non zero but zero may be supplied
434 * for backwards compatibility with PORT_RESET_IN_LEN.
436 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
438 req.emr_cmd = MC_CMD_ENTITY_RESET;
439 req.emr_in_buf = NULL;
440 req.emr_in_length = 0;
441 req.emr_out_buf = NULL;
442 req.emr_out_length = 0;
444 efx_mcdi_execute(enp, &req);
446 if (req.emr_rc != 0) {
458 EFSYS_PROBE1(fail1, efx_rc_t, rc);
470 * RX_INGR_EN is always enabled on Siena, because we rely on
471 * the RX parser to be resiliant to missing SOP/EOP.
473 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
474 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1);
475 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
477 /* Disable parsing of additional 802.1Q in Q packets */
478 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
479 EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0);
480 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
489 EFX_POPULATE_OWORD_1(oword, FRF_CZ_USREV_DIS, 1);
490 EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword);
493 __checkReturn efx_rc_t
499 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
501 /* Enable reporting of some events (e.g. link change) */
502 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
505 siena_sram_init(enp);
507 /* Configure Siena's RX block */
508 siena_nic_rx_cfg(enp);
510 /* Disable USR_EVents for now */
511 siena_nic_usrev_dis(enp);
513 /* bug17057: Ensure set_link is called */
514 if ((rc = siena_phy_reconfigure(enp)) != 0)
517 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1;
524 EFSYS_PROBE1(fail1, efx_rc_t, rc);
533 _NOTE(ARGUNUSED(enp))
540 #if EFSYS_OPT_MON_STATS
541 mcdi_mon_cfg_free(enp);
542 #endif /* EFSYS_OPT_MON_STATS */
543 (void) efx_mcdi_drv_attach(enp, B_FALSE);
548 static siena_register_set_t __siena_registers[] = {
549 { FR_AZ_ADR_REGION_REG_OFST, 0, 1 },
550 { FR_CZ_USR_EV_CFG_OFST, 0, 1 },
551 { FR_AZ_RX_CFG_REG_OFST, 0, 1 },
552 { FR_AZ_TX_CFG_REG_OFST, 0, 1 },
553 { FR_AZ_TX_RESERVED_REG_OFST, 0, 1 },
554 { FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 },
555 { FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 },
556 { FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 },
557 { FR_AZ_DP_CTRL_REG_OFST, 0, 1 },
558 { FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1},
559 { FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1},
560 { FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1},
561 { FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1}
564 static const uint32_t __siena_register_masks[] = {
565 0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF,
566 0x000103FF, 0x00000000, 0x00000000, 0x00000000,
567 0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000,
568 0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF,
569 0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF,
570 0x001FFFFF, 0x00000000, 0x00000000, 0x00000000,
571 0x00000003, 0x00000000, 0x00000000, 0x00000000,
572 0x000003FF, 0x00000000, 0x00000000, 0x00000000,
573 0x00000FFF, 0x00000000, 0x00000000, 0x00000000,
574 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
575 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
576 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
577 0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000
580 static siena_register_set_t __siena_tables[] = {
581 { FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP,
582 FR_AZ_RX_FILTER_TBL0_ROWS },
583 { FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP,
584 FR_CZ_RX_MAC_FILTER_TBL0_ROWS },
585 { FR_AZ_RX_DESC_PTR_TBL_OFST,
586 FR_AZ_RX_DESC_PTR_TBL_STEP, FR_CZ_RX_DESC_PTR_TBL_ROWS },
587 { FR_AZ_TX_DESC_PTR_TBL_OFST,
588 FR_AZ_TX_DESC_PTR_TBL_STEP, FR_CZ_TX_DESC_PTR_TBL_ROWS },
589 { FR_AZ_TIMER_TBL_OFST, FR_AZ_TIMER_TBL_STEP, FR_CZ_TIMER_TBL_ROWS },
590 { FR_CZ_TX_FILTER_TBL0_OFST,
591 FR_CZ_TX_FILTER_TBL0_STEP, FR_CZ_TX_FILTER_TBL0_ROWS },
592 { FR_CZ_TX_MAC_FILTER_TBL0_OFST,
593 FR_CZ_TX_MAC_FILTER_TBL0_STEP, FR_CZ_TX_MAC_FILTER_TBL0_ROWS }
596 static const uint32_t __siena_table_masks[] = {
597 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF,
598 0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000,
599 0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000,
600 0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000,
601 0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000,
602 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF,
603 0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,
606 __checkReturn efx_rc_t
607 siena_nic_test_registers(
609 __in siena_register_set_t *rsp,
613 efx_oword_t original;
619 /* This function is only suitable for registers */
620 EFSYS_ASSERT(rsp->rows == 1);
622 /* bit sweep on and off */
623 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,
625 for (bit = 0; bit < 128; bit++) {
626 /* Is this bit in the mask? */
627 if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))
630 /* Test this bit can be set in isolation */
632 EFX_AND_OWORD(reg, rsp->mask);
633 EFX_SET_OWORD_BIT(reg, bit);
635 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
637 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
640 EFX_AND_OWORD(buf, rsp->mask);
641 if (memcmp(®, &buf, sizeof (reg))) {
646 /* Test this bit can be cleared in isolation */
647 EFX_OR_OWORD(reg, rsp->mask);
648 EFX_CLEAR_OWORD_BIT(reg, bit);
650 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
652 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
655 EFX_AND_OWORD(buf, rsp->mask);
656 if (memcmp(®, &buf, sizeof (reg))) {
662 /* Restore the old value */
663 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,
675 EFSYS_PROBE1(fail1, efx_rc_t, rc);
677 /* Restore the old value */
678 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);
683 __checkReturn efx_rc_t
684 siena_nic_test_tables(
686 __in siena_register_set_t *rsp,
687 __in efx_pattern_type_t pattern,
690 efx_sram_pattern_fn_t func;
692 unsigned int address;
697 EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);
698 func = __efx_sram_pattern_fns[pattern];
702 address = rsp->address;
703 for (index = 0; index < rsp->rows; ++index) {
704 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
705 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
706 EFX_AND_OWORD(reg, rsp->mask);
707 EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE);
709 address += rsp->step;
713 address = rsp->address;
714 for (index = 0; index < rsp->rows; ++index) {
715 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
716 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
717 EFX_AND_OWORD(reg, rsp->mask);
718 EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);
719 if (memcmp(®, &buf, sizeof (reg))) {
724 address += rsp->step;
734 EFSYS_PROBE1(fail1, efx_rc_t, rc);
740 __checkReturn efx_rc_t
741 siena_nic_register_test(
744 siena_register_set_t *rsp;
745 const uint32_t *dwordp;
750 /* Fill out the register mask entries */
751 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)
752 == EFX_ARRAY_SIZE(__siena_registers) * 4);
754 nitems = EFX_ARRAY_SIZE(__siena_registers);
755 dwordp = __siena_register_masks;
756 for (count = 0; count < nitems; ++count) {
757 rsp = __siena_registers + count;
758 rsp->mask.eo_u32[0] = *dwordp++;
759 rsp->mask.eo_u32[1] = *dwordp++;
760 rsp->mask.eo_u32[2] = *dwordp++;
761 rsp->mask.eo_u32[3] = *dwordp++;
764 /* Fill out the register table entries */
765 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)
766 == EFX_ARRAY_SIZE(__siena_tables) * 4);
768 nitems = EFX_ARRAY_SIZE(__siena_tables);
769 dwordp = __siena_table_masks;
770 for (count = 0; count < nitems; ++count) {
771 rsp = __siena_tables + count;
772 rsp->mask.eo_u32[0] = *dwordp++;
773 rsp->mask.eo_u32[1] = *dwordp++;
774 rsp->mask.eo_u32[2] = *dwordp++;
775 rsp->mask.eo_u32[3] = *dwordp++;
778 if ((rc = siena_nic_test_registers(enp, __siena_registers,
779 EFX_ARRAY_SIZE(__siena_registers))) != 0)
782 if ((rc = siena_nic_test_tables(enp, __siena_tables,
783 EFX_PATTERN_BYTE_ALTERNATE,
784 EFX_ARRAY_SIZE(__siena_tables))) != 0)
787 if ((rc = siena_nic_test_tables(enp, __siena_tables,
788 EFX_PATTERN_BYTE_CHANGING,
789 EFX_ARRAY_SIZE(__siena_tables))) != 0)
792 if ((rc = siena_nic_test_tables(enp, __siena_tables,
793 EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0)
805 EFSYS_PROBE1(fail1, efx_rc_t, rc);
810 #endif /* EFSYS_OPT_DIAG */
812 #endif /* EFSYS_OPT_SIENA */