1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2009-2019 Solarflare Communications Inc.
13 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
15 static __checkReturn efx_rc_t
16 siena_nic_get_partn_mask(
18 __out unsigned int *maskp)
21 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_NVRAM_TYPES_IN_LEN,
22 MC_CMD_NVRAM_TYPES_OUT_LEN);
25 req.emr_cmd = MC_CMD_NVRAM_TYPES;
26 req.emr_in_buf = payload;
27 req.emr_in_length = MC_CMD_NVRAM_TYPES_IN_LEN;
28 req.emr_out_buf = payload;
29 req.emr_out_length = MC_CMD_NVRAM_TYPES_OUT_LEN;
31 efx_mcdi_execute(enp, &req);
33 if (req.emr_rc != 0) {
38 if (req.emr_out_length_used < MC_CMD_NVRAM_TYPES_OUT_LEN) {
43 *maskp = MCDI_OUT_DWORD(req, NVRAM_TYPES_OUT_TYPES);
50 EFSYS_PROBE1(fail1, efx_rc_t, rc);
55 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
57 static __checkReturn efx_rc_t
61 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
63 efx_dword_t capabilities;
65 uint32_t nevq, nrxq, ntxq;
68 /* Siena has a fixed 8Kbyte VI window size */
69 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
70 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
72 /* External port identifier using one-based port numbering */
73 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
75 /* Board configuration */
76 if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
77 &capabilities, mac_addr)) != 0)
80 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
82 encp->enc_board_type = board_type;
85 * There is no possibility to determine the number of PFs on Siena
86 * by issuing MCDI request, and it is not an easy task to find the
87 * value based on the board type, so 'enc_hw_pf_count' is set to 1
89 encp->enc_hw_pf_count = 1;
91 /* Additional capabilities */
92 encp->enc_clk_mult = 1;
93 if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
94 enp->en_features |= EFX_FEATURE_TURBO;
96 if (EFX_DWORD_FIELD(capabilities,
97 MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
98 encp->enc_clk_mult = 2;
102 encp->enc_evq_timer_quantum_ns =
103 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
104 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
105 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
107 encp->enc_ev_desc_size = SIENA_EVQ_DESC_SIZE;
108 encp->enc_rx_desc_size = SIENA_RXQ_DESC_SIZE;
109 encp->enc_tx_desc_size = SIENA_TXQ_DESC_SIZE;
111 /* When hash header insertion is enabled, Siena inserts 16 bytes */
112 encp->enc_rx_prefix_size = 16;
114 /* Alignment for receive packet DMA buffers */
115 encp->enc_rx_buf_align_start = 1;
116 encp->enc_rx_buf_align_end = 1;
118 /* Alignment for WPTR updates */
119 encp->enc_rx_push_align = 1;
121 #if EFSYS_OPT_RX_SCALE
122 encp->enc_rx_scale_indirection_max_nqueues = EFX_MAXRSS;
124 /* There is one RSS context per function */
125 encp->enc_rx_scale_max_exclusive_contexts = 1;
127 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_LFSR);
128 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_TOEPLITZ);
131 * It is always possible to use port numbers
132 * as the input data for hash computation.
134 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
136 /* There is no support for additional RSS modes */
137 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
138 #endif /* EFSYS_OPT_RX_SCALE */
141 * Event queue creation is complete when an
142 * EVQ_INIT_DONE_EV event is received.
144 encp->enc_evq_init_done_ev_supported = B_TRUE;
146 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
147 /* Fragments must not span 4k boundaries. */
148 encp->enc_tx_dma_desc_boundary = 4096;
150 /* Resource limits */
151 rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
157 nrxq = EFX_RXQ_LIMIT_TARGET;
158 ntxq = EFX_TXQ_LIMIT_TARGET;
160 encp->enc_evq_limit = nevq;
161 encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
162 encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
164 encp->enc_evq_max_nevs = SIENA_EVQ_MAXNEVS;
165 encp->enc_evq_min_nevs = SIENA_EVQ_MINNEVS;
167 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
168 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
170 encp->enc_txq_max_ndescs = SIENA_TXQ_MAXNDESCS;
171 encp->enc_txq_min_ndescs = SIENA_TXQ_MINNDESCS;
173 encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
174 (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
175 (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
177 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
178 encp->enc_fw_assisted_tso_enabled = B_FALSE;
179 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
180 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
181 encp->enc_tso_v3_enabled = B_FALSE;
182 encp->enc_rx_scatter_max = -1;
183 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
184 encp->enc_rx_packed_stream_supported = B_FALSE;
185 encp->enc_rx_var_packed_stream_supported = B_FALSE;
186 encp->enc_rx_es_super_buffer_supported = B_FALSE;
187 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
189 /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
190 encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
191 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
193 encp->enc_nvram_update_verify_result_supported = B_FALSE;
195 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
197 encp->enc_filter_action_flag_supported = B_FALSE;
198 encp->enc_filter_action_mark_supported = B_FALSE;
199 encp->enc_filter_action_mark_max = 0;
201 encp->enc_mae_supported = B_FALSE;
202 encp->enc_mae_admin = B_FALSE;
204 encp->enc_dma_mapping = EFX_NIC_DMA_MAPPING_FLAT;
211 EFSYS_PROBE1(fail1, efx_rc_t, rc);
216 static __checkReturn efx_rc_t
220 #if EFSYS_OPT_PHY_STATS
221 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
222 #endif /* EFSYS_OPT_PHY_STATS */
225 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
226 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
229 #if EFSYS_OPT_PHY_STATS
230 /* Convert the MCDI statistic mask into the EFX_PHY_STAT mask */
231 siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,
232 NULL, &encp->enc_phy_stat_mask, NULL);
233 #endif /* EFSYS_OPT_PHY_STATS */
238 EFSYS_PROBE1(fail1, efx_rc_t, rc);
243 #define SIENA_BIU_MAGIC0 0x01234567
244 #define SIENA_BIU_MAGIC1 0xfedcba98
246 static __checkReturn efx_rc_t
254 * Write magic values to scratch registers 0 and 1, then
255 * verify that the values were written correctly. Interleave
256 * the accesses to ensure that the BIU is not just reading
257 * back the cached value that was last written.
259 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
260 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
262 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
263 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
265 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
266 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
271 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
272 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
278 * Perform the same test, with the values swapped. This
279 * ensures that subsequent tests don't start with the correct
280 * values already written into the scratch registers.
282 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
283 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
285 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
286 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
288 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
289 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
294 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
295 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
309 EFSYS_PROBE1(fail1, efx_rc_t, rc);
314 __checkReturn efx_rc_t
318 efx_port_t *epp = &(enp->en_port);
319 siena_link_state_t sls;
324 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
327 if ((rc = siena_nic_biu_test(enp)) != 0)
330 /* Clear the region register */
331 EFX_POPULATE_OWORD_4(oword,
332 FRF_AZ_ADR_REGION0, 0,
333 FRF_AZ_ADR_REGION1, (1 << 16),
334 FRF_AZ_ADR_REGION2, (2 << 16),
335 FRF_AZ_ADR_REGION3, (3 << 16));
336 EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
338 /* Read clear any assertion state */
339 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
342 /* Exit the assertion handler */
343 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
346 /* Wrestle control from the BMC */
347 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
350 if ((rc = siena_board_cfg(enp)) != 0)
353 if ((rc = siena_phy_cfg(enp)) != 0)
356 /* Obtain the default PHY advertised capabilities */
357 if ((rc = siena_nic_reset(enp)) != 0)
359 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
361 epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;
362 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
364 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
365 if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0)
367 enp->en_u.siena.enu_partn_mask = mask;
370 #if EFSYS_OPT_MAC_STATS
371 /* Wipe the MAC statistics */
372 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
376 #if EFSYS_OPT_LOOPBACK
377 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
381 #if EFSYS_OPT_MON_STATS
382 if ((rc = mcdi_mon_cfg_build(enp)) != 0)
388 #if EFSYS_OPT_MON_STATS
392 #if EFSYS_OPT_LOOPBACK
396 #if EFSYS_OPT_MAC_STATS
400 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
419 EFSYS_PROBE1(fail1, efx_rc_t, rc);
424 __checkReturn efx_rc_t
431 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
433 /* siena_nic_reset() is called to recover from BADASSERT failures. */
434 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
436 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
440 * Bug24908: ENTITY_RESET_IN_LEN is non zero but zero may be supplied
441 * for backwards compatibility with PORT_RESET_IN_LEN.
443 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
445 req.emr_cmd = MC_CMD_ENTITY_RESET;
446 req.emr_in_buf = NULL;
447 req.emr_in_length = 0;
448 req.emr_out_buf = NULL;
449 req.emr_out_length = 0;
451 efx_mcdi_execute(enp, &req);
453 if (req.emr_rc != 0) {
465 EFSYS_PROBE1(fail1, efx_rc_t, rc);
477 * RX_INGR_EN is always enabled on Siena, because we rely on
478 * the RX parser to be resiliant to missing SOP/EOP.
480 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
481 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1);
482 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
484 /* Disable parsing of additional 802.1Q in Q packets */
485 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
486 EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0);
487 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
496 EFX_POPULATE_OWORD_1(oword, FRF_CZ_USREV_DIS, 1);
497 EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword);
500 __checkReturn efx_rc_t
506 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
508 /* Enable reporting of some events (e.g. link change) */
509 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
512 siena_sram_init(enp);
514 /* Configure Siena's RX block */
515 siena_nic_rx_cfg(enp);
517 /* Disable USR_EVents for now */
518 siena_nic_usrev_dis(enp);
520 /* bug17057: Ensure set_link is called */
521 if ((rc = siena_phy_reconfigure(enp)) != 0)
524 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1;
531 EFSYS_PROBE1(fail1, efx_rc_t, rc);
540 _NOTE(ARGUNUSED(enp))
547 #if EFSYS_OPT_MON_STATS
548 mcdi_mon_cfg_free(enp);
549 #endif /* EFSYS_OPT_MON_STATS */
550 (void) efx_mcdi_drv_attach(enp, B_FALSE);
555 static siena_register_set_t __siena_registers[] = {
556 { FR_AZ_ADR_REGION_REG_OFST, 0, 1 },
557 { FR_CZ_USR_EV_CFG_OFST, 0, 1 },
558 { FR_AZ_RX_CFG_REG_OFST, 0, 1 },
559 { FR_AZ_TX_CFG_REG_OFST, 0, 1 },
560 { FR_AZ_TX_RESERVED_REG_OFST, 0, 1 },
561 { FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 },
562 { FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 },
563 { FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 },
564 { FR_AZ_DP_CTRL_REG_OFST, 0, 1 },
565 { FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1},
566 { FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1},
567 { FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1},
568 { FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1}
571 static const uint32_t __siena_register_masks[] = {
572 0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF,
573 0x000103FF, 0x00000000, 0x00000000, 0x00000000,
574 0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000,
575 0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF,
576 0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF,
577 0x001FFFFF, 0x00000000, 0x00000000, 0x00000000,
578 0x00000003, 0x00000000, 0x00000000, 0x00000000,
579 0x000003FF, 0x00000000, 0x00000000, 0x00000000,
580 0x00000FFF, 0x00000000, 0x00000000, 0x00000000,
581 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
582 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
583 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
584 0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000
587 static siena_register_set_t __siena_tables[] = {
588 { FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP,
589 FR_AZ_RX_FILTER_TBL0_ROWS },
590 { FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP,
591 FR_CZ_RX_MAC_FILTER_TBL0_ROWS },
592 { FR_AZ_RX_DESC_PTR_TBL_OFST,
593 FR_AZ_RX_DESC_PTR_TBL_STEP, FR_CZ_RX_DESC_PTR_TBL_ROWS },
594 { FR_AZ_TX_DESC_PTR_TBL_OFST,
595 FR_AZ_TX_DESC_PTR_TBL_STEP, FR_CZ_TX_DESC_PTR_TBL_ROWS },
596 { FR_AZ_TIMER_TBL_OFST, FR_AZ_TIMER_TBL_STEP, FR_CZ_TIMER_TBL_ROWS },
597 { FR_CZ_TX_FILTER_TBL0_OFST,
598 FR_CZ_TX_FILTER_TBL0_STEP, FR_CZ_TX_FILTER_TBL0_ROWS },
599 { FR_CZ_TX_MAC_FILTER_TBL0_OFST,
600 FR_CZ_TX_MAC_FILTER_TBL0_STEP, FR_CZ_TX_MAC_FILTER_TBL0_ROWS }
603 static const uint32_t __siena_table_masks[] = {
604 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF,
605 0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000,
606 0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000,
607 0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000,
608 0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000,
609 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF,
610 0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,
613 __checkReturn efx_rc_t
614 siena_nic_test_registers(
616 __in siena_register_set_t *rsp,
620 efx_oword_t original;
626 /* This function is only suitable for registers */
627 EFSYS_ASSERT(rsp->rows == 1);
629 /* bit sweep on and off */
630 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,
632 for (bit = 0; bit < 128; bit++) {
633 /* Is this bit in the mask? */
634 if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))
637 /* Test this bit can be set in isolation */
639 EFX_AND_OWORD(reg, rsp->mask);
640 EFX_SET_OWORD_BIT(reg, bit);
642 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
644 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
647 EFX_AND_OWORD(buf, rsp->mask);
648 if (memcmp(®, &buf, sizeof (reg))) {
653 /* Test this bit can be cleared in isolation */
654 EFX_OR_OWORD(reg, rsp->mask);
655 EFX_CLEAR_OWORD_BIT(reg, bit);
657 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
659 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
662 EFX_AND_OWORD(buf, rsp->mask);
663 if (memcmp(®, &buf, sizeof (reg))) {
669 /* Restore the old value */
670 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,
682 EFSYS_PROBE1(fail1, efx_rc_t, rc);
684 /* Restore the old value */
685 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);
690 __checkReturn efx_rc_t
691 siena_nic_test_tables(
693 __in siena_register_set_t *rsp,
694 __in efx_pattern_type_t pattern,
697 efx_sram_pattern_fn_t func;
699 unsigned int address;
704 EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);
705 func = __efx_sram_pattern_fns[pattern];
709 address = rsp->address;
710 for (index = 0; index < rsp->rows; ++index) {
711 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
712 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
713 EFX_AND_OWORD(reg, rsp->mask);
714 EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE);
716 address += rsp->step;
720 address = rsp->address;
721 for (index = 0; index < rsp->rows; ++index) {
722 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
723 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
724 EFX_AND_OWORD(reg, rsp->mask);
725 EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);
726 if (memcmp(®, &buf, sizeof (reg))) {
731 address += rsp->step;
741 EFSYS_PROBE1(fail1, efx_rc_t, rc);
747 __checkReturn efx_rc_t
748 siena_nic_register_test(
751 siena_register_set_t *rsp;
752 const uint32_t *dwordp;
757 /* Fill out the register mask entries */
758 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)
759 == EFX_ARRAY_SIZE(__siena_registers) * 4);
761 nitems = EFX_ARRAY_SIZE(__siena_registers);
762 dwordp = __siena_register_masks;
763 for (count = 0; count < nitems; ++count) {
764 rsp = __siena_registers + count;
765 rsp->mask.eo_u32[0] = *dwordp++;
766 rsp->mask.eo_u32[1] = *dwordp++;
767 rsp->mask.eo_u32[2] = *dwordp++;
768 rsp->mask.eo_u32[3] = *dwordp++;
771 /* Fill out the register table entries */
772 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)
773 == EFX_ARRAY_SIZE(__siena_tables) * 4);
775 nitems = EFX_ARRAY_SIZE(__siena_tables);
776 dwordp = __siena_table_masks;
777 for (count = 0; count < nitems; ++count) {
778 rsp = __siena_tables + count;
779 rsp->mask.eo_u32[0] = *dwordp++;
780 rsp->mask.eo_u32[1] = *dwordp++;
781 rsp->mask.eo_u32[2] = *dwordp++;
782 rsp->mask.eo_u32[3] = *dwordp++;
785 if ((rc = siena_nic_test_registers(enp, __siena_registers,
786 EFX_ARRAY_SIZE(__siena_registers))) != 0)
789 if ((rc = siena_nic_test_tables(enp, __siena_tables,
790 EFX_PATTERN_BYTE_ALTERNATE,
791 EFX_ARRAY_SIZE(__siena_tables))) != 0)
794 if ((rc = siena_nic_test_tables(enp, __siena_tables,
795 EFX_PATTERN_BYTE_CHANGING,
796 EFX_ARRAY_SIZE(__siena_tables))) != 0)
799 if ((rc = siena_nic_test_tables(enp, __siena_tables,
800 EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0)
812 EFSYS_PROBE1(fail1, efx_rc_t, rc);
817 #endif /* EFSYS_OPT_DIAG */
819 #endif /* EFSYS_OPT_SIENA */