1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2009-2019 Solarflare Communications Inc.
13 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
15 static __checkReturn efx_rc_t
16 siena_nic_get_partn_mask(
18 __out unsigned int *maskp)
21 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_NVRAM_TYPES_IN_LEN,
22 MC_CMD_NVRAM_TYPES_OUT_LEN);
25 req.emr_cmd = MC_CMD_NVRAM_TYPES;
26 req.emr_in_buf = payload;
27 req.emr_in_length = MC_CMD_NVRAM_TYPES_IN_LEN;
28 req.emr_out_buf = payload;
29 req.emr_out_length = MC_CMD_NVRAM_TYPES_OUT_LEN;
31 efx_mcdi_execute(enp, &req);
33 if (req.emr_rc != 0) {
38 if (req.emr_out_length_used < MC_CMD_NVRAM_TYPES_OUT_LEN) {
43 *maskp = MCDI_OUT_DWORD(req, NVRAM_TYPES_OUT_TYPES);
50 EFSYS_PROBE1(fail1, efx_rc_t, rc);
55 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
57 static __checkReturn efx_rc_t
61 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
63 efx_dword_t capabilities;
65 uint32_t nevq, nrxq, ntxq;
68 /* Siena has a fixed 8Kbyte VI window size */
69 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
70 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
72 /* External port identifier using one-based port numbering */
73 encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
75 /* Board configuration */
76 if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
77 &capabilities, mac_addr)) != 0)
80 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
82 encp->enc_board_type = board_type;
85 * There is no possibility to determine the number of PFs on Siena
86 * by issuing MCDI request, and it is not an easy task to find the
87 * value based on the board type, so 'enc_hw_pf_count' is set to 1
89 encp->enc_hw_pf_count = 1;
91 /* Additional capabilities */
92 encp->enc_clk_mult = 1;
93 if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
94 enp->en_features |= EFX_FEATURE_TURBO;
96 if (EFX_DWORD_FIELD(capabilities,
97 MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
98 encp->enc_clk_mult = 2;
102 encp->enc_evq_timer_quantum_ns =
103 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
104 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
105 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
107 encp->enc_ev_desc_size = SIENA_EVQ_DESC_SIZE;
108 encp->enc_rx_desc_size = SIENA_RXQ_DESC_SIZE;
109 encp->enc_tx_desc_size = SIENA_TXQ_DESC_SIZE;
111 /* When hash header insertion is enabled, Siena inserts 16 bytes */
112 encp->enc_rx_prefix_size = 16;
114 /* Alignment for receive packet DMA buffers */
115 encp->enc_rx_buf_align_start = 1;
116 encp->enc_rx_buf_align_end = 1;
118 /* Alignment for WPTR updates */
119 encp->enc_rx_push_align = 1;
121 #if EFSYS_OPT_RX_SCALE
122 /* There is one RSS context per function */
123 encp->enc_rx_scale_max_exclusive_contexts = 1;
125 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_LFSR);
126 encp->enc_rx_scale_hash_alg_mask |= (1U << EFX_RX_HASHALG_TOEPLITZ);
129 * It is always possible to use port numbers
130 * as the input data for hash computation.
132 encp->enc_rx_scale_l4_hash_supported = B_TRUE;
134 /* There is no support for additional RSS modes */
135 encp->enc_rx_scale_additional_modes_supported = B_FALSE;
136 #endif /* EFSYS_OPT_RX_SCALE */
139 * Event queue creation is complete when an
140 * EVQ_INIT_DONE_EV event is received.
142 encp->enc_evq_init_done_ev_supported = B_TRUE;
144 encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
145 /* Fragments must not span 4k boundaries. */
146 encp->enc_tx_dma_desc_boundary = 4096;
148 /* Resource limits */
149 rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
155 nrxq = EFX_RXQ_LIMIT_TARGET;
156 ntxq = EFX_TXQ_LIMIT_TARGET;
158 encp->enc_evq_limit = nevq;
159 encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
160 encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
162 encp->enc_evq_max_nevs = SIENA_EVQ_MAXNEVS;
163 encp->enc_evq_min_nevs = SIENA_EVQ_MINNEVS;
165 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
166 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
168 encp->enc_txq_max_ndescs = SIENA_TXQ_MAXNDESCS;
169 encp->enc_txq_min_ndescs = SIENA_TXQ_MINNDESCS;
171 encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
172 (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
173 (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
175 encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
176 encp->enc_fw_assisted_tso_enabled = B_FALSE;
177 encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
178 encp->enc_fw_assisted_tso_v2_n_contexts = 0;
179 encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
180 encp->enc_rx_packed_stream_supported = B_FALSE;
181 encp->enc_rx_var_packed_stream_supported = B_FALSE;
182 encp->enc_rx_es_super_buffer_supported = B_FALSE;
183 encp->enc_fw_subvariant_no_tx_csum_supported = B_FALSE;
185 /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
186 encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
187 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
189 encp->enc_nvram_update_verify_result_supported = B_FALSE;
191 encp->enc_mac_stats_nstats = MC_CMD_MAC_NSTATS;
193 encp->enc_filter_action_flag_supported = B_FALSE;
194 encp->enc_filter_action_mark_supported = B_FALSE;
195 encp->enc_filter_action_mark_max = 0;
202 EFSYS_PROBE1(fail1, efx_rc_t, rc);
207 static __checkReturn efx_rc_t
211 #if EFSYS_OPT_PHY_STATS
212 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
213 #endif /* EFSYS_OPT_PHY_STATS */
216 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
217 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
220 #if EFSYS_OPT_PHY_STATS
221 /* Convert the MCDI statistic mask into the EFX_PHY_STAT mask */
222 siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,
223 NULL, &encp->enc_phy_stat_mask, NULL);
224 #endif /* EFSYS_OPT_PHY_STATS */
229 EFSYS_PROBE1(fail1, efx_rc_t, rc);
234 #define SIENA_BIU_MAGIC0 0x01234567
235 #define SIENA_BIU_MAGIC1 0xfedcba98
237 static __checkReturn efx_rc_t
245 * Write magic values to scratch registers 0 and 1, then
246 * verify that the values were written correctly. Interleave
247 * the accesses to ensure that the BIU is not just reading
248 * back the cached value that was last written.
250 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
251 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
253 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
254 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
256 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
257 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
262 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
263 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
269 * Perform the same test, with the values swapped. This
270 * ensures that subsequent tests don't start with the correct
271 * values already written into the scratch registers.
273 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC1);
274 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
276 EFX_POPULATE_OWORD_1(oword, FRF_AZ_DRIVER_DW0, SIENA_BIU_MAGIC0);
277 EFX_BAR_TBL_WRITEO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
279 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 0, &oword, B_TRUE);
280 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC1) {
285 EFX_BAR_TBL_READO(enp, FR_AZ_DRIVER_REG, 1, &oword, B_TRUE);
286 if (EFX_OWORD_FIELD(oword, FRF_AZ_DRIVER_DW0) != SIENA_BIU_MAGIC0) {
300 EFSYS_PROBE1(fail1, efx_rc_t, rc);
305 __checkReturn efx_rc_t
309 efx_port_t *epp = &(enp->en_port);
310 siena_link_state_t sls;
315 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
318 if ((rc = siena_nic_biu_test(enp)) != 0)
321 /* Clear the region register */
322 EFX_POPULATE_OWORD_4(oword,
323 FRF_AZ_ADR_REGION0, 0,
324 FRF_AZ_ADR_REGION1, (1 << 16),
325 FRF_AZ_ADR_REGION2, (2 << 16),
326 FRF_AZ_ADR_REGION3, (3 << 16));
327 EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
329 /* Read clear any assertion state */
330 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
333 /* Exit the assertion handler */
334 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
337 /* Wrestle control from the BMC */
338 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
341 if ((rc = siena_board_cfg(enp)) != 0)
344 if ((rc = siena_phy_cfg(enp)) != 0)
347 /* Obtain the default PHY advertised capabilities */
348 if ((rc = siena_nic_reset(enp)) != 0)
350 if ((rc = siena_phy_get_link(enp, &sls)) != 0)
352 epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;
353 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
355 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
356 if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0)
358 enp->en_u.siena.enu_partn_mask = mask;
361 #if EFSYS_OPT_MAC_STATS
362 /* Wipe the MAC statistics */
363 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
367 #if EFSYS_OPT_LOOPBACK
368 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
372 #if EFSYS_OPT_MON_STATS
373 if ((rc = mcdi_mon_cfg_build(enp)) != 0)
379 #if EFSYS_OPT_MON_STATS
383 #if EFSYS_OPT_LOOPBACK
387 #if EFSYS_OPT_MAC_STATS
391 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
410 EFSYS_PROBE1(fail1, efx_rc_t, rc);
415 __checkReturn efx_rc_t
422 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
424 /* siena_nic_reset() is called to recover from BADASSERT failures. */
425 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
427 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
431 * Bug24908: ENTITY_RESET_IN_LEN is non zero but zero may be supplied
432 * for backwards compatibility with PORT_RESET_IN_LEN.
434 EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
436 req.emr_cmd = MC_CMD_ENTITY_RESET;
437 req.emr_in_buf = NULL;
438 req.emr_in_length = 0;
439 req.emr_out_buf = NULL;
440 req.emr_out_length = 0;
442 efx_mcdi_execute(enp, &req);
444 if (req.emr_rc != 0) {
456 EFSYS_PROBE1(fail1, efx_rc_t, rc);
468 * RX_INGR_EN is always enabled on Siena, because we rely on
469 * the RX parser to be resiliant to missing SOP/EOP.
471 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
472 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1);
473 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
475 /* Disable parsing of additional 802.1Q in Q packets */
476 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
477 EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0);
478 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
487 EFX_POPULATE_OWORD_1(oword, FRF_CZ_USREV_DIS, 1);
488 EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword);
491 __checkReturn efx_rc_t
497 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
499 /* Enable reporting of some events (e.g. link change) */
500 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
503 siena_sram_init(enp);
505 /* Configure Siena's RX block */
506 siena_nic_rx_cfg(enp);
508 /* Disable USR_EVents for now */
509 siena_nic_usrev_dis(enp);
511 /* bug17057: Ensure set_link is called */
512 if ((rc = siena_phy_reconfigure(enp)) != 0)
515 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1;
522 EFSYS_PROBE1(fail1, efx_rc_t, rc);
531 _NOTE(ARGUNUSED(enp))
538 #if EFSYS_OPT_MON_STATS
539 mcdi_mon_cfg_free(enp);
540 #endif /* EFSYS_OPT_MON_STATS */
541 (void) efx_mcdi_drv_attach(enp, B_FALSE);
546 static siena_register_set_t __siena_registers[] = {
547 { FR_AZ_ADR_REGION_REG_OFST, 0, 1 },
548 { FR_CZ_USR_EV_CFG_OFST, 0, 1 },
549 { FR_AZ_RX_CFG_REG_OFST, 0, 1 },
550 { FR_AZ_TX_CFG_REG_OFST, 0, 1 },
551 { FR_AZ_TX_RESERVED_REG_OFST, 0, 1 },
552 { FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 },
553 { FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 },
554 { FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 },
555 { FR_AZ_DP_CTRL_REG_OFST, 0, 1 },
556 { FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1},
557 { FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1},
558 { FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1},
559 { FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1}
562 static const uint32_t __siena_register_masks[] = {
563 0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF,
564 0x000103FF, 0x00000000, 0x00000000, 0x00000000,
565 0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000,
566 0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF,
567 0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF,
568 0x001FFFFF, 0x00000000, 0x00000000, 0x00000000,
569 0x00000003, 0x00000000, 0x00000000, 0x00000000,
570 0x000003FF, 0x00000000, 0x00000000, 0x00000000,
571 0x00000FFF, 0x00000000, 0x00000000, 0x00000000,
572 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
573 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
574 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
575 0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000
578 static siena_register_set_t __siena_tables[] = {
579 { FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP,
580 FR_AZ_RX_FILTER_TBL0_ROWS },
581 { FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP,
582 FR_CZ_RX_MAC_FILTER_TBL0_ROWS },
583 { FR_AZ_RX_DESC_PTR_TBL_OFST,
584 FR_AZ_RX_DESC_PTR_TBL_STEP, FR_CZ_RX_DESC_PTR_TBL_ROWS },
585 { FR_AZ_TX_DESC_PTR_TBL_OFST,
586 FR_AZ_TX_DESC_PTR_TBL_STEP, FR_CZ_TX_DESC_PTR_TBL_ROWS },
587 { FR_AZ_TIMER_TBL_OFST, FR_AZ_TIMER_TBL_STEP, FR_CZ_TIMER_TBL_ROWS },
588 { FR_CZ_TX_FILTER_TBL0_OFST,
589 FR_CZ_TX_FILTER_TBL0_STEP, FR_CZ_TX_FILTER_TBL0_ROWS },
590 { FR_CZ_TX_MAC_FILTER_TBL0_OFST,
591 FR_CZ_TX_MAC_FILTER_TBL0_STEP, FR_CZ_TX_MAC_FILTER_TBL0_ROWS }
594 static const uint32_t __siena_table_masks[] = {
595 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF,
596 0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000,
597 0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000,
598 0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000,
599 0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000,
600 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF,
601 0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,
604 __checkReturn efx_rc_t
605 siena_nic_test_registers(
607 __in siena_register_set_t *rsp,
611 efx_oword_t original;
617 /* This function is only suitable for registers */
618 EFSYS_ASSERT(rsp->rows == 1);
620 /* bit sweep on and off */
621 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &original,
623 for (bit = 0; bit < 128; bit++) {
624 /* Is this bit in the mask? */
625 if (~(rsp->mask.eo_u32[bit >> 5]) & (1 << bit))
628 /* Test this bit can be set in isolation */
630 EFX_AND_OWORD(reg, rsp->mask);
631 EFX_SET_OWORD_BIT(reg, bit);
633 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
635 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
638 EFX_AND_OWORD(buf, rsp->mask);
639 if (memcmp(®, &buf, sizeof (reg))) {
644 /* Test this bit can be cleared in isolation */
645 EFX_OR_OWORD(reg, rsp->mask);
646 EFX_CLEAR_OWORD_BIT(reg, bit);
648 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, ®,
650 EFSYS_BAR_READO(enp->en_esbp, rsp->address, &buf,
653 EFX_AND_OWORD(buf, rsp->mask);
654 if (memcmp(®, &buf, sizeof (reg))) {
660 /* Restore the old value */
661 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original,
673 EFSYS_PROBE1(fail1, efx_rc_t, rc);
675 /* Restore the old value */
676 EFSYS_BAR_WRITEO(enp->en_esbp, rsp->address, &original, B_TRUE);
681 __checkReturn efx_rc_t
682 siena_nic_test_tables(
684 __in siena_register_set_t *rsp,
685 __in efx_pattern_type_t pattern,
688 efx_sram_pattern_fn_t func;
690 unsigned int address;
695 EFSYS_ASSERT(pattern < EFX_PATTERN_NTYPES);
696 func = __efx_sram_pattern_fns[pattern];
700 address = rsp->address;
701 for (index = 0; index < rsp->rows; ++index) {
702 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
703 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
704 EFX_AND_OWORD(reg, rsp->mask);
705 EFSYS_BAR_WRITEO(enp->en_esbp, address, ®, B_TRUE);
707 address += rsp->step;
711 address = rsp->address;
712 for (index = 0; index < rsp->rows; ++index) {
713 func(2 * index + 0, B_FALSE, ®.eo_qword[0]);
714 func(2 * index + 1, B_FALSE, ®.eo_qword[1]);
715 EFX_AND_OWORD(reg, rsp->mask);
716 EFSYS_BAR_READO(enp->en_esbp, address, &buf, B_TRUE);
717 if (memcmp(®, &buf, sizeof (reg))) {
722 address += rsp->step;
732 EFSYS_PROBE1(fail1, efx_rc_t, rc);
738 __checkReturn efx_rc_t
739 siena_nic_register_test(
742 siena_register_set_t *rsp;
743 const uint32_t *dwordp;
748 /* Fill out the register mask entries */
749 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)
750 == EFX_ARRAY_SIZE(__siena_registers) * 4);
752 nitems = EFX_ARRAY_SIZE(__siena_registers);
753 dwordp = __siena_register_masks;
754 for (count = 0; count < nitems; ++count) {
755 rsp = __siena_registers + count;
756 rsp->mask.eo_u32[0] = *dwordp++;
757 rsp->mask.eo_u32[1] = *dwordp++;
758 rsp->mask.eo_u32[2] = *dwordp++;
759 rsp->mask.eo_u32[3] = *dwordp++;
762 /* Fill out the register table entries */
763 EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)
764 == EFX_ARRAY_SIZE(__siena_tables) * 4);
766 nitems = EFX_ARRAY_SIZE(__siena_tables);
767 dwordp = __siena_table_masks;
768 for (count = 0; count < nitems; ++count) {
769 rsp = __siena_tables + count;
770 rsp->mask.eo_u32[0] = *dwordp++;
771 rsp->mask.eo_u32[1] = *dwordp++;
772 rsp->mask.eo_u32[2] = *dwordp++;
773 rsp->mask.eo_u32[3] = *dwordp++;
776 if ((rc = siena_nic_test_registers(enp, __siena_registers,
777 EFX_ARRAY_SIZE(__siena_registers))) != 0)
780 if ((rc = siena_nic_test_tables(enp, __siena_tables,
781 EFX_PATTERN_BYTE_ALTERNATE,
782 EFX_ARRAY_SIZE(__siena_tables))) != 0)
785 if ((rc = siena_nic_test_tables(enp, __siena_tables,
786 EFX_PATTERN_BYTE_CHANGING,
787 EFX_ARRAY_SIZE(__siena_tables))) != 0)
790 if ((rc = siena_nic_test_tables(enp, __siena_tables,
791 EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0)
803 EFSYS_PROBE1(fail1, efx_rc_t, rc);
808 #endif /* EFSYS_OPT_DIAG */
810 #endif /* EFSYS_OPT_SIENA */