1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2009-2019 Solarflare Communications Inc.
12 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
14 __checkReturn efx_rc_t
15 siena_nvram_partn_size(
21 efx_nvram_info_t eni = { 0 };
23 if ((1 << partn) & ~enp->en_u.siena.enu_partn_mask) {
28 if ((rc = efx_mcdi_nvram_info(enp, partn, &eni)) != 0)
31 *sizep = eni.eni_partn_size;
38 EFSYS_PROBE1(fail1, efx_rc_t, rc);
43 __checkReturn efx_rc_t
44 siena_nvram_partn_info(
47 __out efx_nvram_info_t * enip)
51 if ((rc = efx_mcdi_nvram_info(enp, partn, enip)) != 0)
54 if (enip->eni_write_size == 0)
55 enip->eni_write_size = SIENA_NVRAM_CHUNK;
60 EFSYS_PROBE1(fail1, efx_rc_t, rc);
66 __checkReturn efx_rc_t
67 siena_nvram_partn_lock(
73 if ((rc = efx_mcdi_nvram_update_start(enp, partn)) != 0) {
80 EFSYS_PROBE1(fail1, efx_rc_t, rc);
85 __checkReturn efx_rc_t
86 siena_nvram_partn_read(
89 __in unsigned int offset,
90 __out_bcount(size) caddr_t data,
97 chunk = MIN(size, SIENA_NVRAM_CHUNK);
99 if ((rc = efx_mcdi_nvram_read(enp, partn, offset, data, chunk,
100 MC_CMD_NVRAM_READ_IN_V2_DEFAULT)) != 0) {
112 EFSYS_PROBE1(fail1, efx_rc_t, rc);
117 __checkReturn efx_rc_t
118 siena_nvram_partn_erase(
121 __in unsigned int offset,
126 if ((rc = efx_mcdi_nvram_erase(enp, partn, offset, size)) != 0) {
133 EFSYS_PROBE1(fail1, efx_rc_t, rc);
138 __checkReturn efx_rc_t
139 siena_nvram_partn_write(
142 __in unsigned int offset,
143 __out_bcount(size) caddr_t data,
150 chunk = MIN(size, SIENA_NVRAM_CHUNK);
152 if ((rc = efx_mcdi_nvram_write(enp, partn, offset,
153 data, chunk)) != 0) {
165 EFSYS_PROBE1(fail1, efx_rc_t, rc);
170 __checkReturn efx_rc_t
171 siena_nvram_partn_unlock(
174 __out_opt uint32_t *verify_resultp)
181 * Reboot into the new image only for PHYs. The driver has to
182 * explicitly cope with an MC reboot after a firmware update.
184 reboot = (partn == MC_CMD_NVRAM_TYPE_PHY_PORT0 ||
185 partn == MC_CMD_NVRAM_TYPE_PHY_PORT1 ||
186 partn == MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO);
188 rc = efx_mcdi_nvram_update_finish(enp, partn, reboot, flags,
196 EFSYS_PROBE1(fail1, efx_rc_t, rc);
201 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
205 typedef struct siena_parttbl_entry_s {
208 efx_nvram_type_t nvtype;
209 } siena_parttbl_entry_t;
211 static siena_parttbl_entry_t siena_parttbl[] = {
212 {MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO, 1, EFX_NVRAM_NULLPHY},
213 {MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO, 2, EFX_NVRAM_NULLPHY},
214 {MC_CMD_NVRAM_TYPE_MC_FW, 1, EFX_NVRAM_MC_FIRMWARE},
215 {MC_CMD_NVRAM_TYPE_MC_FW, 2, EFX_NVRAM_MC_FIRMWARE},
216 {MC_CMD_NVRAM_TYPE_MC_FW_BACKUP, 1, EFX_NVRAM_MC_GOLDEN},
217 {MC_CMD_NVRAM_TYPE_MC_FW_BACKUP, 2, EFX_NVRAM_MC_GOLDEN},
218 {MC_CMD_NVRAM_TYPE_EXP_ROM, 1, EFX_NVRAM_BOOTROM},
219 {MC_CMD_NVRAM_TYPE_EXP_ROM, 2, EFX_NVRAM_BOOTROM},
220 {MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0, 1, EFX_NVRAM_BOOTROM_CFG},
221 {MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1, 2, EFX_NVRAM_BOOTROM_CFG},
222 {MC_CMD_NVRAM_TYPE_PHY_PORT0, 1, EFX_NVRAM_PHY},
223 {MC_CMD_NVRAM_TYPE_PHY_PORT1, 2, EFX_NVRAM_PHY},
224 {MC_CMD_NVRAM_TYPE_FPGA, 1, EFX_NVRAM_FPGA},
225 {MC_CMD_NVRAM_TYPE_FPGA, 2, EFX_NVRAM_FPGA},
226 {MC_CMD_NVRAM_TYPE_FPGA_BACKUP, 1, EFX_NVRAM_FPGA_BACKUP},
227 {MC_CMD_NVRAM_TYPE_FPGA_BACKUP, 2, EFX_NVRAM_FPGA_BACKUP},
228 {MC_CMD_NVRAM_TYPE_FC_FW, 1, EFX_NVRAM_FCFW},
229 {MC_CMD_NVRAM_TYPE_FC_FW, 2, EFX_NVRAM_FCFW},
230 {MC_CMD_NVRAM_TYPE_CPLD, 1, EFX_NVRAM_CPLD},
231 {MC_CMD_NVRAM_TYPE_CPLD, 2, EFX_NVRAM_CPLD},
232 {MC_CMD_NVRAM_TYPE_LICENSE, 1, EFX_NVRAM_LICENSE},
233 {MC_CMD_NVRAM_TYPE_LICENSE, 2, EFX_NVRAM_LICENSE}
236 __checkReturn efx_rc_t
237 siena_nvram_type_to_partn(
239 __in efx_nvram_type_t type,
240 __out uint32_t *partnp)
242 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
245 EFSYS_ASSERT3U(type, !=, EFX_NVRAM_INVALID);
246 EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES);
247 EFSYS_ASSERT(partnp != NULL);
249 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) {
250 siena_parttbl_entry_t *entry = &siena_parttbl[i];
252 if (entry->port == emip->emi_port && entry->nvtype == type) {
253 *partnp = entry->partn;
264 __checkReturn efx_rc_t
268 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
269 siena_parttbl_entry_t *entry;
274 * Iterate over the list of supported partition types
275 * applicable to *this* port
277 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) {
278 entry = &siena_parttbl[i];
280 if (entry->port != emip->emi_port ||
281 !(enp->en_u.siena.enu_partn_mask & (1 << entry->partn)))
284 if ((rc = efx_mcdi_nvram_test(enp, entry->partn)) != 0) {
292 EFSYS_PROBE1(fail1, efx_rc_t, rc);
297 #endif /* EFSYS_OPT_DIAG */
300 #define SIENA_DYNAMIC_CFG_SIZE(_nitems) \
301 (sizeof (siena_mc_dynamic_config_hdr_t) + ((_nitems) * \
302 sizeof (((siena_mc_dynamic_config_hdr_t *)NULL)->fw_version[0])))
304 __checkReturn efx_rc_t
305 siena_nvram_get_dynamic_cfg(
309 __out siena_mc_dynamic_config_hdr_t **dcfgp,
312 siena_mc_dynamic_config_hdr_t *dcfg = NULL;
315 unsigned int vpd_offset;
316 unsigned int vpd_length;
317 unsigned int hdr_length;
318 unsigned int nversions;
323 EFSYS_ASSERT(partn == MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 ||
324 partn == MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1);
327 * Allocate sufficient memory for the entire dynamiccfg area, even
328 * if we're not actually going to read in the VPD.
330 if ((rc = siena_nvram_partn_size(enp, partn, &size)) != 0)
333 if (size < SIENA_NVRAM_CHUNK) {
338 EFSYS_KMEM_ALLOC(enp->en_esip, size, dcfg);
344 if ((rc = siena_nvram_partn_read(enp, partn, 0,
345 (caddr_t)dcfg, SIENA_NVRAM_CHUNK)) != 0)
348 /* Verify the magic */
349 if (EFX_DWORD_FIELD(dcfg->magic, EFX_DWORD_0)
350 != SIENA_MC_DYNAMIC_CONFIG_MAGIC)
353 /* All future versions of the structure must be backwards compatible */
354 EFX_STATIC_ASSERT(SIENA_MC_DYNAMIC_CONFIG_VERSION == 0);
356 hdr_length = EFX_WORD_FIELD(dcfg->length, EFX_WORD_0);
357 nversions = EFX_DWORD_FIELD(dcfg->num_fw_version_items, EFX_DWORD_0);
358 vpd_offset = EFX_DWORD_FIELD(dcfg->dynamic_vpd_offset, EFX_DWORD_0);
359 vpd_length = EFX_DWORD_FIELD(dcfg->dynamic_vpd_length, EFX_DWORD_0);
361 /* Verify the hdr doesn't overflow the partn size */
362 if (hdr_length > size || vpd_offset > size || vpd_length > size ||
363 vpd_length + vpd_offset > size)
366 /* Verify the header has room for all it's versions */
367 if (hdr_length < SIENA_DYNAMIC_CFG_SIZE(0) ||
368 hdr_length < SIENA_DYNAMIC_CFG_SIZE(nversions))
372 * Read the remaining portion of the dcfg, either including
373 * the whole of VPD (there is no vpd length in this structure,
374 * so we have to parse each tag), or just the dcfg header itself
376 region = vpd ? vpd_offset + vpd_length : hdr_length;
377 if (region > SIENA_NVRAM_CHUNK) {
378 if ((rc = siena_nvram_partn_read(enp, partn, SIENA_NVRAM_CHUNK,
379 (caddr_t)dcfg + SIENA_NVRAM_CHUNK,
380 region - SIENA_NVRAM_CHUNK)) != 0)
384 /* Verify checksum */
386 for (pos = 0; pos < hdr_length; pos++)
387 cksum += ((uint8_t *)dcfg)[pos];
394 EFSYS_PROBE(invalid4);
396 EFSYS_PROBE(invalid3);
398 EFSYS_PROBE(invalid2);
400 EFSYS_PROBE(invalid1);
403 * Construct a new "null" dcfg, with an empty version vector,
404 * and an empty VPD chunk trailing. This has the neat side effect
405 * of testing the exception paths in the write path.
407 EFX_POPULATE_DWORD_1(dcfg->magic,
408 EFX_DWORD_0, SIENA_MC_DYNAMIC_CONFIG_MAGIC);
409 EFX_POPULATE_WORD_1(dcfg->length, EFX_WORD_0, sizeof (*dcfg));
410 EFX_POPULATE_BYTE_1(dcfg->version, EFX_BYTE_0,
411 SIENA_MC_DYNAMIC_CONFIG_VERSION);
412 EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_offset,
413 EFX_DWORD_0, sizeof (*dcfg));
414 EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_length, EFX_DWORD_0, 0);
415 EFX_POPULATE_DWORD_1(dcfg->num_fw_version_items, EFX_DWORD_0, 0);
428 EFSYS_KMEM_FREE(enp->en_esip, size, dcfg);
435 EFSYS_PROBE1(fail1, efx_rc_t, rc);
440 __checkReturn efx_rc_t
441 siena_nvram_get_subtype(
444 __out uint32_t *subtypep)
447 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_BOARD_CFG_IN_LEN,
448 MC_CMD_GET_BOARD_CFG_OUT_LENMAX);
452 req.emr_cmd = MC_CMD_GET_BOARD_CFG;
453 req.emr_in_buf = payload;
454 req.emr_in_length = MC_CMD_GET_BOARD_CFG_IN_LEN;
455 req.emr_out_buf = payload;
456 req.emr_out_length = MC_CMD_GET_BOARD_CFG_OUT_LENMAX;
458 efx_mcdi_execute(enp, &req);
460 if (req.emr_rc != 0) {
465 if (req.emr_out_length_used < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) {
470 if (req.emr_out_length_used <
471 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST +
472 (partn + 1) * sizeof (efx_word_t)) {
477 fw_list = MCDI_OUT2(req, efx_word_t,
478 GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST);
479 *subtypep = EFX_WORD_FIELD(fw_list[partn], EFX_WORD_0);
488 EFSYS_PROBE1(fail1, efx_rc_t, rc);
493 __checkReturn efx_rc_t
494 siena_nvram_partn_get_version(
497 __out uint32_t *subtypep,
498 __out_ecount(4) uint16_t version[4])
500 siena_mc_dynamic_config_hdr_t *dcfg;
501 siena_parttbl_entry_t *entry;
506 if ((1 << partn) & ~enp->en_u.siena.enu_partn_mask) {
511 if ((rc = siena_nvram_get_subtype(enp, partn, subtypep)) != 0)
515 * Some partitions are accessible from both ports (for instance BOOTROM)
516 * Find the highest version reported by all dcfg structures on ports
517 * that have access to this partition.
519 version[0] = version[1] = version[2] = version[3] = 0;
520 for (i = 0; i < EFX_ARRAY_SIZE(siena_parttbl); i++) {
521 siena_mc_fw_version_t *verp;
526 entry = &siena_parttbl[i];
527 if (entry->partn != partn)
530 dcfg_partn = (entry->port == 1)
531 ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0
532 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1;
534 * Ingore missing partitions on port 2, assuming they're due
535 * to to running on a single port part.
537 if ((1 << dcfg_partn) & ~enp->en_u.siena.enu_partn_mask) {
538 if (entry->port == 2)
542 if ((rc = siena_nvram_get_dynamic_cfg(enp, dcfg_partn,
543 B_FALSE, &dcfg, &length)) != 0)
546 nitems = EFX_DWORD_FIELD(dcfg->num_fw_version_items,
548 if (nitems < entry->partn)
551 verp = &dcfg->fw_version[partn];
552 temp[0] = EFX_WORD_FIELD(verp->version_w, EFX_WORD_0);
553 temp[1] = EFX_WORD_FIELD(verp->version_x, EFX_WORD_0);
554 temp[2] = EFX_WORD_FIELD(verp->version_y, EFX_WORD_0);
555 temp[3] = EFX_WORD_FIELD(verp->version_z, EFX_WORD_0);
556 if (memcmp(version, temp, sizeof (temp)) < 0)
557 memcpy(version, temp, sizeof (temp));
560 EFSYS_KMEM_FREE(enp->en_esip, length, dcfg);
570 EFSYS_PROBE1(fail1, efx_rc_t, rc);
575 __checkReturn efx_rc_t
576 siena_nvram_partn_rw_start(
579 __out size_t *chunk_sizep)
583 if ((rc = siena_nvram_partn_lock(enp, partn)) != 0)
586 if (chunk_sizep != NULL)
587 *chunk_sizep = SIENA_NVRAM_CHUNK;
592 EFSYS_PROBE1(fail1, efx_rc_t, rc);
597 __checkReturn efx_rc_t
598 siena_nvram_partn_rw_finish(
601 __out_opt uint32_t *verify_resultp)
605 if ((rc = siena_nvram_partn_unlock(enp, partn, verify_resultp)) != 0)
611 EFSYS_PROBE1(fail1, efx_rc_t, rc);
616 __checkReturn efx_rc_t
617 siena_nvram_partn_set_version(
620 __in_ecount(4) uint16_t version[4])
622 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
623 siena_mc_dynamic_config_hdr_t *dcfg = NULL;
624 siena_mc_fw_version_t *fwverp;
627 unsigned int hdr_length;
628 unsigned int vpd_length;
629 unsigned int vpd_offset;
631 unsigned int required_hdr_length;
638 dcfg_partn = (emip->emi_port == 1)
639 ? MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0
640 : MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1;
642 if ((rc = siena_nvram_partn_size(enp, dcfg_partn, &dcfg_size)) != 0)
645 if ((rc = siena_nvram_partn_lock(enp, dcfg_partn)) != 0)
648 if ((rc = siena_nvram_get_dynamic_cfg(enp, dcfg_partn,
649 B_TRUE, &dcfg, &length)) != 0)
652 hdr_length = EFX_WORD_FIELD(dcfg->length, EFX_WORD_0);
653 nitems = EFX_DWORD_FIELD(dcfg->num_fw_version_items, EFX_DWORD_0);
654 vpd_length = EFX_DWORD_FIELD(dcfg->dynamic_vpd_length, EFX_DWORD_0);
655 vpd_offset = EFX_DWORD_FIELD(dcfg->dynamic_vpd_offset, EFX_DWORD_0);
658 * NOTE: This function will blatt any fields trailing the version
659 * vector, or the VPD chunk.
661 required_hdr_length = SIENA_DYNAMIC_CFG_SIZE(partn + 1);
662 if (required_hdr_length + vpd_length > length) {
667 if (vpd_offset < required_hdr_length) {
668 (void) memmove((caddr_t)dcfg + required_hdr_length,
669 (caddr_t)dcfg + vpd_offset, vpd_length);
670 vpd_offset = required_hdr_length;
671 EFX_POPULATE_DWORD_1(dcfg->dynamic_vpd_offset,
672 EFX_DWORD_0, vpd_offset);
675 if (hdr_length < required_hdr_length) {
676 (void) memset((caddr_t)dcfg + hdr_length, 0,
677 required_hdr_length - hdr_length);
678 hdr_length = required_hdr_length;
679 EFX_POPULATE_WORD_1(dcfg->length,
680 EFX_WORD_0, hdr_length);
683 /* Get the subtype to insert into the fw_subtype array */
684 if ((rc = siena_nvram_get_subtype(enp, partn, &subtype)) != 0)
687 /* Fill out the new version */
688 fwverp = &dcfg->fw_version[partn];
689 EFX_POPULATE_DWORD_1(fwverp->fw_subtype, EFX_DWORD_0, subtype);
690 EFX_POPULATE_WORD_1(fwverp->version_w, EFX_WORD_0, version[0]);
691 EFX_POPULATE_WORD_1(fwverp->version_x, EFX_WORD_0, version[1]);
692 EFX_POPULATE_WORD_1(fwverp->version_y, EFX_WORD_0, version[2]);
693 EFX_POPULATE_WORD_1(fwverp->version_z, EFX_WORD_0, version[3]);
695 /* Update the version count */
696 if (nitems < partn + 1) {
698 EFX_POPULATE_DWORD_1(dcfg->num_fw_version_items,
699 EFX_DWORD_0, nitems);
702 /* Update the checksum */
704 for (pos = 0; pos < hdr_length; pos++)
705 cksum += ((uint8_t *)dcfg)[pos];
706 dcfg->csum.eb_u8[0] -= cksum;
708 /* Erase and write the new partition */
709 if ((rc = siena_nvram_partn_erase(enp, dcfg_partn, 0, dcfg_size)) != 0)
712 /* Write out the new structure to nvram */
713 if ((rc = siena_nvram_partn_write(enp, dcfg_partn, 0,
714 (caddr_t)dcfg, vpd_offset + vpd_length)) != 0)
717 EFSYS_KMEM_FREE(enp->en_esip, length, dcfg);
719 siena_nvram_partn_unlock(enp, dcfg_partn, NULL);
732 EFSYS_KMEM_FREE(enp->en_esip, length, dcfg);
738 EFSYS_PROBE1(fail1, efx_rc_t, rc);
743 #endif /* EFSYS_OPT_NVRAM */
745 #endif /* EFSYS_OPT_SIENA */