1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2016-2019 Solarflare Communications Inc.
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
10 #ifndef _SFC_COMMON_EFSYS_H
11 #define _SFC_COMMON_EFSYS_H
15 #include <rte_spinlock.h>
16 #include <rte_byteorder.h>
17 #include <rte_debug.h>
18 #include <rte_memzone.h>
19 #include <rte_memory.h>
20 #include <rte_memcpy.h>
21 #include <rte_cycles.h>
22 #include <rte_prefetch.h>
23 #include <rte_common.h>
24 #include <rte_malloc.h>
28 #include "sfc_efx_debug.h"
29 #include "sfc_efx_log.h"
35 #define LIBEFX_API __rte_internal
37 /* No specific decorations required since functions are local by default */
38 #define LIBEFX_INTERNAL
40 #define EFSYS_HAS_UINT64 1
41 #define EFSYS_USE_UINT64 1
42 #define EFSYS_HAS_SSE2_M128 1
44 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
45 #define EFSYS_IS_BIG_ENDIAN 1
46 #define EFSYS_IS_LITTLE_ENDIAN 0
47 #elif RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
48 #define EFSYS_IS_BIG_ENDIAN 0
49 #define EFSYS_IS_LITTLE_ENDIAN 1
51 #error "Cannot determine system endianness"
55 typedef bool boolean_t;
65 * RTE_MAX() and RTE_MIN() cannot be used since braced-group within
66 * expression allowed only inside a function, but MAX() is used as
67 * a number of elements in array.
70 #define MAX(v1, v2) ((v1) > (v2) ? (v1) : (v2))
73 #define MIN(v1, v2) ((v1) < (v2) ? (v1) : (v2))
77 #define ISP2(x) rte_is_power_of_2(x)
80 #define ENOTACTIVE ENOTCONN
83 prefetch_read_many(const volatile void *addr)
89 prefetch_read_once(const volatile void *addr)
91 rte_prefetch_non_temporal(addr);
94 /* Code inclusion options */
97 #define EFSYS_OPT_NAMES 1
99 /* Disable SFN5xxx/SFN6xxx since it requires specific support in the PMD */
100 #define EFSYS_OPT_SIENA 0
101 /* Enable SFN7xxx support */
102 #define EFSYS_OPT_HUNTINGTON 1
103 /* Enable SFN8xxx support */
104 #define EFSYS_OPT_MEDFORD 1
105 /* Enable SFN2xxx support */
106 #define EFSYS_OPT_MEDFORD2 1
107 /* Enable Riverhead support */
108 #define EFSYS_OPT_RIVERHEAD 1
110 #ifdef RTE_LIBRTE_SFC_EFX_DEBUG
111 #define EFSYS_OPT_CHECK_REG 1
113 #define EFSYS_OPT_CHECK_REG 0
116 /* MCDI is required for SFN7xxx and SFN8xx */
117 #define EFSYS_OPT_MCDI 1
118 #define EFSYS_OPT_MCDI_LOGGING 1
119 #define EFSYS_OPT_MCDI_PROXY_AUTH 1
121 #define EFSYS_OPT_MAC_STATS 1
123 #define EFSYS_OPT_LOOPBACK 1
125 #define EFSYS_OPT_MON_MCDI 0
126 #define EFSYS_OPT_MON_STATS 0
128 #define EFSYS_OPT_PHY_STATS 0
129 #define EFSYS_OPT_BIST 0
130 #define EFSYS_OPT_PHY_LED_CONTROL 0
131 #define EFSYS_OPT_PHY_FLAGS 0
133 #define EFSYS_OPT_VPD 0
134 #define EFSYS_OPT_NVRAM 0
135 #define EFSYS_OPT_BOOTCFG 0
136 #define EFSYS_OPT_IMAGE_LAYOUT 0
138 #define EFSYS_OPT_DIAG 0
139 #define EFSYS_OPT_RX_SCALE 1
140 #define EFSYS_OPT_QSTATS 0
141 /* Filters support is required for SFN7xxx and SFN8xx */
142 #define EFSYS_OPT_FILTER 1
143 #define EFSYS_OPT_RX_SCATTER 0
145 #define EFSYS_OPT_EV_EXTENDED_WIDTH 0
146 #define EFSYS_OPT_EV_PREFETCH 0
148 #define EFSYS_OPT_DECODE_INTR_FATAL 0
150 #define EFSYS_OPT_LICENSING 0
152 #define EFSYS_OPT_ALLOW_UNCONFIGURED_NIC 0
154 #define EFSYS_OPT_RX_PACKED_STREAM 0
156 #define EFSYS_OPT_RX_ES_SUPER_BUFFER 1
158 #define EFSYS_OPT_TUNNEL 1
160 #define EFSYS_OPT_FW_SUBVARIANT_AWARE 1
162 #define EFSYS_OPT_EVB 1
164 #define EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 0
166 #define EFSYS_OPT_PCI 1
168 #define EFSYS_OPT_DESC_PROXY 0
172 typedef struct __efsys_identifier_s efsys_identifier_t;
175 #define EFSYS_PROBE(_name) \
178 #define EFSYS_PROBE1(_name, _type1, _arg1) \
181 #define EFSYS_PROBE2(_name, _type1, _arg1, _type2, _arg2) \
184 #define EFSYS_PROBE3(_name, _type1, _arg1, _type2, _arg2, \
188 #define EFSYS_PROBE4(_name, _type1, _arg1, _type2, _arg2, \
189 _type3, _arg3, _type4, _arg4) \
192 #define EFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2, \
193 _type3, _arg3, _type4, _arg4, _type5, _arg5) \
196 #define EFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2, \
197 _type3, _arg3, _type4, _arg4, _type5, _arg5, \
201 #define EFSYS_PROBE7(_name, _type1, _arg1, _type2, _arg2, \
202 _type3, _arg3, _type4, _arg4, _type5, _arg5, \
203 _type6, _arg6, _type7, _arg7) \
209 typedef rte_iova_t efsys_dma_addr_t;
211 typedef struct efsys_mem_s {
212 const struct rte_memzone *esm_mz;
214 * Ideally it should have volatile qualifier to denote that
215 * the memory may be updated by someone else. However, it adds
216 * qualifier discard warnings when the pointer or its derivative
217 * is passed to memset() or rte_mov16().
218 * So, skip the qualifier here, but make sure that it is added
219 * below in access macros.
222 efsys_dma_addr_t esm_addr;
226 #define EFSYS_MEM_ZERO(_esmp, _size) \
228 (void)memset((void *)(_esmp)->esm_base, 0, (_size)); \
230 _NOTE(CONSTANTCONDITION); \
233 #define EFSYS_MEM_READD(_esmp, _offset, _edp) \
235 volatile uint8_t *_base = (_esmp)->esm_base; \
236 volatile uint32_t *_addr; \
238 _NOTE(CONSTANTCONDITION); \
239 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
240 sizeof(efx_dword_t))); \
242 _addr = (volatile uint32_t *)(_base + (_offset)); \
243 (_edp)->ed_u32[0] = _addr[0]; \
245 EFSYS_PROBE2(mem_readl, unsigned int, (_offset), \
246 uint32_t, (_edp)->ed_u32[0]); \
248 _NOTE(CONSTANTCONDITION); \
251 #define EFSYS_MEM_READQ(_esmp, _offset, _eqp) \
253 volatile uint8_t *_base = (_esmp)->esm_base; \
254 volatile uint64_t *_addr; \
256 _NOTE(CONSTANTCONDITION); \
257 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
258 sizeof(efx_qword_t))); \
260 _addr = (volatile uint64_t *)(_base + (_offset)); \
261 (_eqp)->eq_u64[0] = _addr[0]; \
263 EFSYS_PROBE3(mem_readq, unsigned int, (_offset), \
264 uint32_t, (_eqp)->eq_u32[1], \
265 uint32_t, (_eqp)->eq_u32[0]); \
267 _NOTE(CONSTANTCONDITION); \
270 #define EFSYS_MEM_READO(_esmp, _offset, _eop) \
272 volatile uint8_t *_base = (_esmp)->esm_base; \
273 volatile __m128i *_addr; \
275 _NOTE(CONSTANTCONDITION); \
276 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
277 sizeof(efx_oword_t))); \
279 _addr = (volatile __m128i *)(_base + (_offset)); \
280 (_eop)->eo_u128[0] = _addr[0]; \
282 EFSYS_PROBE5(mem_reado, unsigned int, (_offset), \
283 uint32_t, (_eop)->eo_u32[3], \
284 uint32_t, (_eop)->eo_u32[2], \
285 uint32_t, (_eop)->eo_u32[1], \
286 uint32_t, (_eop)->eo_u32[0]); \
288 _NOTE(CONSTANTCONDITION); \
292 #define EFSYS_MEM_WRITED(_esmp, _offset, _edp) \
294 volatile uint8_t *_base = (_esmp)->esm_base; \
295 volatile uint32_t *_addr; \
297 _NOTE(CONSTANTCONDITION); \
298 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
299 sizeof(efx_dword_t))); \
301 EFSYS_PROBE2(mem_writed, unsigned int, (_offset), \
302 uint32_t, (_edp)->ed_u32[0]); \
304 _addr = (volatile uint32_t *)(_base + (_offset)); \
305 _addr[0] = (_edp)->ed_u32[0]; \
307 _NOTE(CONSTANTCONDITION); \
310 #define EFSYS_MEM_WRITEQ(_esmp, _offset, _eqp) \
312 volatile uint8_t *_base = (_esmp)->esm_base; \
313 volatile uint64_t *_addr; \
315 _NOTE(CONSTANTCONDITION); \
316 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
317 sizeof(efx_qword_t))); \
319 EFSYS_PROBE3(mem_writeq, unsigned int, (_offset), \
320 uint32_t, (_eqp)->eq_u32[1], \
321 uint32_t, (_eqp)->eq_u32[0]); \
323 _addr = (volatile uint64_t *)(_base + (_offset)); \
324 _addr[0] = (_eqp)->eq_u64[0]; \
326 _NOTE(CONSTANTCONDITION); \
329 #define EFSYS_MEM_WRITEO(_esmp, _offset, _eop) \
331 volatile uint8_t *_base = (_esmp)->esm_base; \
332 volatile __m128i *_addr; \
334 _NOTE(CONSTANTCONDITION); \
335 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
336 sizeof(efx_oword_t))); \
339 EFSYS_PROBE5(mem_writeo, unsigned int, (_offset), \
340 uint32_t, (_eop)->eo_u32[3], \
341 uint32_t, (_eop)->eo_u32[2], \
342 uint32_t, (_eop)->eo_u32[1], \
343 uint32_t, (_eop)->eo_u32[0]); \
345 _addr = (volatile __m128i *)(_base + (_offset)); \
346 _addr[0] = (_eop)->eo_u128[0]; \
348 _NOTE(CONSTANTCONDITION); \
352 #define EFSYS_MEM_SIZE(_esmp) \
353 ((_esmp)->esm_mz->len)
355 #define EFSYS_MEM_ADDR(_esmp) \
358 #define EFSYS_MEM_IS_NULL(_esmp) \
359 ((_esmp)->esm_base == NULL)
361 #define EFSYS_MEM_PREFETCH(_esmp, _offset) \
363 volatile uint8_t *_base = (_esmp)->esm_base; \
365 rte_prefetch0(_base + (_offset)); \
371 typedef struct efsys_bar_s {
372 rte_spinlock_t esb_lock;
374 struct rte_pci_device *esb_dev;
376 * Ideally it should have volatile qualifier to denote that
377 * the memory may be updated by someone else. However, it adds
378 * qualifier discard warnings when the pointer or its derivative
379 * is passed to memset() or rte_mov16().
380 * So, skip the qualifier here, but make sure that it is added
381 * below in access macros.
386 #define SFC_BAR_LOCK_INIT(_esbp, _ifname) \
388 rte_spinlock_init(&(_esbp)->esb_lock); \
389 _NOTE(CONSTANTCONDITION); \
391 #define SFC_BAR_LOCK_DESTROY(_esbp) ((void)0)
392 #define SFC_BAR_LOCK(_esbp) rte_spinlock_lock(&(_esbp)->esb_lock)
393 #define SFC_BAR_UNLOCK(_esbp) rte_spinlock_unlock(&(_esbp)->esb_lock)
395 #define EFSYS_BAR_READD(_esbp, _offset, _edp, _lock) \
397 volatile uint8_t *_base = (_esbp)->esb_base; \
398 volatile uint32_t *_addr; \
400 _NOTE(CONSTANTCONDITION); \
401 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
402 sizeof(efx_dword_t))); \
403 _NOTE(CONSTANTCONDITION); \
405 SFC_BAR_LOCK(_esbp); \
407 _addr = (volatile uint32_t *)(_base + (_offset)); \
409 (_edp)->ed_u32[0] = rte_read32_relaxed(_addr); \
411 EFSYS_PROBE2(bar_readd, unsigned int, (_offset), \
412 uint32_t, (_edp)->ed_u32[0]); \
414 _NOTE(CONSTANTCONDITION); \
416 SFC_BAR_UNLOCK(_esbp); \
417 _NOTE(CONSTANTCONDITION); \
420 #define EFSYS_BAR_READQ(_esbp, _offset, _eqp) \
422 volatile uint8_t *_base = (_esbp)->esb_base; \
423 volatile uint64_t *_addr; \
425 _NOTE(CONSTANTCONDITION); \
426 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
427 sizeof(efx_qword_t))); \
429 SFC_BAR_LOCK(_esbp); \
431 _addr = (volatile uint64_t *)(_base + (_offset)); \
433 (_eqp)->eq_u64[0] = rte_read64_relaxed(_addr); \
435 EFSYS_PROBE3(bar_readq, unsigned int, (_offset), \
436 uint32_t, (_eqp)->eq_u32[1], \
437 uint32_t, (_eqp)->eq_u32[0]); \
439 SFC_BAR_UNLOCK(_esbp); \
440 _NOTE(CONSTANTCONDITION); \
443 #define EFSYS_BAR_READO(_esbp, _offset, _eop, _lock) \
445 volatile uint8_t *_base = (_esbp)->esb_base; \
446 volatile __m128i *_addr; \
448 _NOTE(CONSTANTCONDITION); \
449 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
450 sizeof(efx_oword_t))); \
452 _NOTE(CONSTANTCONDITION); \
454 SFC_BAR_LOCK(_esbp); \
456 _addr = (volatile __m128i *)(_base + (_offset)); \
458 /* There is no rte_read128_relaxed() yet */ \
459 (_eop)->eo_u128[0] = _addr[0]; \
461 EFSYS_PROBE5(bar_reado, unsigned int, (_offset), \
462 uint32_t, (_eop)->eo_u32[3], \
463 uint32_t, (_eop)->eo_u32[2], \
464 uint32_t, (_eop)->eo_u32[1], \
465 uint32_t, (_eop)->eo_u32[0]); \
467 _NOTE(CONSTANTCONDITION); \
469 SFC_BAR_UNLOCK(_esbp); \
470 _NOTE(CONSTANTCONDITION); \
474 #define EFSYS_BAR_WRITED(_esbp, _offset, _edp, _lock) \
476 volatile uint8_t *_base = (_esbp)->esb_base; \
477 volatile uint32_t *_addr; \
479 _NOTE(CONSTANTCONDITION); \
480 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
481 sizeof(efx_dword_t))); \
483 _NOTE(CONSTANTCONDITION); \
485 SFC_BAR_LOCK(_esbp); \
487 EFSYS_PROBE2(bar_writed, unsigned int, (_offset), \
488 uint32_t, (_edp)->ed_u32[0]); \
490 _addr = (volatile uint32_t *)(_base + (_offset)); \
491 rte_write32_relaxed((_edp)->ed_u32[0], _addr); \
494 _NOTE(CONSTANTCONDITION); \
496 SFC_BAR_UNLOCK(_esbp); \
497 _NOTE(CONSTANTCONDITION); \
500 #define EFSYS_BAR_WRITEQ(_esbp, _offset, _eqp) \
502 volatile uint8_t *_base = (_esbp)->esb_base; \
503 volatile uint64_t *_addr; \
505 _NOTE(CONSTANTCONDITION); \
506 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
507 sizeof(efx_qword_t))); \
509 SFC_BAR_LOCK(_esbp); \
511 EFSYS_PROBE3(bar_writeq, unsigned int, (_offset), \
512 uint32_t, (_eqp)->eq_u32[1], \
513 uint32_t, (_eqp)->eq_u32[0]); \
515 _addr = (volatile uint64_t *)(_base + (_offset)); \
516 rte_write64_relaxed((_eqp)->eq_u64[0], _addr); \
519 SFC_BAR_UNLOCK(_esbp); \
520 _NOTE(CONSTANTCONDITION); \
524 * Guarantees 64bit aligned 64bit writes to write combined BAR mapping
525 * (required by PIO hardware).
527 * Neither VFIO, nor UIO, nor NIC UIO (on FreeBSD) support
528 * write-combined memory mapped to user-land, so just abort if used.
530 #define EFSYS_BAR_WC_WRITEQ(_esbp, _offset, _eqp) \
532 rte_panic("Write-combined BAR access not supported"); \
535 #define EFSYS_BAR_WRITEO(_esbp, _offset, _eop, _lock) \
537 volatile uint8_t *_base = (_esbp)->esb_base; \
538 volatile __m128i *_addr; \
540 _NOTE(CONSTANTCONDITION); \
541 SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset, \
542 sizeof(efx_oword_t))); \
544 _NOTE(CONSTANTCONDITION); \
546 SFC_BAR_LOCK(_esbp); \
548 EFSYS_PROBE5(bar_writeo, unsigned int, (_offset), \
549 uint32_t, (_eop)->eo_u32[3], \
550 uint32_t, (_eop)->eo_u32[2], \
551 uint32_t, (_eop)->eo_u32[1], \
552 uint32_t, (_eop)->eo_u32[0]); \
554 _addr = (volatile __m128i *)(_base + (_offset)); \
555 /* There is no rte_write128_relaxed() yet */ \
556 _addr[0] = (_eop)->eo_u128[0]; \
559 _NOTE(CONSTANTCONDITION); \
561 SFC_BAR_UNLOCK(_esbp); \
562 _NOTE(CONSTANTCONDITION); \
565 /* Use the standard octo-word write for doorbell writes */
566 #define EFSYS_BAR_DOORBELL_WRITEO(_esbp, _offset, _eop) \
568 EFSYS_BAR_WRITEO((_esbp), (_offset), (_eop), B_FALSE); \
569 _NOTE(CONSTANTCONDITION); \
574 #define EFSYS_SPIN(_us) \
577 _NOTE(CONSTANTCONDITION); \
580 #define EFSYS_SLEEP EFSYS_SPIN
584 #define EFSYS_MEM_READ_BARRIER() rte_rmb()
585 #define EFSYS_PIO_WRITE_BARRIER() rte_io_wmb()
590 * DPDK does not provide any DMA syncing API, and no PMD drivers
591 * have any traces of explicit DMA syncing.
592 * DMA mapping is assumed to be coherent.
595 #define EFSYS_DMA_SYNC_FOR_KERNEL(_esmp, _offset, _size) ((void)0)
597 /* Just avoid store and compiler (impliciltly) reordering */
598 #define EFSYS_DMA_SYNC_FOR_DEVICE(_esmp, _offset, _size) rte_wmb()
602 typedef uint64_t efsys_timestamp_t;
604 #define EFSYS_TIMESTAMP(_usp) \
606 *(_usp) = rte_get_timer_cycles() * 1000000 / \
607 rte_get_timer_hz(); \
608 _NOTE(CONSTANTCONDITION); \
613 #define EFSYS_KMEM_ALLOC(_esip, _size, _p) \
616 (_p) = rte_zmalloc("sfc", (_size), 0); \
617 _NOTE(CONSTANTCONDITION); \
620 #define EFSYS_KMEM_FREE(_esip, _size, _p) \
625 _NOTE(CONSTANTCONDITION); \
630 typedef rte_spinlock_t efsys_lock_t;
632 #define SFC_EFSYS_LOCK_INIT(_eslp, _ifname, _label) \
633 rte_spinlock_init((_eslp))
634 #define SFC_EFSYS_LOCK_DESTROY(_eslp) ((void)0)
635 #define SFC_EFSYS_LOCK(_eslp) \
636 rte_spinlock_lock((_eslp))
637 #define SFC_EFSYS_UNLOCK(_eslp) \
638 rte_spinlock_unlock((_eslp))
639 #define SFC_EFSYS_LOCK_ASSERT_OWNED(_eslp) \
640 SFC_EFX_ASSERT(rte_spinlock_is_locked((_eslp)))
642 typedef int efsys_lock_state_t;
644 #define EFSYS_LOCK_MAGIC 0x000010c4
646 #define EFSYS_LOCK(_lockp, _state) \
648 SFC_EFSYS_LOCK(_lockp); \
649 (_state) = EFSYS_LOCK_MAGIC; \
650 _NOTE(CONSTANTCONDITION); \
653 #define EFSYS_UNLOCK(_lockp, _state) \
655 SFC_EFX_ASSERT((_state) == EFSYS_LOCK_MAGIC); \
656 SFC_EFSYS_UNLOCK(_lockp); \
657 _NOTE(CONSTANTCONDITION); \
662 typedef uint64_t efsys_stat_t;
664 #define EFSYS_STAT_INCR(_knp, _delta) \
666 *(_knp) += (_delta); \
667 _NOTE(CONSTANTCONDITION); \
670 #define EFSYS_STAT_DECR(_knp, _delta) \
672 *(_knp) -= (_delta); \
673 _NOTE(CONSTANTCONDITION); \
676 #define EFSYS_STAT_SET(_knp, _val) \
679 _NOTE(CONSTANTCONDITION); \
682 #define EFSYS_STAT_SET_QWORD(_knp, _valp) \
684 *(_knp) = rte_le_to_cpu_64((_valp)->eq_u64[0]); \
685 _NOTE(CONSTANTCONDITION); \
688 #define EFSYS_STAT_SET_DWORD(_knp, _valp) \
690 *(_knp) = rte_le_to_cpu_32((_valp)->ed_u32[0]); \
691 _NOTE(CONSTANTCONDITION); \
694 #define EFSYS_STAT_INCR_QWORD(_knp, _valp) \
696 *(_knp) += rte_le_to_cpu_64((_valp)->eq_u64[0]); \
697 _NOTE(CONSTANTCONDITION); \
700 #define EFSYS_STAT_SUBR_QWORD(_knp, _valp) \
702 *(_knp) -= rte_le_to_cpu_64((_valp)->eq_u64[0]); \
703 _NOTE(CONSTANTCONDITION); \
708 #if EFSYS_OPT_DECODE_INTR_FATAL
709 #define EFSYS_ERR(_esip, _code, _dword0, _dword1) \
712 SFC_EFX_LOG(ERR, "FATAL ERROR #%u (0x%08x%08x)", \
713 (_code), (_dword0), (_dword1)); \
714 _NOTE(CONSTANTCONDITION); \
720 /* RTE_VERIFY from DPDK treats expressions with % operator incorrectly,
721 * so we re-implement it here
723 #ifdef RTE_LIBRTE_SFC_EFX_DEBUG
724 #define EFSYS_ASSERT(_exp) \
726 if (unlikely(!(_exp))) \
727 rte_panic("line %d\tassert \"%s\" failed\n", \
728 __LINE__, (#_exp)); \
731 #define EFSYS_ASSERT(_exp) (void)(_exp)
734 #define EFSYS_ASSERT3(_x, _op, _y, _t) EFSYS_ASSERT((_t)(_x) _op (_t)(_y))
736 #define EFSYS_ASSERT3U(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, uint64_t)
737 #define EFSYS_ASSERT3S(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, int64_t)
738 #define EFSYS_ASSERT3P(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, uintptr_t)
742 #define EFSYS_HAS_ROTL_DWORD 0
746 typedef struct efsys_pci_config_s {
747 struct rte_pci_device *espc_dev;
748 } efsys_pci_config_t;
754 #endif /* _SFC_COMMON_EFSYS_H */