net/ngbe: support packet type query
[dpdk.git] / drivers / common / sfc_efx / version.map
1 INTERNAL {
2         global:
3
4         efx_crc32_calculate;
5
6         efx_ev_fini;
7         efx_ev_init;
8         efx_ev_qcreate;
9         efx_ev_qcreate_check_init_done;
10         efx_ev_qcreate_irq;
11         efx_ev_qdestroy;
12         efx_ev_qmoderate;
13         efx_ev_qpending;
14         efx_ev_qpoll;
15         efx_ev_qpost;
16         efx_ev_qprime;
17         efx_ev_usecs_to_ticks;
18
19         efx_evb_fini;
20         efx_evb_init;
21         efx_evb_vport_mac_set;
22         efx_evb_vport_reset;
23         efx_evb_vport_stats;
24         efx_evb_vport_vlan_set;
25         efx_evb_vswitch_create;
26         efx_evb_vswitch_destroy;
27
28         efx_evq_nbufs;
29         efx_evq_size;
30
31         efx_family;
32         efx_family_probe_bar;
33
34         efx_filter_fini;
35         efx_filter_init;
36         efx_filter_insert;
37         efx_filter_remove;
38         efx_filter_restore;
39         efx_filter_spec_init_rx;
40         efx_filter_spec_init_tx;
41         efx_filter_spec_set_encap_type;
42         efx_filter_spec_set_eth_local;
43         efx_filter_spec_set_ether_type;
44         efx_filter_spec_set_geneve;
45         efx_filter_spec_set_ipv4_full;
46         efx_filter_spec_set_ipv4_local;
47         efx_filter_spec_set_mc_def;
48         efx_filter_spec_set_nvgre;
49         efx_filter_spec_set_rss_context;
50         efx_filter_spec_set_uc_def;
51         efx_filter_spec_set_vxlan;
52         efx_filter_supported_filters;
53
54         efx_hash_bytes;
55         efx_hash_dwords;
56
57         efx_intr_disable;
58         efx_intr_disable_unlocked;
59         efx_intr_enable;
60         efx_intr_fatal;
61         efx_intr_fini;
62         efx_intr_init;
63         efx_intr_status_line;
64         efx_intr_status_message;
65         efx_intr_trigger;
66
67         efx_loopback_mask;
68         efx_loopback_type_name;
69
70         efx_mac_addr_set;
71         efx_mac_drain;
72         efx_mac_fcntl_get;
73         efx_mac_fcntl_set;
74         efx_mac_filter_default_rxq_clear;
75         efx_mac_filter_default_rxq_set;
76         efx_mac_filter_get_all_ucast_mcast;
77         efx_mac_filter_set;
78         efx_mac_multicast_list_set;
79         efx_mac_pdu_get;
80         efx_mac_pdu_set;
81         efx_mac_stat_name;
82         efx_mac_stats_clear;
83         efx_mac_stats_get_mask;
84         efx_mac_stats_periodic;
85         efx_mac_stats_update;
86         efx_mac_stats_upload;
87         efx_mac_up;
88
89         efx_mae_action_rule_insert;
90         efx_mae_action_rule_remove;
91         efx_mae_action_set_alloc;
92         efx_mae_action_set_fill_in_counter_id;
93         efx_mae_action_set_fill_in_eh_id;
94         efx_mae_action_set_free;
95         efx_mae_action_set_get_nb_count;
96         efx_mae_action_set_populate_count;
97         efx_mae_action_set_populate_decap;
98         efx_mae_action_set_populate_deliver;
99         efx_mae_action_set_populate_drop;
100         efx_mae_action_set_populate_encap;
101         efx_mae_action_set_populate_flag;
102         efx_mae_action_set_populate_mark;
103         efx_mae_action_set_populate_vlan_pop;
104         efx_mae_action_set_populate_vlan_push;
105         efx_mae_action_set_spec_fini;
106         efx_mae_action_set_spec_init;
107         efx_mae_action_set_specs_equal;
108         efx_mae_counters_alloc;
109         efx_mae_counters_free;
110         efx_mae_counters_stream_give_credits;
111         efx_mae_counters_stream_start;
112         efx_mae_counters_stream_stop;
113         efx_mae_encap_header_alloc;
114         efx_mae_encap_header_free;
115         efx_mae_fini;
116         efx_mae_get_limits;
117         efx_mae_init;
118         efx_mae_match_spec_bit_set;
119         efx_mae_match_spec_field_set;
120         efx_mae_match_spec_fini;
121         efx_mae_match_spec_init;
122         efx_mae_match_spec_is_valid;
123         efx_mae_match_spec_mport_set;
124         efx_mae_match_spec_outer_rule_id_set;
125         efx_mae_match_spec_recirc_id_set;
126         efx_mae_match_specs_class_cmp;
127         efx_mae_match_specs_equal;
128         efx_mae_mport_by_pcie_function;
129         efx_mae_mport_by_pcie_mh_function;
130         efx_mae_mport_by_phy_port;
131         efx_mae_mport_by_id;
132         efx_mae_mport_free;
133         efx_mae_mport_id_by_selector;
134         efx_mae_mport_invalid;
135         efx_mae_outer_rule_insert;
136         efx_mae_outer_rule_recirc_id_set;
137         efx_mae_outer_rule_remove;
138         efx_mae_read_mport_journal;
139
140         efx_mcdi_fini;
141         efx_mcdi_get_client_handle;
142         efx_mcdi_get_own_client_handle;
143         efx_mcdi_get_proxy_handle;
144         efx_mcdi_get_timeout;
145         efx_mcdi_init;
146         efx_mcdi_mport_alloc_alias;
147         efx_mcdi_new_epoch;
148         efx_mcdi_reboot;
149         efx_mcdi_request_abort;
150         efx_mcdi_request_poll;
151         efx_mcdi_request_start;
152
153         efx_mon_fini;
154         efx_mon_init;
155         efx_mon_name;
156
157         efx_nic_calculate_pcie_link_bandwidth;
158         efx_nic_cfg_get;
159         efx_nic_check_pcie_link_speed;
160         efx_nic_create;
161         efx_nic_destroy;
162         efx_nic_fini;
163         efx_nic_get_bar_region;
164         efx_nic_get_board_info;
165         efx_nic_get_fw_subvariant;
166         efx_nic_get_fw_version;
167         efx_nic_get_vi_pool;
168         efx_nic_hw_unavailable;
169         efx_nic_init;
170         efx_nic_probe;
171         efx_nic_reset;
172         efx_nic_set_drv_limits;
173         efx_nic_set_drv_version;
174         efx_nic_set_fw_subvariant;
175         efx_nic_set_hw_unavailable;
176         efx_nic_unprobe;
177
178         efx_phy_adv_cap_get;
179         efx_phy_adv_cap_set;
180         efx_phy_fec_type_get;
181         efx_phy_link_state_get;
182         efx_phy_lp_cap_get;
183         efx_phy_media_type_get;
184         efx_phy_module_get_info;
185         efx_phy_oui_get;
186         efx_phy_verify;
187
188         efx_port_fini;
189         efx_port_init;
190         efx_port_loopback_set;
191         efx_port_poll;
192
193         efx_pseudo_hdr_hash_get;
194         efx_pseudo_hdr_pkt_length_get;
195
196         efx_rx_fini;
197         efx_rx_hash_default_support_get;
198         efx_rx_init;
199         efx_rx_prefix_get_layout;
200         efx_rx_prefix_layout_check;
201         efx_rx_qcreate;
202         efx_rx_qcreate_es_super_buffer;
203         efx_rx_qdestroy;
204         efx_rx_qenable;
205         efx_rx_qflush;
206         efx_rx_qpost;
207         efx_rx_qpush;
208         efx_rx_scale_context_alloc;
209         efx_rx_scale_context_free;
210         efx_rx_scale_default_support_get;
211         efx_rx_scale_hash_flags_get;
212         efx_rx_scale_key_set;
213         efx_rx_scale_mode_set;
214         efx_rx_scale_tbl_set;
215         efx_rxq_nbufs;
216         efx_rxq_size;
217
218         efx_sram_buf_tbl_clear;
219         efx_sram_buf_tbl_set;
220
221         efx_tunnel_config_clear;
222         efx_tunnel_config_udp_add;
223         efx_tunnel_config_udp_remove;
224         efx_tunnel_fini;
225         efx_tunnel_init;
226         efx_tunnel_reconfigure;
227
228         efx_tx_fini;
229         efx_tx_init;
230         efx_tx_qcreate;
231         efx_tx_qdesc_checksum_create;
232         efx_tx_qdesc_dma_create;
233         efx_tx_qdesc_post;
234         efx_tx_qdesc_tso_create;
235         efx_tx_qdesc_tso2_create;
236         efx_tx_qdesc_vlantci_create;
237         efx_tx_qdestroy;
238         efx_tx_qenable;
239         efx_tx_qflush;
240         efx_tx_qpace;
241         efx_tx_qpio_disable;
242         efx_tx_qpio_enable;
243         efx_tx_qpio_post;
244         efx_tx_qpio_write;
245         efx_tx_qpost;
246         efx_tx_qpush;
247         efx_txq_nbufs;
248         efx_txq_size;
249
250         sfc_efx_dev_class_get;
251         sfc_efx_family;
252
253         sfc_efx_mcdi_init;
254         sfc_efx_mcdi_fini;
255
256         local: *;
257 };