9 efx_ev_qcreate_check_init_done;
17 efx_ev_usecs_to_ticks;
21 efx_evb_vport_mac_set;
24 efx_evb_vport_vlan_set;
25 efx_evb_vswitch_create;
26 efx_evb_vswitch_destroy;
39 efx_filter_spec_init_rx;
40 efx_filter_spec_init_tx;
41 efx_filter_spec_set_encap_type;
42 efx_filter_spec_set_eth_local;
43 efx_filter_spec_set_ether_type;
44 efx_filter_spec_set_geneve;
45 efx_filter_spec_set_ipv4_full;
46 efx_filter_spec_set_ipv4_local;
47 efx_filter_spec_set_mc_def;
48 efx_filter_spec_set_nvgre;
49 efx_filter_spec_set_rss_context;
50 efx_filter_spec_set_uc_def;
51 efx_filter_spec_set_vxlan;
52 efx_filter_supported_filters;
58 efx_intr_disable_unlocked;
64 efx_intr_status_message;
68 efx_loopback_type_name;
74 efx_mac_filter_default_rxq_clear;
75 efx_mac_filter_default_rxq_set;
76 efx_mac_filter_get_all_ucast_mcast;
78 efx_mac_multicast_list_set;
83 efx_mac_stats_get_mask;
84 efx_mac_stats_periodic;
89 efx_mae_action_rule_insert;
90 efx_mae_action_rule_remove;
91 efx_mae_action_set_alloc;
92 efx_mae_action_set_fill_in_counter_id;
93 efx_mae_action_set_fill_in_eh_id;
94 efx_mae_action_set_free;
95 efx_mae_action_set_get_nb_count;
96 efx_mae_action_set_populate_count;
97 efx_mae_action_set_populate_decap;
98 efx_mae_action_set_populate_deliver;
99 efx_mae_action_set_populate_drop;
100 efx_mae_action_set_populate_encap;
101 efx_mae_action_set_populate_flag;
102 efx_mae_action_set_populate_mark;
103 efx_mae_action_set_populate_vlan_pop;
104 efx_mae_action_set_populate_vlan_push;
105 efx_mae_action_set_spec_fini;
106 efx_mae_action_set_spec_init;
107 efx_mae_action_set_specs_equal;
108 efx_mae_counters_alloc;
109 efx_mae_counters_free;
110 efx_mae_counters_stream_give_credits;
111 efx_mae_counters_stream_start;
112 efx_mae_counters_stream_stop;
113 efx_mae_encap_header_alloc;
114 efx_mae_encap_header_free;
118 efx_mae_match_spec_bit_set;
119 efx_mae_match_spec_field_set;
120 efx_mae_match_spec_fini;
121 efx_mae_match_spec_init;
122 efx_mae_match_spec_is_valid;
123 efx_mae_match_spec_mport_set;
124 efx_mae_match_spec_outer_rule_id_set;
125 efx_mae_match_spec_recirc_id_set;
126 efx_mae_match_specs_class_cmp;
127 efx_mae_match_specs_equal;
128 efx_mae_mport_by_pcie_function;
129 efx_mae_mport_by_pcie_mh_function;
130 efx_mae_mport_by_phy_port;
133 efx_mae_mport_id_by_selector;
134 efx_mae_mport_invalid;
135 efx_mae_outer_rule_insert;
136 efx_mae_outer_rule_recirc_id_set;
137 efx_mae_outer_rule_remove;
138 efx_mae_read_mport_journal;
141 efx_mcdi_get_client_handle;
142 efx_mcdi_get_own_client_handle;
143 efx_mcdi_get_proxy_handle;
144 efx_mcdi_get_timeout;
146 efx_mcdi_mport_alloc_alias;
149 efx_mcdi_request_abort;
150 efx_mcdi_request_poll;
151 efx_mcdi_request_start;
157 efx_nic_calculate_pcie_link_bandwidth;
159 efx_nic_check_pcie_link_speed;
163 efx_nic_get_bar_region;
164 efx_nic_get_board_info;
165 efx_nic_get_fw_subvariant;
166 efx_nic_get_fw_version;
168 efx_nic_hw_unavailable;
172 efx_nic_set_drv_limits;
173 efx_nic_set_drv_version;
174 efx_nic_set_fw_subvariant;
175 efx_nic_set_hw_unavailable;
180 efx_phy_fec_type_get;
181 efx_phy_link_state_get;
183 efx_phy_media_type_get;
184 efx_phy_module_get_info;
190 efx_port_loopback_set;
193 efx_pseudo_hdr_hash_get;
194 efx_pseudo_hdr_pkt_length_get;
197 efx_rx_hash_default_support_get;
199 efx_rx_prefix_get_layout;
200 efx_rx_prefix_layout_check;
202 efx_rx_qcreate_es_super_buffer;
208 efx_rx_scale_context_alloc;
209 efx_rx_scale_context_free;
210 efx_rx_scale_default_support_get;
211 efx_rx_scale_hash_flags_get;
212 efx_rx_scale_key_set;
213 efx_rx_scale_mode_set;
214 efx_rx_scale_tbl_set;
218 efx_sram_buf_tbl_clear;
219 efx_sram_buf_tbl_set;
221 efx_tunnel_config_clear;
222 efx_tunnel_config_udp_add;
223 efx_tunnel_config_udp_remove;
226 efx_tunnel_reconfigure;
231 efx_tx_qdesc_checksum_create;
232 efx_tx_qdesc_dma_create;
234 efx_tx_qdesc_tso_create;
235 efx_tx_qdesc_tso2_create;
236 efx_tx_qdesc_vlantci_create;
250 sfc_efx_dev_class_get;