drivers/common/sfc_efx/version.map

   1 INTERNAL {
   2         global:
   3
   4         efx_crc32_calculate;
   5
   6         efx_ev_fini;
   7         efx_ev_init;
   8         efx_ev_qcreate;
   9         efx_ev_qcreate_check_init_done;
  10         efx_ev_qcreate_irq;
  11         efx_ev_qdestroy;
  12         efx_ev_qmoderate;
  13         efx_ev_qpending;
  14         efx_ev_qpoll;
  15         efx_ev_qpost;
  16         efx_ev_qprime;
  17         efx_ev_usecs_to_ticks;
  18
  19         efx_evb_fini;
  20         efx_evb_init;
  21         efx_evb_vport_mac_set;
  22         efx_evb_vport_reset;
  23         efx_evb_vport_stats;
  24         efx_evb_vport_vlan_set;
  25         efx_evb_vswitch_create;
  26         efx_evb_vswitch_destroy;
  27
  28         efx_evq_nbufs;
  29         efx_evq_size;
  30
  31         efx_family;
  32         efx_family_probe_bar;
  33
  34         efx_filter_fini;
  35         efx_filter_init;
  36         efx_filter_insert;
  37         efx_filter_remove;
  38         efx_filter_restore;
  39         efx_filter_spec_init_rx;
  40         efx_filter_spec_init_tx;
  41         efx_filter_spec_set_encap_type;
  42         efx_filter_spec_set_eth_local;
  43         efx_filter_spec_set_ether_type;
  44         efx_filter_spec_set_geneve;
  45         efx_filter_spec_set_ipv4_full;
  46         efx_filter_spec_set_ipv4_local;
  47         efx_filter_spec_set_mc_def;
  48         efx_filter_spec_set_nvgre;
  49         efx_filter_spec_set_rss_context;
  50         efx_filter_spec_set_uc_def;
  51         efx_filter_spec_set_vxlan;
  52         efx_filter_supported_filters;
  53
  54         efx_hash_bytes;
  55         efx_hash_dwords;
  56
  57         efx_intr_disable;
  58         efx_intr_disable_unlocked;
  59         efx_intr_enable;
  60         efx_intr_fatal;
  61         efx_intr_fini;
  62         efx_intr_init;
  63         efx_intr_status_line;
  64         efx_intr_status_message;
  65         efx_intr_trigger;
  66
  67         efx_loopback_mask;
  68         efx_loopback_type_name;
  69
  70         efx_mac_addr_set;
  71         efx_mac_drain;
  72         efx_mac_fcntl_get;
  73         efx_mac_fcntl_set;
  74         efx_mac_filter_default_rxq_clear;
  75         efx_mac_filter_default_rxq_set;
  76         efx_mac_filter_get_all_ucast_mcast;
  77         efx_mac_filter_set;
  78         efx_mac_multicast_list_set;
  79         efx_mac_pdu_get;
  80         efx_mac_pdu_set;
  81         efx_mac_stat_name;
  82         efx_mac_stats_clear;
  83         efx_mac_stats_get_mask;
  84         efx_mac_stats_periodic;
  85         efx_mac_stats_update;
  86         efx_mac_stats_upload;
  87         efx_mac_up;
  88
  89         efx_mae_action_rule_insert;
  90         efx_mae_action_rule_remove;
  91         efx_mae_action_set_alloc;
  92         efx_mae_action_set_fill_in_eh_id;
  93         efx_mae_action_set_free;
  94         efx_mae_action_set_populate_decap;
  95         efx_mae_action_set_populate_deliver;
  96         efx_mae_action_set_populate_drop;
  97         efx_mae_action_set_populate_encap;
  98         efx_mae_action_set_populate_flag;
  99         efx_mae_action_set_populate_mark;
 100         efx_mae_action_set_populate_vlan_pop;
 101         efx_mae_action_set_populate_vlan_push;
 102         efx_mae_action_set_spec_fini;
 103         efx_mae_action_set_spec_init;
 104         efx_mae_action_set_specs_equal;
 105         efx_mae_counters_alloc;
 106         efx_mae_counters_free;
 107         efx_mae_counters_stream_give_credits;
 108         efx_mae_counters_stream_start;
 109         efx_mae_counters_stream_stop;
 110         efx_mae_encap_header_alloc;
 111         efx_mae_encap_header_free;
 112         efx_mae_fini;
 113         efx_mae_get_limits;
 114         efx_mae_init;
 115         efx_mae_match_spec_bit_set;
 116         efx_mae_match_spec_field_set;
 117         efx_mae_match_spec_fini;
 118         efx_mae_match_spec_init;
 119         efx_mae_match_spec_is_valid;
 120         efx_mae_match_spec_mport_set;
 121         efx_mae_match_spec_outer_rule_id_set;
 122         efx_mae_match_specs_class_cmp;
 123         efx_mae_match_specs_equal;
 124         efx_mae_mport_by_pcie_function;
 125         efx_mae_mport_by_phy_port;
 126         efx_mae_outer_rule_insert;
 127         efx_mae_outer_rule_remove;
 128
 129         efx_mcdi_fini;
 130         efx_mcdi_get_proxy_handle;
 131         efx_mcdi_get_timeout;
 132         efx_mcdi_init;
 133         efx_mcdi_new_epoch;
 134         efx_mcdi_reboot;
 135         efx_mcdi_request_abort;
 136         efx_mcdi_request_poll;
 137         efx_mcdi_request_start;
 138
 139         efx_mon_fini;
 140         efx_mon_init;
 141         efx_mon_name;
 142
 143         efx_nic_calculate_pcie_link_bandwidth;
 144         efx_nic_cfg_get;
 145         efx_nic_check_pcie_link_speed;
 146         efx_nic_create;
 147         efx_nic_destroy;
 148         efx_nic_fini;
 149         efx_nic_get_bar_region;
 150         efx_nic_get_board_info;
 151         efx_nic_get_fw_subvariant;
 152         efx_nic_get_fw_version;
 153         efx_nic_get_vi_pool;
 154         efx_nic_hw_unavailable;
 155         efx_nic_init;
 156         efx_nic_probe;
 157         efx_nic_reset;
 158         efx_nic_set_drv_limits;
 159         efx_nic_set_drv_version;
 160         efx_nic_set_fw_subvariant;
 161         efx_nic_set_hw_unavailable;
 162         efx_nic_unprobe;
 163
 164         efx_phy_adv_cap_get;
 165         efx_phy_adv_cap_set;
 166         efx_phy_fec_type_get;
 167         efx_phy_link_state_get;
 168         efx_phy_lp_cap_get;
 169         efx_phy_media_type_get;
 170         efx_phy_module_get_info;
 171         efx_phy_oui_get;
 172         efx_phy_verify;
 173
 174         efx_port_fini;
 175         efx_port_init;
 176         efx_port_loopback_set;
 177         efx_port_poll;
 178
 179         efx_pseudo_hdr_hash_get;
 180         efx_pseudo_hdr_pkt_length_get;
 181
 182         efx_rx_fini;
 183         efx_rx_hash_default_support_get;
 184         efx_rx_init;
 185         efx_rx_prefix_get_layout;
 186         efx_rx_prefix_layout_check;
 187         efx_rx_qcreate;
 188         efx_rx_qcreate_es_super_buffer;
 189         efx_rx_qdestroy;
 190         efx_rx_qenable;
 191         efx_rx_qflush;
 192         efx_rx_qpost;
 193         efx_rx_qpush;
 194         efx_rx_scale_context_alloc;
 195         efx_rx_scale_context_free;
 196         efx_rx_scale_default_support_get;
 197         efx_rx_scale_hash_flags_get;
 198         efx_rx_scale_key_set;
 199         efx_rx_scale_mode_set;
 200         efx_rx_scale_tbl_set;
 201         efx_rxq_nbufs;
 202         efx_rxq_size;
 203
 204         efx_sram_buf_tbl_clear;
 205         efx_sram_buf_tbl_set;
 206
 207         efx_tunnel_config_clear;
 208         efx_tunnel_config_udp_add;
 209         efx_tunnel_config_udp_remove;
 210         efx_tunnel_fini;
 211         efx_tunnel_init;
 212         efx_tunnel_reconfigure;
 213
 214         efx_tx_fini;
 215         efx_tx_init;
 216         efx_tx_qcreate;
 217         efx_tx_qdesc_checksum_create;
 218         efx_tx_qdesc_dma_create;
 219         efx_tx_qdesc_post;
 220         efx_tx_qdesc_tso_create;
 221         efx_tx_qdesc_tso2_create;
 222         efx_tx_qdesc_vlantci_create;
 223         efx_tx_qdestroy;
 224         efx_tx_qenable;
 225         efx_tx_qflush;
 226         efx_tx_qpace;
 227         efx_tx_qpio_disable;
 228         efx_tx_qpio_enable;
 229         efx_tx_qpio_post;
 230         efx_tx_qpio_write;
 231         efx_tx_qpost;
 232         efx_tx_qpush;
 233         efx_txq_nbufs;
 234         efx_txq_size;
 235
 236         sfc_efx_dev_class_get;
 237         sfc_efx_family;
 238
 239         sfc_efx_mcdi_init;
 240         sfc_efx_mcdi_fini;
 241
 242         local: *;
 243 };