drivers/compress/mlx5/mlx5_compress.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_log.h>
   7 #include <rte_errno.h>
   8 #include <rte_pci.h>
   9 #include <rte_spinlock.h>
  10 #include <rte_comp.h>
  11 #include <rte_compressdev.h>
  12 #include <rte_compressdev_pmd.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_common.h>
  16 #include <mlx5_common_pci.h>
  17 #include <mlx5_devx_cmds.h>
  18 #include <mlx5_common_os.h>
  19 #include <mlx5_common_devx.h>
  20 #include <mlx5_common_mr.h>
  21 #include <mlx5_prm.h>
  22
  23 #include "mlx5_compress_utils.h"
  24
  25 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
  26 #define MLX5_COMPRESS_LOG_NAME    pmd.compress.mlx5
  27 #define MLX5_COMPRESS_MAX_QPS 1024
  28 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
  29
  30 struct mlx5_compress_xform {
  31         LIST_ENTRY(mlx5_compress_xform) next;
  32         enum rte_comp_xform_type type;
  33         enum rte_comp_checksum_type csum_type;
  34         uint32_t opcode;
  35         uint32_t gga_ctrl1; /* BE. */
  36 };
  37
  38 struct mlx5_compress_priv {
  39         TAILQ_ENTRY(mlx5_compress_priv) next;
  40         struct ibv_context *ctx; /* Device context. */
  41         struct rte_pci_device *pci_dev;
  42         struct rte_compressdev *cdev;
  43         void *uar;
  44         uint32_t pdn; /* Protection Domain number. */
  45         uint8_t min_block_size;
  46         /* Minimum huffman block size supported by the device. */
  47         struct ibv_pd *pd;
  48         struct rte_compressdev_config dev_config;
  49         LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
  50         rte_spinlock_t xform_sl;
  51         struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
  52 };
  53
  54 struct mlx5_compress_qp {
  55         uint16_t qp_id;
  56         uint16_t entries_n;
  57         uint16_t pi;
  58         uint16_t ci;
  59         volatile uint64_t *uar_addr;
  60         struct mlx5_mr_ctrl mr_ctrl;
  61         int socket_id;
  62         struct mlx5_devx_cq cq;
  63         struct mlx5_devx_sq sq;
  64         struct mlx5_pmd_mr opaque_mr;
  65         struct rte_comp_op **ops;
  66         struct mlx5_compress_priv *priv;
  67 };
  68
  69 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
  70                                 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
  71 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
  72
  73 int mlx5_compress_logtype;
  74
  75 const struct rte_compressdev_capabilities mlx5_caps[RTE_COMP_ALGO_LIST_END];
  76
  77
  78 static void
  79 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
  80                            struct rte_compressdev_info *info)
  81 {
  82         RTE_SET_USED(dev);
  83         if (info != NULL) {
  84                 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
  85                 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
  86                 info->capabilities = mlx5_caps;
  87         }
  88 }
  89
  90 static int
  91 mlx5_compress_dev_configure(struct rte_compressdev *dev,
  92                             struct rte_compressdev_config *config)
  93 {
  94         struct mlx5_compress_priv *priv;
  95
  96         if (dev == NULL || config == NULL)
  97                 return -EINVAL;
  98         priv = dev->data->dev_private;
  99         priv->dev_config = *config;
 100         return 0;
 101 }
 102
 103 static int
 104 mlx5_compress_dev_close(struct rte_compressdev *dev)
 105 {
 106         RTE_SET_USED(dev);
 107         return 0;
 108 }
 109
 110 static int
 111 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
 112 {
 113         struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 114
 115         if (qp->sq.sq != NULL)
 116                 mlx5_devx_sq_destroy(&qp->sq);
 117         if (qp->cq.cq != NULL)
 118                 mlx5_devx_cq_destroy(&qp->cq);
 119         if (qp->opaque_mr.obj != NULL) {
 120                 void *opaq = qp->opaque_mr.addr;
 121
 122                 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
 123                 if (opaq != NULL)
 124                         rte_free(opaq);
 125         }
 126         mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
 127         rte_free(qp);
 128         dev->data->queue_pairs[qp_id] = NULL;
 129         return 0;
 130 }
 131
 132 static void
 133 mlx5_compress_init_sq(struct mlx5_compress_qp *qp)
 134 {
 135         volatile struct mlx5_gga_wqe *restrict wqe =
 136                                     (volatile struct mlx5_gga_wqe *)qp->sq.wqes;
 137         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 138         const uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u);
 139         const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 140                                         MLX5_COMP_MODE_OFFSET);
 141         const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
 142         int i;
 143
 144         /* All the next fields state should stay constant. */
 145         for (i = 0; i < qp->entries_n; ++i, ++wqe) {
 146                 wqe->sq_ds = sq_ds;
 147                 wqe->flags = flags;
 148                 wqe->opaque_lkey = opaq_lkey;
 149                 wqe->opaque_vaddr = rte_cpu_to_be_64
 150                                                 ((uint64_t)(uintptr_t)&opaq[i]);
 151         }
 152 }
 153
 154 static int
 155 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 156                        uint32_t max_inflight_ops, int socket_id)
 157 {
 158         struct mlx5_compress_priv *priv = dev->data->dev_private;
 159         struct mlx5_compress_qp *qp;
 160         struct mlx5_devx_cq_attr cq_attr = {
 161                 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
 162         };
 163         struct mlx5_devx_create_sq_attr sq_attr = {
 164                 .user_index = qp_id,
 165                 .wq_attr = (struct mlx5_devx_wq_attr){
 166                         .pd = priv->pdn,
 167                         .uar_page = mlx5_os_get_devx_uar_page_id(priv->uar),
 168                 },
 169         };
 170         struct mlx5_devx_modify_sq_attr modify_attr = {
 171                 .state = MLX5_SQC_STATE_RDY,
 172         };
 173         uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
 174         uint32_t alloc_size = sizeof(*qp);
 175         void *opaq_buf;
 176         int ret;
 177
 178         alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
 179         alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
 180         qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
 181                                 socket_id);
 182         if (qp == NULL) {
 183                 DRV_LOG(ERR, "Failed to allocate qp memory.");
 184                 rte_errno = ENOMEM;
 185                 return -rte_errno;
 186         }
 187         dev->data->queue_pairs[qp_id] = qp;
 188         opaq_buf = rte_calloc(__func__, 1u << log_ops_n,
 189                               sizeof(struct mlx5_gga_compress_opaque),
 190                               sizeof(struct mlx5_gga_compress_opaque));
 191         if (opaq_buf == NULL) {
 192                 DRV_LOG(ERR, "Failed to allocate opaque memory.");
 193                 rte_errno = ENOMEM;
 194                 goto err;
 195         }
 196         if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,
 197                                priv->dev_config.socket_id)) {
 198                 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
 199                         (uint32_t)qp_id);
 200                 rte_errno = ENOMEM;
 201                 goto err;
 202         }
 203         qp->entries_n = 1 << log_ops_n;
 204         qp->socket_id = socket_id;
 205         qp->qp_id = qp_id;
 206         qp->priv = priv;
 207         qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
 208                                                    RTE_CACHE_LINE_SIZE);
 209         qp->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
 210         MLX5_ASSERT(qp->uar_addr);
 211         if (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n *
 212                                         sizeof(struct mlx5_gga_compress_opaque),
 213                                                          &qp->opaque_mr) != 0) {
 214                 rte_free(opaq_buf);
 215                 DRV_LOG(ERR, "Failed to register opaque MR.");
 216                 rte_errno = ENOMEM;
 217                 goto err;
 218         }
 219         ret = mlx5_devx_cq_create(priv->ctx, &qp->cq, log_ops_n, &cq_attr,
 220                                   socket_id);
 221         if (ret != 0) {
 222                 DRV_LOG(ERR, "Failed to create CQ.");
 223                 goto err;
 224         }
 225         sq_attr.cqn = qp->cq.cq->id;
 226         ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,
 227                                   socket_id);
 228         if (ret != 0) {
 229                 DRV_LOG(ERR, "Failed to create SQ.");
 230                 goto err;
 231         }
 232         mlx5_compress_init_sq(qp);
 233         ret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr);
 234         if (ret != 0) {
 235                 DRV_LOG(ERR, "Can't change SQ state to ready.");
 236                 goto err;
 237         }
 238         DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u\n",
 239                 (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n);
 240         return 0;
 241 err:
 242         mlx5_compress_qp_release(dev, qp_id);
 243         return -1;
 244 }
 245
 246 static int
 247 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
 248 {
 249         struct mlx5_compress_priv *priv = dev->data->dev_private;
 250
 251         rte_spinlock_lock(&priv->xform_sl);
 252         LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
 253         rte_spinlock_unlock(&priv->xform_sl);
 254         rte_free(xform);
 255         return 0;
 256 }
 257
 258 static int
 259 mlx5_compress_xform_create(struct rte_compressdev *dev,
 260                            const struct rte_comp_xform *xform,
 261                            void **private_xform)
 262 {
 263         struct mlx5_compress_priv *priv = dev->data->dev_private;
 264         struct mlx5_compress_xform *xfrm;
 265         uint32_t size;
 266
 267         if (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==
 268                                                           RTE_COMP_LEVEL_NONE) {
 269                 DRV_LOG(ERR, "Non-compressed block is not supported.");
 270                 return -ENOTSUP;
 271         }
 272         if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=
 273              RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&
 274                       xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {
 275                 DRV_LOG(ERR, "SHA is not supported.");
 276                 return -ENOTSUP;
 277         }
 278         xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
 279                                                     priv->dev_config.socket_id);
 280         if (xfrm == NULL)
 281                 return -ENOMEM;
 282         xfrm->opcode = MLX5_OPCODE_MMO;
 283         xfrm->type = xform->type;
 284         switch (xform->type) {
 285         case RTE_COMP_COMPRESS:
 286                 switch (xform->compress.algo) {
 287                 case RTE_COMP_ALGO_NULL:
 288                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 289                                                         WQE_CSEG_OPC_MOD_OFFSET;
 290                         break;
 291                 case RTE_COMP_ALGO_DEFLATE:
 292                         size = 1 << xform->compress.window_size;
 293                         size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
 294                         xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 295                                          MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 296                                            WQE_GGA_COMP_WIN_SIZE_OFFSET;
 297                         if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
 298                                 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 299                         else
 300                                 size = priv->min_block_size - 1 +
 301                                                           xform->compress.level;
 302                         xfrm->gga_ctrl1 += RTE_MIN(size,
 303                                             MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
 304                                                  WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 305                         xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
 306                                                         WQE_CSEG_OPC_MOD_OFFSET;
 307                         size = xform->compress.deflate.huffman ==
 308                                                       RTE_COMP_HUFFMAN_DYNAMIC ?
 309                                             MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
 310                                              MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
 311                         xfrm->gga_ctrl1 += size <<
 312                                                WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
 313                         break;
 314                 default:
 315                         goto err;
 316                 }
 317                 xfrm->csum_type = xform->compress.chksum;
 318                 break;
 319         case RTE_COMP_DECOMPRESS:
 320                 switch (xform->decompress.algo) {
 321                 case RTE_COMP_ALGO_NULL:
 322                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 323                                                         WQE_CSEG_OPC_MOD_OFFSET;
 324                         break;
 325                 case RTE_COMP_ALGO_DEFLATE:
 326                         xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
 327                                                         WQE_CSEG_OPC_MOD_OFFSET;
 328                         break;
 329                 default:
 330                         goto err;
 331                 }
 332                 xfrm->csum_type = xform->decompress.chksum;
 333                 break;
 334         default:
 335                 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
 336                 goto err;
 337         }
 338         DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
 339                 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
 340         xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
 341         rte_spinlock_lock(&priv->xform_sl);
 342         LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
 343         rte_spinlock_unlock(&priv->xform_sl);
 344         *private_xform = xfrm;
 345         return 0;
 346 err:
 347         rte_free(xfrm);
 348         return -ENOTSUP;
 349 }
 350
 351 static struct rte_compressdev_ops mlx5_compress_ops = {
 352         .dev_configure          = mlx5_compress_dev_configure,
 353         .dev_start              = NULL,
 354         .dev_stop               = NULL,
 355         .dev_close              = mlx5_compress_dev_close,
 356         .dev_infos_get          = mlx5_compress_dev_info_get,
 357         .stats_get              = NULL,
 358         .stats_reset            = NULL,
 359         .queue_pair_setup       = mlx5_compress_qp_setup,
 360         .queue_pair_release     = mlx5_compress_qp_release,
 361         .private_xform_create   = mlx5_compress_xform_create,
 362         .private_xform_free     = mlx5_compress_xform_free,
 363         .stream_create          = NULL,
 364         .stream_free            = NULL,
 365 };
 366
 367 static struct ibv_device *
 368 mlx5_compress_get_ib_device_match(struct rte_pci_addr *addr)
 369 {
 370         int n;
 371         struct ibv_device **ibv_list = mlx5_glue->get_device_list(&n);
 372         struct ibv_device *ibv_match = NULL;
 373
 374         if (ibv_list == NULL) {
 375                 rte_errno = ENOSYS;
 376                 return NULL;
 377         }
 378         while (n-- > 0) {
 379                 struct rte_pci_addr paddr;
 380
 381                 DRV_LOG(DEBUG, "Checking device \"%s\"..", ibv_list[n]->name);
 382                 if (mlx5_dev_to_pci_addr(ibv_list[n]->ibdev_path, &paddr) != 0)
 383                         continue;
 384                 if (rte_pci_addr_cmp(addr, &paddr) != 0)
 385                         continue;
 386                 ibv_match = ibv_list[n];
 387                 break;
 388         }
 389         if (ibv_match == NULL)
 390                 rte_errno = ENOENT;
 391         mlx5_glue->free_device_list(ibv_list);
 392         return ibv_match;
 393 }
 394
 395 static void
 396 mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv)
 397 {
 398         if (priv->pd != NULL) {
 399                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 400                 priv->pd = NULL;
 401         }
 402         if (priv->uar != NULL) {
 403                 mlx5_glue->devx_free_uar(priv->uar);
 404                 priv->uar = NULL;
 405         }
 406 }
 407
 408 static int
 409 mlx5_compress_pd_create(struct mlx5_compress_priv *priv)
 410 {
 411 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 412         struct mlx5dv_obj obj;
 413         struct mlx5dv_pd pd_info;
 414         int ret;
 415
 416         priv->pd = mlx5_glue->alloc_pd(priv->ctx);
 417         if (priv->pd == NULL) {
 418                 DRV_LOG(ERR, "Failed to allocate PD.");
 419                 return errno ? -errno : -ENOMEM;
 420         }
 421         obj.pd.in = priv->pd;
 422         obj.pd.out = &pd_info;
 423         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 424         if (ret != 0) {
 425                 DRV_LOG(ERR, "Fail to get PD object info.");
 426                 mlx5_glue->dealloc_pd(priv->pd);
 427                 priv->pd = NULL;
 428                 return -errno;
 429         }
 430         priv->pdn = pd_info.pdn;
 431         return 0;
 432 #else
 433         (void)priv;
 434         DRV_LOG(ERR, "Cannot get pdn - no DV support.");
 435         return -ENOTSUP;
 436 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 437 }
 438
 439 static int
 440 mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv)
 441 {
 442         if (mlx5_compress_pd_create(priv) != 0)
 443                 return -1;
 444         priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
 445         if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
 446             NULL) {
 447                 rte_errno = errno;
 448                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 449                 DRV_LOG(ERR, "Failed to allocate UAR.");
 450                 return -1;
 451         }
 452         return 0;
 453 }
 454
 455 /**
 456  * DPDK callback to register a PCI device.
 457  *
 458  * This function spawns compress device out of a given PCI device.
 459  *
 460  * @param[in] pci_drv
 461  *   PCI driver structure (mlx5_compress_driver).
 462  * @param[in] pci_dev
 463  *   PCI device information.
 464  *
 465  * @return
 466  *   0 on success, 1 to skip this driver, a negative errno value otherwise
 467  *   and rte_errno is set.
 468  */
 469 static int
 470 mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv,
 471                         struct rte_pci_device *pci_dev)
 472 {
 473         struct ibv_device *ibv;
 474         struct rte_compressdev *cdev;
 475         struct ibv_context *ctx;
 476         struct mlx5_compress_priv *priv;
 477         struct mlx5_hca_attr att = { 0 };
 478         struct rte_compressdev_pmd_init_params init_params = {
 479                 .name = "",
 480                 .socket_id = pci_dev->device.numa_node,
 481         };
 482
 483         RTE_SET_USED(pci_drv);
 484         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 485                 DRV_LOG(ERR, "Non-primary process type is not supported.");
 486                 rte_errno = ENOTSUP;
 487                 return -rte_errno;
 488         }
 489         ibv = mlx5_compress_get_ib_device_match(&pci_dev->addr);
 490         if (ibv == NULL) {
 491                 DRV_LOG(ERR, "No matching IB device for PCI slot "
 492                         PCI_PRI_FMT ".", pci_dev->addr.domain,
 493                         pci_dev->addr.bus, pci_dev->addr.devid,
 494                         pci_dev->addr.function);
 495                 return -rte_errno;
 496         }
 497         DRV_LOG(INFO, "PCI information matches for device \"%s\".", ibv->name);
 498         ctx = mlx5_glue->dv_open_device(ibv);
 499         if (ctx == NULL) {
 500                 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name);
 501                 rte_errno = ENODEV;
 502                 return -rte_errno;
 503         }
 504         if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 ||
 505             att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 ||
 506             att.mmo_dma_en == 0) {
 507                 DRV_LOG(ERR, "Not enough capabilities to support compress "
 508                         "operations, maybe old FW/OFED version?");
 509                 claim_zero(mlx5_glue->close_device(ctx));
 510                 rte_errno = ENOTSUP;
 511                 return -ENOTSUP;
 512         }
 513         cdev = rte_compressdev_pmd_create(ibv->name, &pci_dev->device,
 514                                           sizeof(*priv), &init_params);
 515         if (cdev == NULL) {
 516                 DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name);
 517                 claim_zero(mlx5_glue->close_device(ctx));
 518                 return -ENODEV;
 519         }
 520         DRV_LOG(INFO,
 521                 "Compress device %s was created successfully.", ibv->name);
 522         cdev->dev_ops = &mlx5_compress_ops;
 523         cdev->dequeue_burst = NULL;
 524         cdev->enqueue_burst = NULL;
 525         cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 526         priv = cdev->data->dev_private;
 527         priv->ctx = ctx;
 528         priv->pci_dev = pci_dev;
 529         priv->cdev = cdev;
 530         priv->min_block_size = att.compress_min_block_size;
 531         if (mlx5_compress_hw_global_prepare(priv) != 0) {
 532                 rte_compressdev_pmd_destroy(priv->cdev);
 533                 claim_zero(mlx5_glue->close_device(priv->ctx));
 534                 return -1;
 535         }
 536         if (mlx5_mr_btree_init(&priv->mr_scache.cache,
 537                              MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {
 538                 DRV_LOG(ERR, "Failed to allocate shared cache MR memory.");
 539                 mlx5_compress_hw_global_release(priv);
 540                 rte_compressdev_pmd_destroy(priv->cdev);
 541                 claim_zero(mlx5_glue->close_device(priv->ctx));
 542                 rte_errno = ENOMEM;
 543                 return -rte_errno;
 544         }
 545         priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;
 546         priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;
 547         pthread_mutex_lock(&priv_list_lock);
 548         TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
 549         pthread_mutex_unlock(&priv_list_lock);
 550         return 0;
 551 }
 552
 553 /**
 554  * DPDK callback to remove a PCI device.
 555  *
 556  * This function removes all compress devices belong to a given PCI device.
 557  *
 558  * @param[in] pci_dev
 559  *   Pointer to the PCI device.
 560  *
 561  * @return
 562  *   0 on success, the function cannot fail.
 563  */
 564 static int
 565 mlx5_compress_pci_remove(struct rte_pci_device *pdev)
 566 {
 567         struct mlx5_compress_priv *priv = NULL;
 568
 569         pthread_mutex_lock(&priv_list_lock);
 570         TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 571                 if (rte_pci_addr_cmp(&priv->pci_dev->addr, &pdev->addr) != 0)
 572                         break;
 573         if (priv)
 574                 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
 575         pthread_mutex_unlock(&priv_list_lock);
 576         if (priv) {
 577                 mlx5_mr_release_cache(&priv->mr_scache);
 578                 mlx5_compress_hw_global_release(priv);
 579                 rte_compressdev_pmd_destroy(priv->cdev);
 580                 claim_zero(mlx5_glue->close_device(priv->ctx));
 581         }
 582         return 0;
 583 }
 584
 585 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
 586         {
 587                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 588                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
 589         },
 590         {
 591                 .vendor_id = 0
 592         }
 593 };
 594
 595 static struct mlx5_pci_driver mlx5_compress_driver = {
 596         .driver_class = MLX5_CLASS_COMPRESS,
 597         .pci_driver = {
 598                 .driver = {
 599                         .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
 600                 },
 601                 .id_table = mlx5_compress_pci_id_map,
 602                 .probe = mlx5_compress_pci_probe,
 603                 .remove = mlx5_compress_pci_remove,
 604                 .drv_flags = 0,
 605         },
 606 };
 607
 608 RTE_INIT(rte_mlx5_compress_init)
 609 {
 610         mlx5_common_init();
 611         if (mlx5_glue != NULL)
 612                 mlx5_pci_driver_register(&mlx5_compress_driver);
 613 }
 614
 615 RTE_LOG_REGISTER(mlx5_compress_logtype, MLX5_COMPRESS_LOG_NAME, NOTICE)
 616 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
 617 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
 618 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");