drivers/compress/mlx5/mlx5_compress.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_log.h>
   7 #include <rte_errno.h>
   8 #include <rte_pci.h>
   9 #include <rte_spinlock.h>
  10 #include <rte_comp.h>
  11 #include <rte_compressdev.h>
  12 #include <rte_compressdev_pmd.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_common.h>
  16 #include <mlx5_common_pci.h>
  17 #include <mlx5_devx_cmds.h>
  18 #include <mlx5_common_os.h>
  19 #include <mlx5_common_devx.h>
  20 #include <mlx5_common_mr.h>
  21 #include <mlx5_prm.h>
  22
  23 #include "mlx5_compress_utils.h"
  24
  25 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
  26 #define MLX5_COMPRESS_LOG_NAME    pmd.compress.mlx5
  27 #define MLX5_COMPRESS_MAX_QPS 1024
  28 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
  29
  30 struct mlx5_compress_xform {
  31         LIST_ENTRY(mlx5_compress_xform) next;
  32         enum rte_comp_xform_type type;
  33         enum rte_comp_checksum_type csum_type;
  34         uint32_t opcode;
  35         uint32_t gga_ctrl1; /* BE. */
  36 };
  37
  38 struct mlx5_compress_priv {
  39         TAILQ_ENTRY(mlx5_compress_priv) next;
  40         struct ibv_context *ctx; /* Device context. */
  41         struct rte_pci_device *pci_dev;
  42         struct rte_compressdev *cdev;
  43         void *uar;
  44         uint32_t pdn; /* Protection Domain number. */
  45         uint8_t min_block_size;
  46         /* Minimum huffman block size supported by the device. */
  47         struct ibv_pd *pd;
  48         struct rte_compressdev_config dev_config;
  49         LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
  50         rte_spinlock_t xform_sl;
  51         struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
  52 };
  53
  54 struct mlx5_compress_qp {
  55         uint16_t qp_id;
  56         uint16_t entries_n;
  57         uint16_t pi;
  58         uint16_t ci;
  59         volatile uint64_t *uar_addr;
  60         struct mlx5_mr_ctrl mr_ctrl;
  61         int socket_id;
  62         struct mlx5_devx_cq cq;
  63         struct mlx5_devx_sq sq;
  64         struct mlx5_pmd_mr opaque_mr;
  65         struct rte_comp_op **ops;
  66         struct mlx5_compress_priv *priv;
  67 };
  68
  69 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
  70                                 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
  71 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
  72
  73 int mlx5_compress_logtype;
  74
  75 const struct rte_compressdev_capabilities mlx5_caps[RTE_COMP_ALGO_LIST_END];
  76
  77
  78 static void
  79 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
  80                            struct rte_compressdev_info *info)
  81 {
  82         RTE_SET_USED(dev);
  83         if (info != NULL) {
  84                 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
  85                 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
  86                 info->capabilities = mlx5_caps;
  87         }
  88 }
  89
  90 static int
  91 mlx5_compress_dev_configure(struct rte_compressdev *dev,
  92                             struct rte_compressdev_config *config)
  93 {
  94         struct mlx5_compress_priv *priv;
  95
  96         if (dev == NULL || config == NULL)
  97                 return -EINVAL;
  98         priv = dev->data->dev_private;
  99         priv->dev_config = *config;
 100         return 0;
 101 }
 102
 103 static int
 104 mlx5_compress_dev_close(struct rte_compressdev *dev)
 105 {
 106         RTE_SET_USED(dev);
 107         return 0;
 108 }
 109
 110 static int
 111 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
 112 {
 113         struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 114
 115         if (qp->sq.sq != NULL)
 116                 mlx5_devx_sq_destroy(&qp->sq);
 117         if (qp->cq.cq != NULL)
 118                 mlx5_devx_cq_destroy(&qp->cq);
 119         if (qp->opaque_mr.obj != NULL) {
 120                 void *opaq = qp->opaque_mr.addr;
 121
 122                 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
 123                 if (opaq != NULL)
 124                         rte_free(opaq);
 125         }
 126         mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
 127         rte_free(qp);
 128         dev->data->queue_pairs[qp_id] = NULL;
 129         return 0;
 130 }
 131
 132 static void
 133 mlx5_compress_init_sq(struct mlx5_compress_qp *qp)
 134 {
 135         volatile struct mlx5_gga_wqe *restrict wqe =
 136                                     (volatile struct mlx5_gga_wqe *)qp->sq.wqes;
 137         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 138         const uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u);
 139         const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 140                                         MLX5_COMP_MODE_OFFSET);
 141         const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
 142         int i;
 143
 144         /* All the next fields state should stay constant. */
 145         for (i = 0; i < qp->entries_n; ++i, ++wqe) {
 146                 wqe->sq_ds = sq_ds;
 147                 wqe->flags = flags;
 148                 wqe->opaque_lkey = opaq_lkey;
 149                 wqe->opaque_vaddr = rte_cpu_to_be_64
 150                                                 ((uint64_t)(uintptr_t)&opaq[i]);
 151         }
 152 }
 153
 154 static int
 155 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 156                        uint32_t max_inflight_ops, int socket_id)
 157 {
 158         struct mlx5_compress_priv *priv = dev->data->dev_private;
 159         struct mlx5_compress_qp *qp;
 160         struct mlx5_devx_cq_attr cq_attr = {
 161                 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
 162         };
 163         struct mlx5_devx_create_sq_attr sq_attr = {
 164                 .user_index = qp_id,
 165                 .wq_attr = (struct mlx5_devx_wq_attr){
 166                         .pd = priv->pdn,
 167                         .uar_page = mlx5_os_get_devx_uar_page_id(priv->uar),
 168                 },
 169         };
 170         struct mlx5_devx_modify_sq_attr modify_attr = {
 171                 .state = MLX5_SQC_STATE_RDY,
 172         };
 173         uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
 174         uint32_t alloc_size = sizeof(*qp);
 175         void *opaq_buf;
 176         int ret;
 177
 178         alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
 179         alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
 180         qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
 181                                 socket_id);
 182         if (qp == NULL) {
 183                 DRV_LOG(ERR, "Failed to allocate qp memory.");
 184                 rte_errno = ENOMEM;
 185                 return -rte_errno;
 186         }
 187         dev->data->queue_pairs[qp_id] = qp;
 188         opaq_buf = rte_calloc(__func__, 1u << log_ops_n,
 189                               sizeof(struct mlx5_gga_compress_opaque),
 190                               sizeof(struct mlx5_gga_compress_opaque));
 191         if (opaq_buf == NULL) {
 192                 DRV_LOG(ERR, "Failed to allocate opaque memory.");
 193                 rte_errno = ENOMEM;
 194                 goto err;
 195         }
 196         if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,
 197                                priv->dev_config.socket_id)) {
 198                 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
 199                         (uint32_t)qp_id);
 200                 rte_errno = ENOMEM;
 201                 goto err;
 202         }
 203         qp->entries_n = 1 << log_ops_n;
 204         qp->socket_id = socket_id;
 205         qp->qp_id = qp_id;
 206         qp->priv = priv;
 207         qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
 208                                                    RTE_CACHE_LINE_SIZE);
 209         qp->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
 210         MLX5_ASSERT(qp->uar_addr);
 211         if (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n *
 212                                         sizeof(struct mlx5_gga_compress_opaque),
 213                                                          &qp->opaque_mr) != 0) {
 214                 rte_free(opaq_buf);
 215                 DRV_LOG(ERR, "Failed to register opaque MR.");
 216                 rte_errno = ENOMEM;
 217                 goto err;
 218         }
 219         ret = mlx5_devx_cq_create(priv->ctx, &qp->cq, log_ops_n, &cq_attr,
 220                                   socket_id);
 221         if (ret != 0) {
 222                 DRV_LOG(ERR, "Failed to create CQ.");
 223                 goto err;
 224         }
 225         sq_attr.cqn = qp->cq.cq->id;
 226         ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,
 227                                   socket_id);
 228         if (ret != 0) {
 229                 DRV_LOG(ERR, "Failed to create SQ.");
 230                 goto err;
 231         }
 232         mlx5_compress_init_sq(qp);
 233         ret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr);
 234         if (ret != 0) {
 235                 DRV_LOG(ERR, "Can't change SQ state to ready.");
 236                 goto err;
 237         }
 238         DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u\n",
 239                 (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n);
 240         return 0;
 241 err:
 242         mlx5_compress_qp_release(dev, qp_id);
 243         return -1;
 244 }
 245
 246 static int
 247 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
 248 {
 249         struct mlx5_compress_priv *priv = dev->data->dev_private;
 250
 251         rte_spinlock_lock(&priv->xform_sl);
 252         LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
 253         rte_spinlock_unlock(&priv->xform_sl);
 254         rte_free(xform);
 255         return 0;
 256 }
 257
 258 static int
 259 mlx5_compress_xform_create(struct rte_compressdev *dev,
 260                            const struct rte_comp_xform *xform,
 261                            void **private_xform)
 262 {
 263         struct mlx5_compress_priv *priv = dev->data->dev_private;
 264         struct mlx5_compress_xform *xfrm;
 265         uint32_t size;
 266
 267         if (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==
 268                                                           RTE_COMP_LEVEL_NONE) {
 269                 DRV_LOG(ERR, "Non-compressed block is not supported.");
 270                 return -ENOTSUP;
 271         }
 272         if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=
 273              RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&
 274                       xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {
 275                 DRV_LOG(ERR, "SHA is not supported.");
 276                 return -ENOTSUP;
 277         }
 278         xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
 279                                                     priv->dev_config.socket_id);
 280         if (xfrm == NULL)
 281                 return -ENOMEM;
 282         xfrm->opcode = MLX5_OPCODE_MMO;
 283         xfrm->type = xform->type;
 284         switch (xform->type) {
 285         case RTE_COMP_COMPRESS:
 286                 switch (xform->compress.algo) {
 287                 case RTE_COMP_ALGO_NULL:
 288                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 289                                                         WQE_CSEG_OPC_MOD_OFFSET;
 290                         break;
 291                 case RTE_COMP_ALGO_DEFLATE:
 292                         size = 1 << xform->compress.window_size;
 293                         size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
 294                         xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 295                                          MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 296                                            WQE_GGA_COMP_WIN_SIZE_OFFSET;
 297                         if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
 298                                 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 299                         else
 300                                 size = priv->min_block_size - 1 +
 301                                                           xform->compress.level;
 302                         xfrm->gga_ctrl1 += RTE_MIN(size,
 303                                             MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
 304                                                  WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 305                         xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
 306                                                         WQE_CSEG_OPC_MOD_OFFSET;
 307                         size = xform->compress.deflate.huffman ==
 308                                                       RTE_COMP_HUFFMAN_DYNAMIC ?
 309                                             MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
 310                                              MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
 311                         xfrm->gga_ctrl1 += size <<
 312                                                WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
 313                         break;
 314                 default:
 315                         goto err;
 316                 }
 317                 xfrm->csum_type = xform->compress.chksum;
 318                 break;
 319         case RTE_COMP_DECOMPRESS:
 320                 switch (xform->decompress.algo) {
 321                 case RTE_COMP_ALGO_NULL:
 322                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 323                                                         WQE_CSEG_OPC_MOD_OFFSET;
 324                         break;
 325                 case RTE_COMP_ALGO_DEFLATE:
 326                         xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
 327                                                         WQE_CSEG_OPC_MOD_OFFSET;
 328                         break;
 329                 default:
 330                         goto err;
 331                 }
 332                 xfrm->csum_type = xform->decompress.chksum;
 333                 break;
 334         default:
 335                 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
 336                 goto err;
 337         }
 338         DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
 339                 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
 340         xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
 341         rte_spinlock_lock(&priv->xform_sl);
 342         LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
 343         rte_spinlock_unlock(&priv->xform_sl);
 344         *private_xform = xfrm;
 345         return 0;
 346 err:
 347         rte_free(xfrm);
 348         return -ENOTSUP;
 349 }
 350
 351 static void
 352 mlx5_compress_dev_stop(struct rte_compressdev *dev)
 353 {
 354         RTE_SET_USED(dev);
 355 }
 356
 357 static int
 358 mlx5_compress_dev_start(struct rte_compressdev *dev)
 359 {
 360         RTE_SET_USED(dev);
 361         return 0;
 362 }
 363
 364 static struct rte_compressdev_ops mlx5_compress_ops = {
 365         .dev_configure          = mlx5_compress_dev_configure,
 366         .dev_start              = mlx5_compress_dev_start,
 367         .dev_stop               = mlx5_compress_dev_stop,
 368         .dev_close              = mlx5_compress_dev_close,
 369         .dev_infos_get          = mlx5_compress_dev_info_get,
 370         .stats_get              = NULL,
 371         .stats_reset            = NULL,
 372         .queue_pair_setup       = mlx5_compress_qp_setup,
 373         .queue_pair_release     = mlx5_compress_qp_release,
 374         .private_xform_create   = mlx5_compress_xform_create,
 375         .private_xform_free     = mlx5_compress_xform_free,
 376         .stream_create          = NULL,
 377         .stream_free            = NULL,
 378 };
 379
 380 static __rte_always_inline uint32_t
 381 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
 382                        volatile struct mlx5_wqe_dseg *restrict dseg,
 383                        struct rte_mbuf *restrict mbuf,
 384                        uint32_t offset, uint32_t len)
 385 {
 386         uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
 387
 388         dseg->bcount = rte_cpu_to_be_32(len);
 389         dseg->lkey = mlx5_mr_addr2mr_bh(qp->priv->pd, 0, &qp->priv->mr_scache,
 390                                         &qp->mr_ctrl, addr,
 391                                         !!(mbuf->ol_flags & EXT_ATTACHED_MBUF));
 392         dseg->pbuf = rte_cpu_to_be_64(addr);
 393         return dseg->lkey;
 394 }
 395
 396 static uint16_t
 397 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
 398                             uint16_t nb_ops)
 399 {
 400         struct mlx5_compress_qp *qp = queue_pair;
 401         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 402                                                               qp->sq.wqes, *wqe;
 403         struct mlx5_compress_xform *xform;
 404         struct rte_comp_op *op;
 405         uint16_t mask = qp->entries_n - 1;
 406         uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
 407         uint16_t idx;
 408         bool invalid;
 409
 410         if (remain < nb_ops)
 411                 nb_ops = remain;
 412         else
 413                 remain = nb_ops;
 414         if (unlikely(remain == 0))
 415                 return 0;
 416         do {
 417                 idx = qp->pi & mask;
 418                 wqe = &wqes[idx];
 419                 rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
 420                 op = *ops++;
 421                 xform = op->private_xform;
 422                 /*
 423                  * Check operation arguments and error cases:
 424                  *   - Operation type must be state-less.
 425                  *   - Compress operation flush flag must be FULL or FINAL.
 426                  *   - Source and destination buffers must be mapped internally.
 427                  */
 428                 invalid = op->op_type != RTE_COMP_OP_STATELESS ||
 429                                             (xform->type == RTE_COMP_COMPRESS &&
 430                                           op->flush_flag < RTE_COMP_FLUSH_FULL);
 431                 if (unlikely(invalid ||
 432                              (mlx5_compress_dseg_set(qp, &wqe->gather,
 433                                                      op->m_src,
 434                                                      op->src.offset,
 435                                                      op->src.length) ==
 436                                                                   UINT32_MAX) ||
 437                              (mlx5_compress_dseg_set(qp, &wqe->scatter,
 438                                                 op->m_dst,
 439                                                 op->dst.offset,
 440                                                 rte_pktmbuf_pkt_len(op->m_dst) -
 441                                                               op->dst.offset) ==
 442                                                                  UINT32_MAX))) {
 443                         op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
 444                                                        RTE_COMP_OP_STATUS_ERROR;
 445                         nb_ops -= remain;
 446                         if (unlikely(nb_ops == 0))
 447                                 return 0;
 448                         break;
 449                 }
 450                 wqe->gga_ctrl1 = xform->gga_ctrl1;
 451                 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
 452                 qp->ops[idx] = op;
 453                 qp->pi++;
 454         } while (--remain);
 455         rte_io_wmb();
 456         qp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
 457         rte_wmb();
 458         *qp->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/
 459         rte_wmb();
 460         return nb_ops;
 461 }
 462
 463 static void
 464 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
 465                              volatile uint32_t *opaq)
 466 {
 467         size_t i;
 468
 469         DRV_LOG(ERR, "Error cqe:");
 470         for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
 471                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 472                         cqe[i + 2], cqe[i + 3]);
 473         DRV_LOG(ERR, "\nError wqe:");
 474         for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
 475                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 476                         wqe[i + 2], wqe[i + 3]);
 477         DRV_LOG(ERR, "\nError opaq:");
 478         for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
 479                 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
 480                         opaq[i + 2], opaq[i + 3]);
 481 }
 482
 483 static void
 484 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
 485                              struct rte_comp_op *op)
 486 {
 487         const uint32_t idx = qp->ci & (qp->entries_n - 1);
 488         volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
 489                                                               &qp->cq.cqes[idx];
 490         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 491                                                                     qp->sq.wqes;
 492         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 493
 494         op->status = RTE_COMP_OP_STATUS_ERROR;
 495         op->consumed = 0;
 496         op->produced = 0;
 497         op->output_chksum = 0;
 498         op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
 499                               ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
 500         mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
 501                                  (volatile uint32_t *)&wqes[idx],
 502                                  (volatile uint32_t *)&opaq[idx]);
 503 }
 504
 505 static uint16_t
 506 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
 507                             uint16_t nb_ops)
 508 {
 509         struct mlx5_compress_qp *qp = queue_pair;
 510         volatile struct mlx5_compress_xform *restrict xform;
 511         volatile struct mlx5_cqe *restrict cqe;
 512         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 513         struct rte_comp_op *restrict op;
 514         const unsigned int cq_size = qp->entries_n;
 515         const unsigned int mask = cq_size - 1;
 516         uint32_t idx;
 517         uint32_t next_idx = qp->ci & mask;
 518         const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
 519         uint16_t i = 0;
 520         int ret;
 521
 522         if (unlikely(max == 0))
 523                 return 0;
 524         do {
 525                 idx = next_idx;
 526                 next_idx = (qp->ci + 1) & mask;
 527                 rte_prefetch0(&qp->cq.cqes[next_idx]);
 528                 rte_prefetch0(qp->ops[next_idx]);
 529                 op = qp->ops[idx];
 530                 cqe = &qp->cq.cqes[idx];
 531                 ret = check_cqe(cqe, cq_size, qp->ci);
 532                 /*
 533                  * Be sure owner read is done before any other cookie field or
 534                  * opaque field.
 535                  */
 536                 rte_io_rmb();
 537                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 538                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 539                                 break;
 540                         mlx5_compress_cqe_err_handle(qp, op);
 541                 } else {
 542                         xform = op->private_xform;
 543                         op->status = RTE_COMP_OP_STATUS_SUCCESS;
 544                         op->consumed = op->src.length;
 545                         op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
 546                         MLX5_ASSERT(cqe->byte_cnt ==
 547                                     qp->opaque_buf[idx].scattered_length);
 548                         switch (xform->csum_type) {
 549                         case RTE_COMP_CHECKSUM_CRC32:
 550                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 551                                                     (opaq[idx].crc32);
 552                                 break;
 553                         case RTE_COMP_CHECKSUM_ADLER32:
 554                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 555                                             (opaq[idx].adler32) << 32;
 556                                 break;
 557                         case RTE_COMP_CHECKSUM_CRC32_ADLER32:
 558                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 559                                                              (opaq[idx].crc32) |
 560                                                      ((uint64_t)rte_be_to_cpu_32
 561                                                      (opaq[idx].adler32) << 32);
 562                                 break;
 563                         default:
 564                                 break;
 565                         }
 566                 }
 567                 ops[i++] = op;
 568                 qp->ci++;
 569         } while (i < max);
 570         if (likely(i != 0)) {
 571                 rte_io_wmb();
 572                 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
 573         }
 574         return i;
 575 }
 576
 577 static struct ibv_device *
 578 mlx5_compress_get_ib_device_match(struct rte_pci_addr *addr)
 579 {
 580         int n;
 581         struct ibv_device **ibv_list = mlx5_glue->get_device_list(&n);
 582         struct ibv_device *ibv_match = NULL;
 583
 584         if (ibv_list == NULL) {
 585                 rte_errno = ENOSYS;
 586                 return NULL;
 587         }
 588         while (n-- > 0) {
 589                 struct rte_pci_addr paddr;
 590
 591                 DRV_LOG(DEBUG, "Checking device \"%s\"..", ibv_list[n]->name);
 592                 if (mlx5_dev_to_pci_addr(ibv_list[n]->ibdev_path, &paddr) != 0)
 593                         continue;
 594                 if (rte_pci_addr_cmp(addr, &paddr) != 0)
 595                         continue;
 596                 ibv_match = ibv_list[n];
 597                 break;
 598         }
 599         if (ibv_match == NULL)
 600                 rte_errno = ENOENT;
 601         mlx5_glue->free_device_list(ibv_list);
 602         return ibv_match;
 603 }
 604
 605 static void
 606 mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv)
 607 {
 608         if (priv->pd != NULL) {
 609                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 610                 priv->pd = NULL;
 611         }
 612         if (priv->uar != NULL) {
 613                 mlx5_glue->devx_free_uar(priv->uar);
 614                 priv->uar = NULL;
 615         }
 616 }
 617
 618 static int
 619 mlx5_compress_pd_create(struct mlx5_compress_priv *priv)
 620 {
 621 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 622         struct mlx5dv_obj obj;
 623         struct mlx5dv_pd pd_info;
 624         int ret;
 625
 626         priv->pd = mlx5_glue->alloc_pd(priv->ctx);
 627         if (priv->pd == NULL) {
 628                 DRV_LOG(ERR, "Failed to allocate PD.");
 629                 return errno ? -errno : -ENOMEM;
 630         }
 631         obj.pd.in = priv->pd;
 632         obj.pd.out = &pd_info;
 633         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 634         if (ret != 0) {
 635                 DRV_LOG(ERR, "Fail to get PD object info.");
 636                 mlx5_glue->dealloc_pd(priv->pd);
 637                 priv->pd = NULL;
 638                 return -errno;
 639         }
 640         priv->pdn = pd_info.pdn;
 641         return 0;
 642 #else
 643         (void)priv;
 644         DRV_LOG(ERR, "Cannot get pdn - no DV support.");
 645         return -ENOTSUP;
 646 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 647 }
 648
 649 static int
 650 mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv)
 651 {
 652         if (mlx5_compress_pd_create(priv) != 0)
 653                 return -1;
 654         priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
 655         if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
 656             NULL) {
 657                 rte_errno = errno;
 658                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 659                 DRV_LOG(ERR, "Failed to allocate UAR.");
 660                 return -1;
 661         }
 662         return 0;
 663 }
 664
 665 /**
 666  * DPDK callback to register a PCI device.
 667  *
 668  * This function spawns compress device out of a given PCI device.
 669  *
 670  * @param[in] pci_drv
 671  *   PCI driver structure (mlx5_compress_driver).
 672  * @param[in] pci_dev
 673  *   PCI device information.
 674  *
 675  * @return
 676  *   0 on success, 1 to skip this driver, a negative errno value otherwise
 677  *   and rte_errno is set.
 678  */
 679 static int
 680 mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv,
 681                         struct rte_pci_device *pci_dev)
 682 {
 683         struct ibv_device *ibv;
 684         struct rte_compressdev *cdev;
 685         struct ibv_context *ctx;
 686         struct mlx5_compress_priv *priv;
 687         struct mlx5_hca_attr att = { 0 };
 688         struct rte_compressdev_pmd_init_params init_params = {
 689                 .name = "",
 690                 .socket_id = pci_dev->device.numa_node,
 691         };
 692
 693         RTE_SET_USED(pci_drv);
 694         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 695                 DRV_LOG(ERR, "Non-primary process type is not supported.");
 696                 rte_errno = ENOTSUP;
 697                 return -rte_errno;
 698         }
 699         ibv = mlx5_compress_get_ib_device_match(&pci_dev->addr);
 700         if (ibv == NULL) {
 701                 DRV_LOG(ERR, "No matching IB device for PCI slot "
 702                         PCI_PRI_FMT ".", pci_dev->addr.domain,
 703                         pci_dev->addr.bus, pci_dev->addr.devid,
 704                         pci_dev->addr.function);
 705                 return -rte_errno;
 706         }
 707         DRV_LOG(INFO, "PCI information matches for device \"%s\".", ibv->name);
 708         ctx = mlx5_glue->dv_open_device(ibv);
 709         if (ctx == NULL) {
 710                 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name);
 711                 rte_errno = ENODEV;
 712                 return -rte_errno;
 713         }
 714         if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 ||
 715             att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 ||
 716             att.mmo_dma_en == 0) {
 717                 DRV_LOG(ERR, "Not enough capabilities to support compress "
 718                         "operations, maybe old FW/OFED version?");
 719                 claim_zero(mlx5_glue->close_device(ctx));
 720                 rte_errno = ENOTSUP;
 721                 return -ENOTSUP;
 722         }
 723         cdev = rte_compressdev_pmd_create(ibv->name, &pci_dev->device,
 724                                           sizeof(*priv), &init_params);
 725         if (cdev == NULL) {
 726                 DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name);
 727                 claim_zero(mlx5_glue->close_device(ctx));
 728                 return -ENODEV;
 729         }
 730         DRV_LOG(INFO,
 731                 "Compress device %s was created successfully.", ibv->name);
 732         cdev->dev_ops = &mlx5_compress_ops;
 733         cdev->dequeue_burst = mlx5_compress_dequeue_burst;
 734         cdev->enqueue_burst = mlx5_compress_enqueue_burst;
 735         cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 736         priv = cdev->data->dev_private;
 737         priv->ctx = ctx;
 738         priv->pci_dev = pci_dev;
 739         priv->cdev = cdev;
 740         priv->min_block_size = att.compress_min_block_size;
 741         if (mlx5_compress_hw_global_prepare(priv) != 0) {
 742                 rte_compressdev_pmd_destroy(priv->cdev);
 743                 claim_zero(mlx5_glue->close_device(priv->ctx));
 744                 return -1;
 745         }
 746         if (mlx5_mr_btree_init(&priv->mr_scache.cache,
 747                              MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {
 748                 DRV_LOG(ERR, "Failed to allocate shared cache MR memory.");
 749                 mlx5_compress_hw_global_release(priv);
 750                 rte_compressdev_pmd_destroy(priv->cdev);
 751                 claim_zero(mlx5_glue->close_device(priv->ctx));
 752                 rte_errno = ENOMEM;
 753                 return -rte_errno;
 754         }
 755         priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;
 756         priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;
 757         pthread_mutex_lock(&priv_list_lock);
 758         TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
 759         pthread_mutex_unlock(&priv_list_lock);
 760         return 0;
 761 }
 762
 763 /**
 764  * DPDK callback to remove a PCI device.
 765  *
 766  * This function removes all compress devices belong to a given PCI device.
 767  *
 768  * @param[in] pci_dev
 769  *   Pointer to the PCI device.
 770  *
 771  * @return
 772  *   0 on success, the function cannot fail.
 773  */
 774 static int
 775 mlx5_compress_pci_remove(struct rte_pci_device *pdev)
 776 {
 777         struct mlx5_compress_priv *priv = NULL;
 778
 779         pthread_mutex_lock(&priv_list_lock);
 780         TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 781                 if (rte_pci_addr_cmp(&priv->pci_dev->addr, &pdev->addr) != 0)
 782                         break;
 783         if (priv)
 784                 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
 785         pthread_mutex_unlock(&priv_list_lock);
 786         if (priv) {
 787                 mlx5_mr_release_cache(&priv->mr_scache);
 788                 mlx5_compress_hw_global_release(priv);
 789                 rte_compressdev_pmd_destroy(priv->cdev);
 790                 claim_zero(mlx5_glue->close_device(priv->ctx));
 791         }
 792         return 0;
 793 }
 794
 795 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
 796         {
 797                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 798                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
 799         },
 800         {
 801                 .vendor_id = 0
 802         }
 803 };
 804
 805 static struct mlx5_pci_driver mlx5_compress_driver = {
 806         .driver_class = MLX5_CLASS_COMPRESS,
 807         .pci_driver = {
 808                 .driver = {
 809                         .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
 810                 },
 811                 .id_table = mlx5_compress_pci_id_map,
 812                 .probe = mlx5_compress_pci_probe,
 813                 .remove = mlx5_compress_pci_remove,
 814                 .drv_flags = 0,
 815         },
 816 };
 817
 818 RTE_INIT(rte_mlx5_compress_init)
 819 {
 820         mlx5_common_init();
 821         if (mlx5_glue != NULL)
 822                 mlx5_pci_driver_register(&mlx5_compress_driver);
 823 }
 824
 825 RTE_LOG_REGISTER(mlx5_compress_logtype, MLX5_COMPRESS_LOG_NAME, NOTICE)
 826 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
 827 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
 828 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");