1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2021 Mellanox Technologies, Ltd
5 #include <rte_malloc.h>
8 #include <rte_bus_pci.h>
9 #include <rte_spinlock.h>
11 #include <rte_compressdev.h>
12 #include <rte_compressdev_pmd.h>
14 #include <mlx5_glue.h>
15 #include <mlx5_common.h>
16 #include <mlx5_devx_cmds.h>
17 #include <mlx5_common_os.h>
18 #include <mlx5_common_devx.h>
19 #include <mlx5_common_mr.h>
22 #include "mlx5_compress_utils.h"
24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
25 #define MLX5_COMPRESS_MAX_QPS 1024
26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
28 struct mlx5_compress_xform {
29 LIST_ENTRY(mlx5_compress_xform) next;
30 enum rte_comp_xform_type type;
31 enum rte_comp_checksum_type csum_type;
33 uint32_t gga_ctrl1; /* BE. */
36 struct mlx5_compress_priv {
37 TAILQ_ENTRY(mlx5_compress_priv) next;
38 struct ibv_context *ctx; /* Device context. */
39 struct rte_compressdev *cdev;
41 uint32_t pdn; /* Protection Domain number. */
42 uint8_t min_block_size;
43 uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */
44 /* Minimum huffman block size supported by the device. */
46 struct rte_compressdev_config dev_config;
47 LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
48 rte_spinlock_t xform_sl;
49 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
50 volatile uint64_t *uar_addr;
52 rte_spinlock_t uar32_sl;
53 #endif /* RTE_ARCH_64 */
56 struct mlx5_compress_qp {
61 struct mlx5_mr_ctrl mr_ctrl;
63 struct mlx5_devx_cq cq;
64 struct mlx5_devx_sq sq;
65 struct mlx5_pmd_mr opaque_mr;
66 struct rte_comp_op **ops;
67 struct mlx5_compress_priv *priv;
68 struct rte_compressdev_stats stats;
71 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
72 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
73 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
75 int mlx5_compress_logtype;
77 static const struct rte_compressdev_capabilities mlx5_caps[] = {
79 .algo = RTE_COMP_ALGO_NULL,
80 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
81 RTE_COMP_FF_CRC32_CHECKSUM |
82 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
83 RTE_COMP_FF_SHAREABLE_PRIV_XFORM,
86 .algo = RTE_COMP_ALGO_DEFLATE,
87 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
88 RTE_COMP_FF_CRC32_CHECKSUM |
89 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
90 RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
91 RTE_COMP_FF_HUFFMAN_FIXED |
92 RTE_COMP_FF_HUFFMAN_DYNAMIC,
93 .window_size = {.min = 10, .max = 15, .increment = 1},
96 .algo = RTE_COMP_ALGO_LIST_END,
101 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
102 struct rte_compressdev_info *info)
106 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
107 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
108 info->capabilities = mlx5_caps;
113 mlx5_compress_dev_configure(struct rte_compressdev *dev,
114 struct rte_compressdev_config *config)
116 struct mlx5_compress_priv *priv;
118 if (dev == NULL || config == NULL)
120 priv = dev->data->dev_private;
121 priv->dev_config = *config;
126 mlx5_compress_dev_close(struct rte_compressdev *dev)
133 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
135 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
137 if (qp->sq.sq != NULL)
138 mlx5_devx_sq_destroy(&qp->sq);
139 if (qp->cq.cq != NULL)
140 mlx5_devx_cq_destroy(&qp->cq);
141 if (qp->opaque_mr.obj != NULL) {
142 void *opaq = qp->opaque_mr.addr;
144 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
148 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
150 dev->data->queue_pairs[qp_id] = NULL;
155 mlx5_compress_init_sq(struct mlx5_compress_qp *qp)
157 volatile struct mlx5_gga_wqe *restrict wqe =
158 (volatile struct mlx5_gga_wqe *)qp->sq.wqes;
159 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
160 const uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u);
161 const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
162 MLX5_COMP_MODE_OFFSET);
163 const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
166 /* All the next fields state should stay constant. */
167 for (i = 0; i < qp->entries_n; ++i, ++wqe) {
170 wqe->opaque_lkey = opaq_lkey;
171 wqe->opaque_vaddr = rte_cpu_to_be_64
172 ((uint64_t)(uintptr_t)&opaq[i]);
177 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
178 uint32_t max_inflight_ops, int socket_id)
180 struct mlx5_compress_priv *priv = dev->data->dev_private;
181 struct mlx5_compress_qp *qp;
182 struct mlx5_devx_cq_attr cq_attr = {
183 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
185 struct mlx5_devx_create_sq_attr sq_attr = {
187 .wq_attr = (struct mlx5_devx_wq_attr){
189 .uar_page = mlx5_os_get_devx_uar_page_id(priv->uar),
192 struct mlx5_devx_modify_sq_attr modify_attr = {
193 .state = MLX5_SQC_STATE_RDY,
195 uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
196 uint32_t alloc_size = sizeof(*qp);
200 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
201 alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
202 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
205 DRV_LOG(ERR, "Failed to allocate qp memory.");
209 dev->data->queue_pairs[qp_id] = qp;
210 if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,
211 priv->dev_config.socket_id)) {
212 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
217 opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n,
218 sizeof(struct mlx5_gga_compress_opaque),
219 sizeof(struct mlx5_gga_compress_opaque));
220 if (opaq_buf == NULL) {
221 DRV_LOG(ERR, "Failed to allocate opaque memory.");
225 qp->entries_n = 1 << log_ops_n;
226 qp->socket_id = socket_id;
229 qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
230 RTE_CACHE_LINE_SIZE);
231 if (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n *
232 sizeof(struct mlx5_gga_compress_opaque),
233 &qp->opaque_mr) != 0) {
235 DRV_LOG(ERR, "Failed to register opaque MR.");
239 ret = mlx5_devx_cq_create(priv->ctx, &qp->cq, log_ops_n, &cq_attr,
242 DRV_LOG(ERR, "Failed to create CQ.");
245 sq_attr.cqn = qp->cq.cq->id;
246 sq_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format);
247 ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,
250 DRV_LOG(ERR, "Failed to create SQ.");
253 mlx5_compress_init_sq(qp);
254 ret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr);
256 DRV_LOG(ERR, "Can't change SQ state to ready.");
259 /* Save pointer of global generation number to check memory event. */
260 qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;
261 DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u",
262 (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n);
265 mlx5_compress_qp_release(dev, qp_id);
270 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
272 struct mlx5_compress_priv *priv = dev->data->dev_private;
274 rte_spinlock_lock(&priv->xform_sl);
275 LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
276 rte_spinlock_unlock(&priv->xform_sl);
282 mlx5_compress_xform_create(struct rte_compressdev *dev,
283 const struct rte_comp_xform *xform,
284 void **private_xform)
286 struct mlx5_compress_priv *priv = dev->data->dev_private;
287 struct mlx5_compress_xform *xfrm;
290 if (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==
291 RTE_COMP_LEVEL_NONE) {
292 DRV_LOG(ERR, "Non-compressed block is not supported.");
295 if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=
296 RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&
297 xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {
298 DRV_LOG(ERR, "SHA is not supported.");
301 xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
302 priv->dev_config.socket_id);
305 xfrm->opcode = MLX5_OPCODE_MMO;
306 xfrm->type = xform->type;
307 switch (xform->type) {
308 case RTE_COMP_COMPRESS:
309 switch (xform->compress.algo) {
310 case RTE_COMP_ALGO_NULL:
311 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
312 WQE_CSEG_OPC_MOD_OFFSET;
314 case RTE_COMP_ALGO_DEFLATE:
315 size = 1 << xform->compress.window_size;
316 size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
317 xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
318 MLX5_COMP_MAX_WIN_SIZE_CONF) <<
319 WQE_GGA_COMP_WIN_SIZE_OFFSET;
320 switch (xform->compress.level) {
321 case RTE_COMP_LEVEL_PMD_DEFAULT:
322 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
324 case RTE_COMP_LEVEL_MAX:
325 size = priv->min_block_size;
328 size = RTE_MAX(MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX
329 + 1 - xform->compress.level,
330 priv->min_block_size);
332 xfrm->gga_ctrl1 += RTE_MIN(size,
333 MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
334 WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
335 xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
336 WQE_CSEG_OPC_MOD_OFFSET;
337 size = xform->compress.deflate.huffman ==
338 RTE_COMP_HUFFMAN_DYNAMIC ?
339 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
340 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
341 xfrm->gga_ctrl1 += size <<
342 WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
347 xfrm->csum_type = xform->compress.chksum;
349 case RTE_COMP_DECOMPRESS:
350 switch (xform->decompress.algo) {
351 case RTE_COMP_ALGO_NULL:
352 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
353 WQE_CSEG_OPC_MOD_OFFSET;
355 case RTE_COMP_ALGO_DEFLATE:
356 xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
357 WQE_CSEG_OPC_MOD_OFFSET;
362 xfrm->csum_type = xform->decompress.chksum;
365 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
368 DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
369 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
370 xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
371 rte_spinlock_lock(&priv->xform_sl);
372 LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
373 rte_spinlock_unlock(&priv->xform_sl);
374 *private_xform = xfrm;
382 mlx5_compress_dev_stop(struct rte_compressdev *dev)
388 mlx5_compress_dev_start(struct rte_compressdev *dev)
395 mlx5_compress_stats_get(struct rte_compressdev *dev,
396 struct rte_compressdev_stats *stats)
400 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
401 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
403 stats->enqueued_count += qp->stats.enqueued_count;
404 stats->dequeued_count += qp->stats.dequeued_count;
405 stats->enqueue_err_count += qp->stats.enqueue_err_count;
406 stats->dequeue_err_count += qp->stats.dequeue_err_count;
411 mlx5_compress_stats_reset(struct rte_compressdev *dev)
415 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
416 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
418 memset(&qp->stats, 0, sizeof(qp->stats));
422 static struct rte_compressdev_ops mlx5_compress_ops = {
423 .dev_configure = mlx5_compress_dev_configure,
424 .dev_start = mlx5_compress_dev_start,
425 .dev_stop = mlx5_compress_dev_stop,
426 .dev_close = mlx5_compress_dev_close,
427 .dev_infos_get = mlx5_compress_dev_info_get,
428 .stats_get = mlx5_compress_stats_get,
429 .stats_reset = mlx5_compress_stats_reset,
430 .queue_pair_setup = mlx5_compress_qp_setup,
431 .queue_pair_release = mlx5_compress_qp_release,
432 .private_xform_create = mlx5_compress_xform_create,
433 .private_xform_free = mlx5_compress_xform_free,
434 .stream_create = NULL,
439 * Query LKey from a packet buffer for QP. If not found, add the mempool.
442 * Pointer to the priv object.
446 * Pointer to per-queue MR control structure.
448 * Mbuf offload features.
451 * Searched LKey on success, UINT32_MAX on no match.
453 static __rte_always_inline uint32_t
454 mlx5_compress_addr2mr(struct mlx5_compress_priv *priv, uintptr_t addr,
455 struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags)
459 /* Check generation bit to see if there's any change on existing MRs. */
460 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
461 mlx5_mr_flush_local_cache(mr_ctrl);
462 /* Linear search on MR cache array. */
463 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
464 MLX5_MR_CACHE_N, addr);
465 if (likely(lkey != UINT32_MAX))
467 /* Take slower bottom-half on miss. */
468 return mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr,
469 !!(ol_flags & EXT_ATTACHED_MBUF));
472 static __rte_always_inline uint32_t
473 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
474 volatile struct mlx5_wqe_dseg *restrict dseg,
475 struct rte_mbuf *restrict mbuf,
476 uint32_t offset, uint32_t len)
478 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
480 dseg->bcount = rte_cpu_to_be_32(len);
481 dseg->lkey = mlx5_compress_addr2mr(qp->priv, addr, &qp->mr_ctrl,
483 dseg->pbuf = rte_cpu_to_be_64(addr);
488 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
489 * 64bit architectures.
491 static __rte_always_inline void
492 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv)
495 *priv->uar_addr = val;
496 #else /* !RTE_ARCH_64 */
497 rte_spinlock_lock(&priv->uar32_sl);
498 *(volatile uint32_t *)priv->uar_addr = val;
500 *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32;
501 rte_spinlock_unlock(&priv->uar32_sl);
506 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
509 struct mlx5_compress_qp *qp = queue_pair;
510 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
512 struct mlx5_compress_xform *xform;
513 struct rte_comp_op *op;
514 uint16_t mask = qp->entries_n - 1;
515 uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
523 if (unlikely(remain == 0))
528 rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
530 xform = op->private_xform;
532 * Check operation arguments and error cases:
533 * - Operation type must be state-less.
534 * - Compress operation flush flag must be FULL or FINAL.
535 * - Source and destination buffers must be mapped internally.
537 invalid = op->op_type != RTE_COMP_OP_STATELESS ||
538 (xform->type == RTE_COMP_COMPRESS &&
539 op->flush_flag < RTE_COMP_FLUSH_FULL);
540 if (unlikely(invalid ||
541 (mlx5_compress_dseg_set(qp, &wqe->gather,
546 (mlx5_compress_dseg_set(qp, &wqe->scatter,
549 rte_pktmbuf_pkt_len(op->m_dst) -
552 op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
553 RTE_COMP_OP_STATUS_ERROR;
555 if (unlikely(nb_ops == 0))
559 wqe->gga_ctrl1 = xform->gga_ctrl1;
560 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
564 qp->stats.enqueued_count += nb_ops;
566 qp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
568 mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv);
574 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
575 volatile uint32_t *opaq)
579 DRV_LOG(ERR, "Error cqe:");
580 for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
581 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
582 cqe[i + 2], cqe[i + 3]);
583 DRV_LOG(ERR, "\nError wqe:");
584 for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
585 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
586 wqe[i + 2], wqe[i + 3]);
587 DRV_LOG(ERR, "\nError opaq:");
588 for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
589 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
590 opaq[i + 2], opaq[i + 3]);
594 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
595 struct rte_comp_op *op)
597 const uint32_t idx = qp->ci & (qp->entries_n - 1);
598 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
600 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
602 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
604 op->status = RTE_COMP_OP_STATUS_ERROR;
607 op->output_chksum = 0;
608 op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
609 ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
610 mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
611 (volatile uint32_t *)&wqes[idx],
612 (volatile uint32_t *)&opaq[idx]);
613 qp->stats.dequeue_err_count++;
617 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
620 struct mlx5_compress_qp *qp = queue_pair;
621 volatile struct mlx5_compress_xform *restrict xform;
622 volatile struct mlx5_cqe *restrict cqe;
623 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
624 struct rte_comp_op *restrict op;
625 const unsigned int cq_size = qp->entries_n;
626 const unsigned int mask = cq_size - 1;
628 uint32_t next_idx = qp->ci & mask;
629 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
633 if (unlikely(max == 0))
637 next_idx = (qp->ci + 1) & mask;
638 rte_prefetch0(&qp->cq.cqes[next_idx]);
639 rte_prefetch0(qp->ops[next_idx]);
641 cqe = &qp->cq.cqes[idx];
642 ret = check_cqe(cqe, cq_size, qp->ci);
644 * Be sure owner read is done before any other cookie field or
648 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
649 if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
651 mlx5_compress_cqe_err_handle(qp, op);
653 xform = op->private_xform;
654 op->status = RTE_COMP_OP_STATUS_SUCCESS;
655 op->consumed = op->src.length;
656 op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
657 MLX5_ASSERT(cqe->byte_cnt ==
658 opaq[idx].scattered_length);
659 switch (xform->csum_type) {
660 case RTE_COMP_CHECKSUM_CRC32:
661 op->output_chksum = (uint64_t)rte_be_to_cpu_32
664 case RTE_COMP_CHECKSUM_ADLER32:
665 op->output_chksum = (uint64_t)rte_be_to_cpu_32
666 (opaq[idx].adler32) << 32;
668 case RTE_COMP_CHECKSUM_CRC32_ADLER32:
669 op->output_chksum = (uint64_t)rte_be_to_cpu_32
671 ((uint64_t)rte_be_to_cpu_32
672 (opaq[idx].adler32) << 32);
681 if (likely(i != 0)) {
683 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
684 qp->stats.dequeued_count += i;
690 mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv)
692 if (priv->pd != NULL) {
693 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
696 if (priv->uar != NULL) {
697 mlx5_glue->devx_free_uar(priv->uar);
703 mlx5_compress_pd_create(struct mlx5_compress_priv *priv)
705 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
706 struct mlx5dv_obj obj;
707 struct mlx5dv_pd pd_info;
710 priv->pd = mlx5_glue->alloc_pd(priv->ctx);
711 if (priv->pd == NULL) {
712 DRV_LOG(ERR, "Failed to allocate PD.");
713 return errno ? -errno : -ENOMEM;
715 obj.pd.in = priv->pd;
716 obj.pd.out = &pd_info;
717 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
719 DRV_LOG(ERR, "Fail to get PD object info.");
720 mlx5_glue->dealloc_pd(priv->pd);
724 priv->pdn = pd_info.pdn;
728 DRV_LOG(ERR, "Cannot get pdn - no DV support.");
730 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
734 mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv)
736 if (mlx5_compress_pd_create(priv) != 0)
738 priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
739 if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
742 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
743 DRV_LOG(ERR, "Failed to allocate UAR.");
746 priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
747 MLX5_ASSERT(priv->uar_addr);
749 rte_spinlock_init(&priv->uar32_sl);
750 #endif /* RTE_ARCH_64 */
755 * Callback for memory event.
765 mlx5_compress_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,
766 size_t len, void *arg __rte_unused)
768 struct mlx5_compress_priv *priv;
770 /* Must be called from the primary process. */
771 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
772 switch (event_type) {
773 case RTE_MEM_EVENT_FREE:
774 pthread_mutex_lock(&priv_list_lock);
775 /* Iterate all the existing mlx5 devices. */
776 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
777 mlx5_free_mr_by_addr(&priv->mr_scache,
778 priv->ctx->device->name,
780 pthread_mutex_unlock(&priv_list_lock);
782 case RTE_MEM_EVENT_ALLOC:
789 mlx5_compress_dev_probe(struct rte_device *dev)
791 struct ibv_device *ibv;
792 struct rte_compressdev *cdev;
793 struct ibv_context *ctx;
794 struct mlx5_compress_priv *priv;
795 struct mlx5_hca_attr att = { 0 };
796 struct rte_compressdev_pmd_init_params init_params = {
798 .socket_id = dev->numa_node,
801 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
802 DRV_LOG(ERR, "Non-primary process type is not supported.");
806 ibv = mlx5_os_get_ibv_dev(dev);
809 ctx = mlx5_glue->dv_open_device(ibv);
811 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name);
815 if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 ||
816 att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 ||
817 att.mmo_dma_en == 0) {
818 DRV_LOG(ERR, "Not enough capabilities to support compress "
819 "operations, maybe old FW/OFED version?");
820 claim_zero(mlx5_glue->close_device(ctx));
824 cdev = rte_compressdev_pmd_create(ibv->name, dev,
825 sizeof(*priv), &init_params);
827 DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name);
828 claim_zero(mlx5_glue->close_device(ctx));
832 "Compress device %s was created successfully.", ibv->name);
833 cdev->dev_ops = &mlx5_compress_ops;
834 cdev->dequeue_burst = mlx5_compress_dequeue_burst;
835 cdev->enqueue_burst = mlx5_compress_enqueue_burst;
836 cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
837 priv = cdev->data->dev_private;
840 priv->min_block_size = att.compress_min_block_size;
841 priv->sq_ts_format = att.sq_ts_format;
842 if (mlx5_compress_hw_global_prepare(priv) != 0) {
843 rte_compressdev_pmd_destroy(priv->cdev);
844 claim_zero(mlx5_glue->close_device(priv->ctx));
847 if (mlx5_mr_btree_init(&priv->mr_scache.cache,
848 MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {
849 DRV_LOG(ERR, "Failed to allocate shared cache MR memory.");
850 mlx5_compress_hw_global_release(priv);
851 rte_compressdev_pmd_destroy(priv->cdev);
852 claim_zero(mlx5_glue->close_device(priv->ctx));
856 priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;
857 priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;
858 /* Register callback function for global shared MR cache management. */
859 if (TAILQ_EMPTY(&mlx5_compress_priv_list))
860 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
861 mlx5_compress_mr_mem_event_cb,
863 pthread_mutex_lock(&priv_list_lock);
864 TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
865 pthread_mutex_unlock(&priv_list_lock);
870 mlx5_compress_dev_remove(struct rte_device *dev)
872 struct mlx5_compress_priv *priv = NULL;
874 pthread_mutex_lock(&priv_list_lock);
875 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
876 if (priv->cdev->device == dev)
879 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
880 pthread_mutex_unlock(&priv_list_lock);
882 if (TAILQ_EMPTY(&mlx5_compress_priv_list))
883 rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB",
885 mlx5_mr_release_cache(&priv->mr_scache);
886 mlx5_compress_hw_global_release(priv);
887 rte_compressdev_pmd_destroy(priv->cdev);
888 claim_zero(mlx5_glue->close_device(priv->ctx));
893 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
895 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
896 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
903 static struct mlx5_class_driver mlx5_compress_driver = {
904 .drv_class = MLX5_CLASS_COMPRESS,
905 .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
906 .id_table = mlx5_compress_pci_id_map,
907 .probe = mlx5_compress_dev_probe,
908 .remove = mlx5_compress_dev_remove,
911 RTE_INIT(rte_mlx5_compress_init)
914 if (mlx5_glue != NULL)
915 mlx5_class_driver_register(&mlx5_compress_driver);
918 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE)
919 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
920 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
921 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");