drivers/compress/mlx5/mlx5_compress.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_log.h>
   7 #include <rte_errno.h>
   8 #include <rte_pci.h>
   9 #include <rte_spinlock.h>
  10 #include <rte_comp.h>
  11 #include <rte_compressdev.h>
  12 #include <rte_compressdev_pmd.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_common.h>
  16 #include <mlx5_common_pci.h>
  17 #include <mlx5_devx_cmds.h>
  18 #include <mlx5_common_os.h>
  19 #include <mlx5_common_devx.h>
  20 #include <mlx5_common_mr.h>
  21 #include <mlx5_prm.h>
  22
  23 #include "mlx5_compress_utils.h"
  24
  25 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
  26 #define MLX5_COMPRESS_LOG_NAME    pmd.compress.mlx5
  27 #define MLX5_COMPRESS_MAX_QPS 1024
  28 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
  29
  30 struct mlx5_compress_xform {
  31         LIST_ENTRY(mlx5_compress_xform) next;
  32         enum rte_comp_xform_type type;
  33         enum rte_comp_checksum_type csum_type;
  34         uint32_t opcode;
  35         uint32_t gga_ctrl1; /* BE. */
  36 };
  37
  38 struct mlx5_compress_priv {
  39         TAILQ_ENTRY(mlx5_compress_priv) next;
  40         struct ibv_context *ctx; /* Device context. */
  41         struct rte_pci_device *pci_dev;
  42         struct rte_compressdev *cdev;
  43         void *uar;
  44         uint32_t pdn; /* Protection Domain number. */
  45         uint8_t min_block_size;
  46         /* Minimum huffman block size supported by the device. */
  47         struct ibv_pd *pd;
  48         struct rte_compressdev_config dev_config;
  49         LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
  50         rte_spinlock_t xform_sl;
  51 };
  52
  53 struct mlx5_compress_qp {
  54         uint16_t qp_id;
  55         uint16_t entries_n;
  56         uint16_t pi;
  57         uint16_t ci;
  58         volatile uint64_t *uar_addr;
  59         int socket_id;
  60         struct mlx5_devx_cq cq;
  61         struct mlx5_devx_sq sq;
  62         struct mlx5_pmd_mr opaque_mr;
  63         struct rte_comp_op **ops;
  64         struct mlx5_compress_priv *priv;
  65 };
  66
  67 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
  68                                 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
  69 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
  70
  71 int mlx5_compress_logtype;
  72
  73 const struct rte_compressdev_capabilities mlx5_caps[RTE_COMP_ALGO_LIST_END];
  74
  75
  76 static void
  77 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
  78                            struct rte_compressdev_info *info)
  79 {
  80         RTE_SET_USED(dev);
  81         if (info != NULL) {
  82                 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
  83                 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
  84                 info->capabilities = mlx5_caps;
  85         }
  86 }
  87
  88 static int
  89 mlx5_compress_dev_configure(struct rte_compressdev *dev,
  90                             struct rte_compressdev_config *config)
  91 {
  92         struct mlx5_compress_priv *priv;
  93
  94         if (dev == NULL || config == NULL)
  95                 return -EINVAL;
  96         priv = dev->data->dev_private;
  97         priv->dev_config = *config;
  98         return 0;
  99 }
 100
 101 static int
 102 mlx5_compress_dev_close(struct rte_compressdev *dev)
 103 {
 104         RTE_SET_USED(dev);
 105         return 0;
 106 }
 107
 108 static int
 109 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
 110 {
 111         struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 112
 113         if (qp->sq.sq != NULL)
 114                 mlx5_devx_sq_destroy(&qp->sq);
 115         if (qp->cq.cq != NULL)
 116                 mlx5_devx_cq_destroy(&qp->cq);
 117         if (qp->opaque_mr.obj != NULL) {
 118                 void *opaq = qp->opaque_mr.addr;
 119
 120                 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
 121                 if (opaq != NULL)
 122                         rte_free(opaq);
 123         }
 124         rte_free(qp);
 125         dev->data->queue_pairs[qp_id] = NULL;
 126         return 0;
 127 }
 128
 129 static void
 130 mlx5_compress_init_sq(struct mlx5_compress_qp *qp)
 131 {
 132         volatile struct mlx5_gga_wqe *restrict wqe =
 133                                     (volatile struct mlx5_gga_wqe *)qp->sq.wqes;
 134         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 135         const uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u);
 136         const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 137                                         MLX5_COMP_MODE_OFFSET);
 138         const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
 139         int i;
 140
 141         /* All the next fields state should stay constant. */
 142         for (i = 0; i < qp->entries_n; ++i, ++wqe) {
 143                 wqe->sq_ds = sq_ds;
 144                 wqe->flags = flags;
 145                 wqe->opaque_lkey = opaq_lkey;
 146                 wqe->opaque_vaddr = rte_cpu_to_be_64
 147                                                 ((uint64_t)(uintptr_t)&opaq[i]);
 148         }
 149 }
 150
 151 static int
 152 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 153                        uint32_t max_inflight_ops, int socket_id)
 154 {
 155         struct mlx5_compress_priv *priv = dev->data->dev_private;
 156         struct mlx5_compress_qp *qp;
 157         struct mlx5_devx_cq_attr cq_attr = {
 158                 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
 159         };
 160         struct mlx5_devx_create_sq_attr sq_attr = {
 161                 .user_index = qp_id,
 162                 .wq_attr = (struct mlx5_devx_wq_attr){
 163                         .pd = priv->pdn,
 164                         .uar_page = mlx5_os_get_devx_uar_page_id(priv->uar),
 165                 },
 166         };
 167         struct mlx5_devx_modify_sq_attr modify_attr = {
 168                 .state = MLX5_SQC_STATE_RDY,
 169         };
 170         uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
 171         uint32_t alloc_size = sizeof(*qp);
 172         void *opaq_buf;
 173         int ret;
 174
 175         alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
 176         alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
 177         qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
 178                                 socket_id);
 179         if (qp == NULL) {
 180                 DRV_LOG(ERR, "Failed to allocate qp memory.");
 181                 rte_errno = ENOMEM;
 182                 return -rte_errno;
 183         }
 184         dev->data->queue_pairs[qp_id] = qp;
 185         opaq_buf = rte_calloc(__func__, 1u << log_ops_n,
 186                               sizeof(struct mlx5_gga_compress_opaque),
 187                               sizeof(struct mlx5_gga_compress_opaque));
 188         if (opaq_buf == NULL) {
 189                 DRV_LOG(ERR, "Failed to allocate opaque memory.");
 190                 rte_errno = ENOMEM;
 191                 goto err;
 192         }
 193         qp->entries_n = 1 << log_ops_n;
 194         qp->socket_id = socket_id;
 195         qp->qp_id = qp_id;
 196         qp->priv = priv;
 197         qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
 198                                                    RTE_CACHE_LINE_SIZE);
 199         qp->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
 200         MLX5_ASSERT(qp->uar_addr);
 201         if (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n *
 202                                         sizeof(struct mlx5_gga_compress_opaque),
 203                                                          &qp->opaque_mr) != 0) {
 204                 rte_free(opaq_buf);
 205                 DRV_LOG(ERR, "Failed to register opaque MR.");
 206                 rte_errno = ENOMEM;
 207                 goto err;
 208         }
 209         ret = mlx5_devx_cq_create(priv->ctx, &qp->cq, log_ops_n, &cq_attr,
 210                                   socket_id);
 211         if (ret != 0) {
 212                 DRV_LOG(ERR, "Failed to create CQ.");
 213                 goto err;
 214         }
 215         sq_attr.cqn = qp->cq.cq->id;
 216         ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,
 217                                   socket_id);
 218         if (ret != 0) {
 219                 DRV_LOG(ERR, "Failed to create SQ.");
 220                 goto err;
 221         }
 222         mlx5_compress_init_sq(qp);
 223         ret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr);
 224         if (ret != 0) {
 225                 DRV_LOG(ERR, "Can't change SQ state to ready.");
 226                 goto err;
 227         }
 228         DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u\n",
 229                 (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n);
 230         return 0;
 231 err:
 232         mlx5_compress_qp_release(dev, qp_id);
 233         return -1;
 234 }
 235
 236 static int
 237 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
 238 {
 239         struct mlx5_compress_priv *priv = dev->data->dev_private;
 240
 241         rte_spinlock_lock(&priv->xform_sl);
 242         LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
 243         rte_spinlock_unlock(&priv->xform_sl);
 244         rte_free(xform);
 245         return 0;
 246 }
 247
 248 static int
 249 mlx5_compress_xform_create(struct rte_compressdev *dev,
 250                            const struct rte_comp_xform *xform,
 251                            void **private_xform)
 252 {
 253         struct mlx5_compress_priv *priv = dev->data->dev_private;
 254         struct mlx5_compress_xform *xfrm;
 255         uint32_t size;
 256
 257         if (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==
 258                                                           RTE_COMP_LEVEL_NONE) {
 259                 DRV_LOG(ERR, "Non-compressed block is not supported.");
 260                 return -ENOTSUP;
 261         }
 262         if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=
 263              RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&
 264                       xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {
 265                 DRV_LOG(ERR, "SHA is not supported.");
 266                 return -ENOTSUP;
 267         }
 268         xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
 269                                                     priv->dev_config.socket_id);
 270         if (xfrm == NULL)
 271                 return -ENOMEM;
 272         xfrm->opcode = MLX5_OPCODE_MMO;
 273         xfrm->type = xform->type;
 274         switch (xform->type) {
 275         case RTE_COMP_COMPRESS:
 276                 switch (xform->compress.algo) {
 277                 case RTE_COMP_ALGO_NULL:
 278                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 279                                                         WQE_CSEG_OPC_MOD_OFFSET;
 280                         break;
 281                 case RTE_COMP_ALGO_DEFLATE:
 282                         size = 1 << xform->compress.window_size;
 283                         size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
 284                         xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 285                                          MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 286                                            WQE_GGA_COMP_WIN_SIZE_OFFSET;
 287                         if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
 288                                 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 289                         else
 290                                 size = priv->min_block_size - 1 +
 291                                                           xform->compress.level;
 292                         xfrm->gga_ctrl1 += RTE_MIN(size,
 293                                             MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
 294                                                  WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 295                         xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
 296                                                         WQE_CSEG_OPC_MOD_OFFSET;
 297                         size = xform->compress.deflate.huffman ==
 298                                                       RTE_COMP_HUFFMAN_DYNAMIC ?
 299                                             MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
 300                                              MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
 301                         xfrm->gga_ctrl1 += size <<
 302                                                WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
 303                         break;
 304                 default:
 305                         goto err;
 306                 }
 307                 xfrm->csum_type = xform->compress.chksum;
 308                 break;
 309         case RTE_COMP_DECOMPRESS:
 310                 switch (xform->decompress.algo) {
 311                 case RTE_COMP_ALGO_NULL:
 312                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 313                                                         WQE_CSEG_OPC_MOD_OFFSET;
 314                         break;
 315                 case RTE_COMP_ALGO_DEFLATE:
 316                         xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
 317                                                         WQE_CSEG_OPC_MOD_OFFSET;
 318                         break;
 319                 default:
 320                         goto err;
 321                 }
 322                 xfrm->csum_type = xform->decompress.chksum;
 323                 break;
 324         default:
 325                 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
 326                 goto err;
 327         }
 328         DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
 329                 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
 330         xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
 331         rte_spinlock_lock(&priv->xform_sl);
 332         LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
 333         rte_spinlock_unlock(&priv->xform_sl);
 334         *private_xform = xfrm;
 335         return 0;
 336 err:
 337         rte_free(xfrm);
 338         return -ENOTSUP;
 339 }
 340
 341 static struct rte_compressdev_ops mlx5_compress_ops = {
 342         .dev_configure          = mlx5_compress_dev_configure,
 343         .dev_start              = NULL,
 344         .dev_stop               = NULL,
 345         .dev_close              = mlx5_compress_dev_close,
 346         .dev_infos_get          = mlx5_compress_dev_info_get,
 347         .stats_get              = NULL,
 348         .stats_reset            = NULL,
 349         .queue_pair_setup       = mlx5_compress_qp_setup,
 350         .queue_pair_release     = mlx5_compress_qp_release,
 351         .private_xform_create   = mlx5_compress_xform_create,
 352         .private_xform_free     = mlx5_compress_xform_free,
 353         .stream_create          = NULL,
 354         .stream_free            = NULL,
 355 };
 356
 357 static struct ibv_device *
 358 mlx5_compress_get_ib_device_match(struct rte_pci_addr *addr)
 359 {
 360         int n;
 361         struct ibv_device **ibv_list = mlx5_glue->get_device_list(&n);
 362         struct ibv_device *ibv_match = NULL;
 363
 364         if (ibv_list == NULL) {
 365                 rte_errno = ENOSYS;
 366                 return NULL;
 367         }
 368         while (n-- > 0) {
 369                 struct rte_pci_addr paddr;
 370
 371                 DRV_LOG(DEBUG, "Checking device \"%s\"..", ibv_list[n]->name);
 372                 if (mlx5_dev_to_pci_addr(ibv_list[n]->ibdev_path, &paddr) != 0)
 373                         continue;
 374                 if (rte_pci_addr_cmp(addr, &paddr) != 0)
 375                         continue;
 376                 ibv_match = ibv_list[n];
 377                 break;
 378         }
 379         if (ibv_match == NULL)
 380                 rte_errno = ENOENT;
 381         mlx5_glue->free_device_list(ibv_list);
 382         return ibv_match;
 383 }
 384
 385 static void
 386 mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv)
 387 {
 388         if (priv->pd != NULL) {
 389                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 390                 priv->pd = NULL;
 391         }
 392         if (priv->uar != NULL) {
 393                 mlx5_glue->devx_free_uar(priv->uar);
 394                 priv->uar = NULL;
 395         }
 396 }
 397
 398 static int
 399 mlx5_compress_pd_create(struct mlx5_compress_priv *priv)
 400 {
 401 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 402         struct mlx5dv_obj obj;
 403         struct mlx5dv_pd pd_info;
 404         int ret;
 405
 406         priv->pd = mlx5_glue->alloc_pd(priv->ctx);
 407         if (priv->pd == NULL) {
 408                 DRV_LOG(ERR, "Failed to allocate PD.");
 409                 return errno ? -errno : -ENOMEM;
 410         }
 411         obj.pd.in = priv->pd;
 412         obj.pd.out = &pd_info;
 413         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 414         if (ret != 0) {
 415                 DRV_LOG(ERR, "Fail to get PD object info.");
 416                 mlx5_glue->dealloc_pd(priv->pd);
 417                 priv->pd = NULL;
 418                 return -errno;
 419         }
 420         priv->pdn = pd_info.pdn;
 421         return 0;
 422 #else
 423         (void)priv;
 424         DRV_LOG(ERR, "Cannot get pdn - no DV support.");
 425         return -ENOTSUP;
 426 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 427 }
 428
 429 static int
 430 mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv)
 431 {
 432         if (mlx5_compress_pd_create(priv) != 0)
 433                 return -1;
 434         priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
 435         if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
 436             NULL) {
 437                 rte_errno = errno;
 438                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 439                 DRV_LOG(ERR, "Failed to allocate UAR.");
 440                 return -1;
 441         }
 442         return 0;
 443 }
 444
 445 /**
 446  * DPDK callback to register a PCI device.
 447  *
 448  * This function spawns compress device out of a given PCI device.
 449  *
 450  * @param[in] pci_drv
 451  *   PCI driver structure (mlx5_compress_driver).
 452  * @param[in] pci_dev
 453  *   PCI device information.
 454  *
 455  * @return
 456  *   0 on success, 1 to skip this driver, a negative errno value otherwise
 457  *   and rte_errno is set.
 458  */
 459 static int
 460 mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv,
 461                         struct rte_pci_device *pci_dev)
 462 {
 463         struct ibv_device *ibv;
 464         struct rte_compressdev *cdev;
 465         struct ibv_context *ctx;
 466         struct mlx5_compress_priv *priv;
 467         struct mlx5_hca_attr att = { 0 };
 468         struct rte_compressdev_pmd_init_params init_params = {
 469                 .name = "",
 470                 .socket_id = pci_dev->device.numa_node,
 471         };
 472
 473         RTE_SET_USED(pci_drv);
 474         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 475                 DRV_LOG(ERR, "Non-primary process type is not supported.");
 476                 rte_errno = ENOTSUP;
 477                 return -rte_errno;
 478         }
 479         ibv = mlx5_compress_get_ib_device_match(&pci_dev->addr);
 480         if (ibv == NULL) {
 481                 DRV_LOG(ERR, "No matching IB device for PCI slot "
 482                         PCI_PRI_FMT ".", pci_dev->addr.domain,
 483                         pci_dev->addr.bus, pci_dev->addr.devid,
 484                         pci_dev->addr.function);
 485                 return -rte_errno;
 486         }
 487         DRV_LOG(INFO, "PCI information matches for device \"%s\".", ibv->name);
 488         ctx = mlx5_glue->dv_open_device(ibv);
 489         if (ctx == NULL) {
 490                 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name);
 491                 rte_errno = ENODEV;
 492                 return -rte_errno;
 493         }
 494         if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 ||
 495             att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 ||
 496             att.mmo_dma_en == 0) {
 497                 DRV_LOG(ERR, "Not enough capabilities to support compress "
 498                         "operations, maybe old FW/OFED version?");
 499                 claim_zero(mlx5_glue->close_device(ctx));
 500                 rte_errno = ENOTSUP;
 501                 return -ENOTSUP;
 502         }
 503         cdev = rte_compressdev_pmd_create(ibv->name, &pci_dev->device,
 504                                           sizeof(*priv), &init_params);
 505         if (cdev == NULL) {
 506                 DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name);
 507                 claim_zero(mlx5_glue->close_device(ctx));
 508                 return -ENODEV;
 509         }
 510         DRV_LOG(INFO,
 511                 "Compress device %s was created successfully.", ibv->name);
 512         cdev->dev_ops = &mlx5_compress_ops;
 513         cdev->dequeue_burst = NULL;
 514         cdev->enqueue_burst = NULL;
 515         cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 516         priv = cdev->data->dev_private;
 517         priv->ctx = ctx;
 518         priv->pci_dev = pci_dev;
 519         priv->cdev = cdev;
 520         priv->min_block_size = att.compress_min_block_size;
 521         if (mlx5_compress_hw_global_prepare(priv) != 0) {
 522                 rte_compressdev_pmd_destroy(priv->cdev);
 523                 claim_zero(mlx5_glue->close_device(priv->ctx));
 524                 return -1;
 525         }
 526         pthread_mutex_lock(&priv_list_lock);
 527         TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
 528         pthread_mutex_unlock(&priv_list_lock);
 529         return 0;
 530 }
 531
 532 /**
 533  * DPDK callback to remove a PCI device.
 534  *
 535  * This function removes all compress devices belong to a given PCI device.
 536  *
 537  * @param[in] pci_dev
 538  *   Pointer to the PCI device.
 539  *
 540  * @return
 541  *   0 on success, the function cannot fail.
 542  */
 543 static int
 544 mlx5_compress_pci_remove(struct rte_pci_device *pdev)
 545 {
 546         struct mlx5_compress_priv *priv = NULL;
 547
 548         pthread_mutex_lock(&priv_list_lock);
 549         TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 550                 if (rte_pci_addr_cmp(&priv->pci_dev->addr, &pdev->addr) != 0)
 551                         break;
 552         if (priv)
 553                 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
 554         pthread_mutex_unlock(&priv_list_lock);
 555         if (priv) {
 556                 mlx5_compress_hw_global_release(priv);
 557                 rte_compressdev_pmd_destroy(priv->cdev);
 558                 claim_zero(mlx5_glue->close_device(priv->ctx));
 559         }
 560         return 0;
 561 }
 562
 563 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
 564         {
 565                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 566                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
 567         },
 568         {
 569                 .vendor_id = 0
 570         }
 571 };
 572
 573 static struct mlx5_pci_driver mlx5_compress_driver = {
 574         .driver_class = MLX5_CLASS_COMPRESS,
 575         .pci_driver = {
 576                 .driver = {
 577                         .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
 578                 },
 579                 .id_table = mlx5_compress_pci_id_map,
 580                 .probe = mlx5_compress_pci_probe,
 581                 .remove = mlx5_compress_pci_remove,
 582                 .drv_flags = 0,
 583         },
 584 };
 585
 586 RTE_INIT(rte_mlx5_compress_init)
 587 {
 588         mlx5_common_init();
 589         if (mlx5_glue != NULL)
 590                 mlx5_pci_driver_register(&mlx5_compress_driver);
 591 }
 592
 593 RTE_LOG_REGISTER(mlx5_compress_logtype, MLX5_COMPRESS_LOG_NAME, NOTICE)
 594 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
 595 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
 596 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");