1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2021 Mellanox Technologies, Ltd
5 #include <rte_malloc.h>
9 #include <rte_spinlock.h>
11 #include <rte_compressdev.h>
12 #include <rte_compressdev_pmd.h>
14 #include <mlx5_glue.h>
15 #include <mlx5_common.h>
16 #include <mlx5_common_pci.h>
17 #include <mlx5_devx_cmds.h>
18 #include <mlx5_common_os.h>
19 #include <mlx5_common_devx.h>
20 #include <mlx5_common_mr.h>
23 #include "mlx5_compress_utils.h"
25 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
26 #define MLX5_COMPRESS_LOG_NAME pmd.compress.mlx5
27 #define MLX5_COMPRESS_MAX_QPS 1024
28 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
30 struct mlx5_compress_xform {
31 LIST_ENTRY(mlx5_compress_xform) next;
32 enum rte_comp_xform_type type;
33 enum rte_comp_checksum_type csum_type;
35 uint32_t gga_ctrl1; /* BE. */
38 struct mlx5_compress_priv {
39 TAILQ_ENTRY(mlx5_compress_priv) next;
40 struct ibv_context *ctx; /* Device context. */
41 struct rte_pci_device *pci_dev;
42 struct rte_compressdev *cdev;
44 uint32_t pdn; /* Protection Domain number. */
45 uint8_t min_block_size;
46 /* Minimum huffman block size supported by the device. */
48 struct rte_compressdev_config dev_config;
49 LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
50 rte_spinlock_t xform_sl;
53 struct mlx5_compress_qp {
58 volatile uint64_t *uar_addr;
60 struct mlx5_devx_cq cq;
61 struct mlx5_devx_sq sq;
62 struct mlx5_pmd_mr opaque_mr;
63 struct rte_comp_op **ops;
64 struct mlx5_compress_priv *priv;
67 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
68 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
69 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
71 int mlx5_compress_logtype;
73 const struct rte_compressdev_capabilities mlx5_caps[RTE_COMP_ALGO_LIST_END];
77 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
78 struct rte_compressdev_info *info)
82 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
83 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
84 info->capabilities = mlx5_caps;
89 mlx5_compress_dev_configure(struct rte_compressdev *dev,
90 struct rte_compressdev_config *config)
92 struct mlx5_compress_priv *priv;
94 if (dev == NULL || config == NULL)
96 priv = dev->data->dev_private;
97 priv->dev_config = *config;
102 mlx5_compress_dev_close(struct rte_compressdev *dev)
109 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
111 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
113 if (qp->sq.sq != NULL)
114 mlx5_devx_sq_destroy(&qp->sq);
115 if (qp->cq.cq != NULL)
116 mlx5_devx_cq_destroy(&qp->cq);
117 if (qp->opaque_mr.obj != NULL) {
118 void *opaq = qp->opaque_mr.addr;
120 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
125 dev->data->queue_pairs[qp_id] = NULL;
130 mlx5_compress_init_sq(struct mlx5_compress_qp *qp)
132 volatile struct mlx5_gga_wqe *restrict wqe =
133 (volatile struct mlx5_gga_wqe *)qp->sq.wqes;
134 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
135 const uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u);
136 const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
137 MLX5_COMP_MODE_OFFSET);
138 const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
141 /* All the next fields state should stay constant. */
142 for (i = 0; i < qp->entries_n; ++i, ++wqe) {
145 wqe->opaque_lkey = opaq_lkey;
146 wqe->opaque_vaddr = rte_cpu_to_be_64
147 ((uint64_t)(uintptr_t)&opaq[i]);
152 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
153 uint32_t max_inflight_ops, int socket_id)
155 struct mlx5_compress_priv *priv = dev->data->dev_private;
156 struct mlx5_compress_qp *qp;
157 struct mlx5_devx_cq_attr cq_attr = {
158 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
160 struct mlx5_devx_create_sq_attr sq_attr = {
162 .wq_attr = (struct mlx5_devx_wq_attr){
164 .uar_page = mlx5_os_get_devx_uar_page_id(priv->uar),
167 struct mlx5_devx_modify_sq_attr modify_attr = {
168 .state = MLX5_SQC_STATE_RDY,
170 uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
171 uint32_t alloc_size = sizeof(*qp);
175 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
176 alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
177 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
180 DRV_LOG(ERR, "Failed to allocate qp memory.");
184 dev->data->queue_pairs[qp_id] = qp;
185 opaq_buf = rte_calloc(__func__, 1u << log_ops_n,
186 sizeof(struct mlx5_gga_compress_opaque),
187 sizeof(struct mlx5_gga_compress_opaque));
188 if (opaq_buf == NULL) {
189 DRV_LOG(ERR, "Failed to allocate opaque memory.");
193 qp->entries_n = 1 << log_ops_n;
194 qp->socket_id = socket_id;
197 qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
198 RTE_CACHE_LINE_SIZE);
199 qp->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
200 MLX5_ASSERT(qp->uar_addr);
201 if (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n *
202 sizeof(struct mlx5_gga_compress_opaque),
203 &qp->opaque_mr) != 0) {
205 DRV_LOG(ERR, "Failed to register opaque MR.");
209 ret = mlx5_devx_cq_create(priv->ctx, &qp->cq, log_ops_n, &cq_attr,
212 DRV_LOG(ERR, "Failed to create CQ.");
215 sq_attr.cqn = qp->cq.cq->id;
216 ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,
219 DRV_LOG(ERR, "Failed to create SQ.");
222 mlx5_compress_init_sq(qp);
223 ret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr);
225 DRV_LOG(ERR, "Can't change SQ state to ready.");
228 DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u\n",
229 (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n);
232 mlx5_compress_qp_release(dev, qp_id);
237 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
239 struct mlx5_compress_priv *priv = dev->data->dev_private;
241 rte_spinlock_lock(&priv->xform_sl);
242 LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
243 rte_spinlock_unlock(&priv->xform_sl);
249 mlx5_compress_xform_create(struct rte_compressdev *dev,
250 const struct rte_comp_xform *xform,
251 void **private_xform)
253 struct mlx5_compress_priv *priv = dev->data->dev_private;
254 struct mlx5_compress_xform *xfrm;
257 if (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==
258 RTE_COMP_LEVEL_NONE) {
259 DRV_LOG(ERR, "Non-compressed block is not supported.");
262 if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=
263 RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&
264 xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {
265 DRV_LOG(ERR, "SHA is not supported.");
268 xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
269 priv->dev_config.socket_id);
272 xfrm->opcode = MLX5_OPCODE_MMO;
273 xfrm->type = xform->type;
274 switch (xform->type) {
275 case RTE_COMP_COMPRESS:
276 switch (xform->compress.algo) {
277 case RTE_COMP_ALGO_NULL:
278 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
279 WQE_CSEG_OPC_MOD_OFFSET;
281 case RTE_COMP_ALGO_DEFLATE:
282 size = 1 << xform->compress.window_size;
283 size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
284 xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
285 MLX5_COMP_MAX_WIN_SIZE_CONF) <<
286 WQE_GGA_COMP_WIN_SIZE_OFFSET;
287 if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
288 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
290 size = priv->min_block_size - 1 +
291 xform->compress.level;
292 xfrm->gga_ctrl1 += RTE_MIN(size,
293 MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
294 WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
295 xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
296 WQE_CSEG_OPC_MOD_OFFSET;
297 size = xform->compress.deflate.huffman ==
298 RTE_COMP_HUFFMAN_DYNAMIC ?
299 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
300 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
301 xfrm->gga_ctrl1 += size <<
302 WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
307 xfrm->csum_type = xform->compress.chksum;
309 case RTE_COMP_DECOMPRESS:
310 switch (xform->decompress.algo) {
311 case RTE_COMP_ALGO_NULL:
312 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
313 WQE_CSEG_OPC_MOD_OFFSET;
315 case RTE_COMP_ALGO_DEFLATE:
316 xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
317 WQE_CSEG_OPC_MOD_OFFSET;
322 xfrm->csum_type = xform->decompress.chksum;
325 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
328 DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
329 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
330 xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
331 rte_spinlock_lock(&priv->xform_sl);
332 LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
333 rte_spinlock_unlock(&priv->xform_sl);
334 *private_xform = xfrm;
341 static struct rte_compressdev_ops mlx5_compress_ops = {
342 .dev_configure = mlx5_compress_dev_configure,
345 .dev_close = mlx5_compress_dev_close,
346 .dev_infos_get = mlx5_compress_dev_info_get,
349 .queue_pair_setup = mlx5_compress_qp_setup,
350 .queue_pair_release = mlx5_compress_qp_release,
351 .private_xform_create = mlx5_compress_xform_create,
352 .private_xform_free = mlx5_compress_xform_free,
353 .stream_create = NULL,
357 static struct ibv_device *
358 mlx5_compress_get_ib_device_match(struct rte_pci_addr *addr)
361 struct ibv_device **ibv_list = mlx5_glue->get_device_list(&n);
362 struct ibv_device *ibv_match = NULL;
364 if (ibv_list == NULL) {
369 struct rte_pci_addr paddr;
371 DRV_LOG(DEBUG, "Checking device \"%s\"..", ibv_list[n]->name);
372 if (mlx5_dev_to_pci_addr(ibv_list[n]->ibdev_path, &paddr) != 0)
374 if (rte_pci_addr_cmp(addr, &paddr) != 0)
376 ibv_match = ibv_list[n];
379 if (ibv_match == NULL)
381 mlx5_glue->free_device_list(ibv_list);
386 mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv)
388 if (priv->pd != NULL) {
389 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
392 if (priv->uar != NULL) {
393 mlx5_glue->devx_free_uar(priv->uar);
399 mlx5_compress_pd_create(struct mlx5_compress_priv *priv)
401 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
402 struct mlx5dv_obj obj;
403 struct mlx5dv_pd pd_info;
406 priv->pd = mlx5_glue->alloc_pd(priv->ctx);
407 if (priv->pd == NULL) {
408 DRV_LOG(ERR, "Failed to allocate PD.");
409 return errno ? -errno : -ENOMEM;
411 obj.pd.in = priv->pd;
412 obj.pd.out = &pd_info;
413 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
415 DRV_LOG(ERR, "Fail to get PD object info.");
416 mlx5_glue->dealloc_pd(priv->pd);
420 priv->pdn = pd_info.pdn;
424 DRV_LOG(ERR, "Cannot get pdn - no DV support.");
426 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
430 mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv)
432 if (mlx5_compress_pd_create(priv) != 0)
434 priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
435 if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
438 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
439 DRV_LOG(ERR, "Failed to allocate UAR.");
446 * DPDK callback to register a PCI device.
448 * This function spawns compress device out of a given PCI device.
451 * PCI driver structure (mlx5_compress_driver).
453 * PCI device information.
456 * 0 on success, 1 to skip this driver, a negative errno value otherwise
457 * and rte_errno is set.
460 mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv,
461 struct rte_pci_device *pci_dev)
463 struct ibv_device *ibv;
464 struct rte_compressdev *cdev;
465 struct ibv_context *ctx;
466 struct mlx5_compress_priv *priv;
467 struct mlx5_hca_attr att = { 0 };
468 struct rte_compressdev_pmd_init_params init_params = {
470 .socket_id = pci_dev->device.numa_node,
473 RTE_SET_USED(pci_drv);
474 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
475 DRV_LOG(ERR, "Non-primary process type is not supported.");
479 ibv = mlx5_compress_get_ib_device_match(&pci_dev->addr);
481 DRV_LOG(ERR, "No matching IB device for PCI slot "
482 PCI_PRI_FMT ".", pci_dev->addr.domain,
483 pci_dev->addr.bus, pci_dev->addr.devid,
484 pci_dev->addr.function);
487 DRV_LOG(INFO, "PCI information matches for device \"%s\".", ibv->name);
488 ctx = mlx5_glue->dv_open_device(ibv);
490 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name);
494 if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 ||
495 att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 ||
496 att.mmo_dma_en == 0) {
497 DRV_LOG(ERR, "Not enough capabilities to support compress "
498 "operations, maybe old FW/OFED version?");
499 claim_zero(mlx5_glue->close_device(ctx));
503 cdev = rte_compressdev_pmd_create(ibv->name, &pci_dev->device,
504 sizeof(*priv), &init_params);
506 DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name);
507 claim_zero(mlx5_glue->close_device(ctx));
511 "Compress device %s was created successfully.", ibv->name);
512 cdev->dev_ops = &mlx5_compress_ops;
513 cdev->dequeue_burst = NULL;
514 cdev->enqueue_burst = NULL;
515 cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
516 priv = cdev->data->dev_private;
518 priv->pci_dev = pci_dev;
520 priv->min_block_size = att.compress_min_block_size;
521 if (mlx5_compress_hw_global_prepare(priv) != 0) {
522 rte_compressdev_pmd_destroy(priv->cdev);
523 claim_zero(mlx5_glue->close_device(priv->ctx));
526 pthread_mutex_lock(&priv_list_lock);
527 TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
528 pthread_mutex_unlock(&priv_list_lock);
533 * DPDK callback to remove a PCI device.
535 * This function removes all compress devices belong to a given PCI device.
538 * Pointer to the PCI device.
541 * 0 on success, the function cannot fail.
544 mlx5_compress_pci_remove(struct rte_pci_device *pdev)
546 struct mlx5_compress_priv *priv = NULL;
548 pthread_mutex_lock(&priv_list_lock);
549 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
550 if (rte_pci_addr_cmp(&priv->pci_dev->addr, &pdev->addr) != 0)
553 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
554 pthread_mutex_unlock(&priv_list_lock);
556 mlx5_compress_hw_global_release(priv);
557 rte_compressdev_pmd_destroy(priv->cdev);
558 claim_zero(mlx5_glue->close_device(priv->ctx));
563 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
565 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
566 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
573 static struct mlx5_pci_driver mlx5_compress_driver = {
574 .driver_class = MLX5_CLASS_COMPRESS,
577 .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
579 .id_table = mlx5_compress_pci_id_map,
580 .probe = mlx5_compress_pci_probe,
581 .remove = mlx5_compress_pci_remove,
586 RTE_INIT(rte_mlx5_compress_init)
589 if (mlx5_glue != NULL)
590 mlx5_pci_driver_register(&mlx5_compress_driver);
593 RTE_LOG_REGISTER(mlx5_compress_logtype, MLX5_COMPRESS_LOG_NAME, NOTICE)
594 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
595 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
596 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");