drivers/compress/mlx5/mlx5_compress.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_log.h>
   7 #include <rte_errno.h>
   8 #include <rte_bus_pci.h>
   9 #include <rte_spinlock.h>
  10 #include <rte_comp.h>
  11 #include <rte_compressdev.h>
  12 #include <rte_compressdev_pmd.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_common.h>
  16 #include <mlx5_devx_cmds.h>
  17 #include <mlx5_common_os.h>
  18 #include <mlx5_common_devx.h>
  19 #include <mlx5_common_mr.h>
  20 #include <mlx5_prm.h>
  21
  22 #include "mlx5_compress_utils.h"
  23
  24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
  25 #define MLX5_COMPRESS_MAX_QPS 1024
  26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
  27
  28 struct mlx5_compress_devarg_params {
  29         uint32_t log_block_sz;
  30 };
  31
  32 struct mlx5_compress_xform {
  33         LIST_ENTRY(mlx5_compress_xform) next;
  34         enum rte_comp_xform_type type;
  35         enum rte_comp_checksum_type csum_type;
  36         uint32_t opcode;
  37         uint32_t gga_ctrl1; /* BE. */
  38 };
  39
  40 struct mlx5_compress_priv {
  41         TAILQ_ENTRY(mlx5_compress_priv) next;
  42         struct rte_compressdev *compressdev;
  43         struct mlx5_common_device *cdev; /* Backend mlx5 device. */
  44         struct mlx5_uar uar;
  45         uint8_t min_block_size;
  46         /* Minimum huffman block size supported by the device. */
  47         struct rte_compressdev_config dev_config;
  48         LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
  49         rte_spinlock_t xform_sl;
  50         /* HCA caps */
  51         uint32_t mmo_decomp_sq:1;
  52         uint32_t mmo_decomp_qp:1;
  53         uint32_t mmo_comp_sq:1;
  54         uint32_t mmo_comp_qp:1;
  55         uint32_t mmo_dma_sq:1;
  56         uint32_t mmo_dma_qp:1;
  57         uint32_t log_block_sz;
  58 };
  59
  60 struct mlx5_compress_qp {
  61         uint16_t qp_id;
  62         uint16_t entries_n;
  63         uint16_t pi;
  64         uint16_t ci;
  65         struct mlx5_mr_ctrl mr_ctrl;
  66         int socket_id;
  67         struct mlx5_devx_cq cq;
  68         struct mlx5_devx_qp qp;
  69         struct mlx5_pmd_mr opaque_mr;
  70         struct rte_comp_op **ops;
  71         struct mlx5_compress_priv *priv;
  72         struct rte_compressdev_stats stats;
  73 };
  74
  75 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
  76                                 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
  77 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
  78
  79 int mlx5_compress_logtype;
  80
  81 static const struct rte_compressdev_capabilities mlx5_caps[] = {
  82         {
  83                 .algo = RTE_COMP_ALGO_NULL,
  84                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  85                                       RTE_COMP_FF_CRC32_CHECKSUM |
  86                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  87                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM,
  88         },
  89         {
  90                 .algo = RTE_COMP_ALGO_DEFLATE,
  91                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  92                                       RTE_COMP_FF_CRC32_CHECKSUM |
  93                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  94                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
  95                                       RTE_COMP_FF_HUFFMAN_FIXED |
  96                                       RTE_COMP_FF_HUFFMAN_DYNAMIC,
  97                 .window_size = {.min = 10, .max = 15, .increment = 1},
  98         },
  99         {
 100                 .algo = RTE_COMP_ALGO_LIST_END,
 101         }
 102 };
 103
 104 static void
 105 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
 106                            struct rte_compressdev_info *info)
 107 {
 108         RTE_SET_USED(dev);
 109         if (info != NULL) {
 110                 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
 111                 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 112                 info->capabilities = mlx5_caps;
 113         }
 114 }
 115
 116 static int
 117 mlx5_compress_dev_configure(struct rte_compressdev *dev,
 118                             struct rte_compressdev_config *config)
 119 {
 120         struct mlx5_compress_priv *priv;
 121
 122         if (dev == NULL || config == NULL)
 123                 return -EINVAL;
 124         priv = dev->data->dev_private;
 125         priv->dev_config = *config;
 126         return 0;
 127 }
 128
 129 static int
 130 mlx5_compress_dev_close(struct rte_compressdev *dev)
 131 {
 132         RTE_SET_USED(dev);
 133         return 0;
 134 }
 135
 136 static int
 137 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
 138 {
 139         struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 140
 141         if (qp->qp.qp != NULL)
 142                 mlx5_devx_qp_destroy(&qp->qp);
 143         if (qp->cq.cq != NULL)
 144                 mlx5_devx_cq_destroy(&qp->cq);
 145         if (qp->opaque_mr.obj != NULL) {
 146                 void *opaq = qp->opaque_mr.addr;
 147
 148                 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
 149                 rte_free(opaq);
 150         }
 151         mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
 152         rte_free(qp);
 153         dev->data->queue_pairs[qp_id] = NULL;
 154         return 0;
 155 }
 156
 157 static void
 158 mlx5_compress_init_qp(struct mlx5_compress_qp *qp)
 159 {
 160         volatile struct mlx5_gga_wqe *restrict wqe =
 161                                     (volatile struct mlx5_gga_wqe *)qp->qp.wqes;
 162         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 163         const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u);
 164         const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 165                                         MLX5_COMP_MODE_OFFSET);
 166         const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
 167         int i;
 168
 169         /* All the next fields state should stay constant. */
 170         for (i = 0; i < qp->entries_n; ++i, ++wqe) {
 171                 wqe->sq_ds = sq_ds;
 172                 wqe->flags = flags;
 173                 wqe->opaque_lkey = opaq_lkey;
 174                 wqe->opaque_vaddr = rte_cpu_to_be_64
 175                                                 ((uint64_t)(uintptr_t)&opaq[i]);
 176         }
 177 }
 178
 179 static int
 180 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 181                        uint32_t max_inflight_ops, int socket_id)
 182 {
 183         struct mlx5_compress_priv *priv = dev->data->dev_private;
 184         struct mlx5_compress_qp *qp;
 185         struct mlx5_devx_cq_attr cq_attr = {
 186                 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar.obj),
 187         };
 188         struct mlx5_devx_qp_attr qp_attr = {
 189                 .pd = priv->cdev->pdn,
 190                 .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar.obj),
 191                 .user_index = qp_id,
 192         };
 193         uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
 194         uint32_t alloc_size = sizeof(*qp);
 195         void *opaq_buf;
 196         int ret;
 197
 198         alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
 199         alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
 200         qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
 201                                 socket_id);
 202         if (qp == NULL) {
 203                 DRV_LOG(ERR, "Failed to allocate qp memory.");
 204                 rte_errno = ENOMEM;
 205                 return -rte_errno;
 206         }
 207         dev->data->queue_pairs[qp_id] = qp;
 208         if (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->cdev->mr_scache.dev_gen,
 209                               priv->dev_config.socket_id)) {
 210                 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
 211                         (uint32_t)qp_id);
 212                 rte_errno = ENOMEM;
 213                 goto err;
 214         }
 215         opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n,
 216                               sizeof(struct mlx5_gga_compress_opaque),
 217                               sizeof(struct mlx5_gga_compress_opaque));
 218         if (opaq_buf == NULL) {
 219                 DRV_LOG(ERR, "Failed to allocate opaque memory.");
 220                 rte_errno = ENOMEM;
 221                 goto err;
 222         }
 223         qp->entries_n = 1 << log_ops_n;
 224         qp->socket_id = socket_id;
 225         qp->qp_id = qp_id;
 226         qp->priv = priv;
 227         qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
 228                                                    RTE_CACHE_LINE_SIZE);
 229         if (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n *
 230                                         sizeof(struct mlx5_gga_compress_opaque),
 231                                                          &qp->opaque_mr) != 0) {
 232                 rte_free(opaq_buf);
 233                 DRV_LOG(ERR, "Failed to register opaque MR.");
 234                 rte_errno = ENOMEM;
 235                 goto err;
 236         }
 237         ret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr,
 238                                   socket_id);
 239         if (ret != 0) {
 240                 DRV_LOG(ERR, "Failed to create CQ.");
 241                 goto err;
 242         }
 243         qp_attr.cqn = qp->cq.cq->id;
 244         qp_attr.ts_format =
 245                 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
 246         qp_attr.num_of_receive_wqes = 0;
 247         qp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n);
 248         qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp
 249                         && priv->mmo_dma_qp;
 250         ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp,
 251                                         qp_attr.num_of_send_wqbbs *
 252                                         MLX5_WQE_SIZE, &qp_attr, socket_id);
 253         if (ret != 0) {
 254                 DRV_LOG(ERR, "Failed to create QP.");
 255                 goto err;
 256         }
 257         mlx5_compress_init_qp(qp);
 258         ret = mlx5_devx_qp2rts(&qp->qp, 0);
 259         if (ret)
 260                 goto err;
 261         DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u",
 262                 (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n);
 263         return 0;
 264 err:
 265         mlx5_compress_qp_release(dev, qp_id);
 266         return -1;
 267 }
 268
 269 static int
 270 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
 271 {
 272         struct mlx5_compress_priv *priv = dev->data->dev_private;
 273
 274         rte_spinlock_lock(&priv->xform_sl);
 275         LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
 276         rte_spinlock_unlock(&priv->xform_sl);
 277         rte_free(xform);
 278         return 0;
 279 }
 280
 281 static int
 282 mlx5_compress_xform_create(struct rte_compressdev *dev,
 283                            const struct rte_comp_xform *xform,
 284                            void **private_xform)
 285 {
 286         struct mlx5_compress_priv *priv = dev->data->dev_private;
 287         struct mlx5_compress_xform *xfrm;
 288         uint32_t size;
 289
 290         switch (xform->type) {
 291         case RTE_COMP_COMPRESS:
 292                 if (xform->compress.algo == RTE_COMP_ALGO_NULL &&
 293                                 !priv->mmo_dma_qp && !priv->mmo_dma_sq) {
 294                         DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?");
 295                         return -ENOTSUP;
 296                 } else if (!priv->mmo_comp_qp && !priv->mmo_comp_sq) {
 297                         DRV_LOG(ERR, "Not enough capabilities to support compress operation, maybe old FW/OFED version?");
 298                         return -ENOTSUP;
 299                 }
 300                 if (xform->compress.level == RTE_COMP_LEVEL_NONE) {
 301                         DRV_LOG(ERR, "Non-compressed block is not supported.");
 302                         return -ENOTSUP;
 303                 }
 304                 if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) {
 305                         DRV_LOG(ERR, "SHA is not supported.");
 306                         return -ENOTSUP;
 307                 }
 308                 break;
 309         case RTE_COMP_DECOMPRESS:
 310                 if (xform->decompress.algo == RTE_COMP_ALGO_NULL &&
 311                                 !priv->mmo_dma_qp && !priv->mmo_dma_sq) {
 312                         DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?");
 313                         return -ENOTSUP;
 314                 } else if (!priv->mmo_decomp_qp && !priv->mmo_decomp_sq) {
 315                         DRV_LOG(ERR, "Not enough capabilities to support decompress operation, maybe old FW/OFED version?");
 316                         return -ENOTSUP;
 317                 }
 318                 if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) {
 319                         DRV_LOG(ERR, "SHA is not supported.");
 320                         return -ENOTSUP;
 321                 }
 322                 break;
 323         default:
 324                 DRV_LOG(ERR, "Xform type should be compress/decompress");
 325                 return -ENOTSUP;
 326         }
 327
 328         xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
 329                                                     priv->dev_config.socket_id);
 330         if (xfrm == NULL)
 331                 return -ENOMEM;
 332         xfrm->opcode = MLX5_OPCODE_MMO;
 333         xfrm->type = xform->type;
 334         switch (xform->type) {
 335         case RTE_COMP_COMPRESS:
 336                 switch (xform->compress.algo) {
 337                 case RTE_COMP_ALGO_NULL:
 338                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 339                                                         WQE_CSEG_OPC_MOD_OFFSET;
 340                         break;
 341                 case RTE_COMP_ALGO_DEFLATE:
 342                         size = 1 << xform->compress.window_size;
 343                         size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
 344                         xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 345                                          MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 346                                                 WQE_GGA_COMP_WIN_SIZE_OFFSET;
 347                         size = priv->log_block_sz;
 348                         xfrm->gga_ctrl1 += size <<
 349                                                 WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 350                         xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
 351                                                         WQE_CSEG_OPC_MOD_OFFSET;
 352                         size = xform->compress.deflate.huffman ==
 353                                                       RTE_COMP_HUFFMAN_DYNAMIC ?
 354                                             MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
 355                                              MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
 356                         xfrm->gga_ctrl1 += size <<
 357                                                WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
 358                         break;
 359                 default:
 360                         goto err;
 361                 }
 362                 xfrm->csum_type = xform->compress.chksum;
 363                 break;
 364         case RTE_COMP_DECOMPRESS:
 365                 switch (xform->decompress.algo) {
 366                 case RTE_COMP_ALGO_NULL:
 367                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 368                                                         WQE_CSEG_OPC_MOD_OFFSET;
 369                         break;
 370                 case RTE_COMP_ALGO_DEFLATE:
 371                         xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
 372                                                         WQE_CSEG_OPC_MOD_OFFSET;
 373                         break;
 374                 default:
 375                         goto err;
 376                 }
 377                 xfrm->csum_type = xform->decompress.chksum;
 378                 break;
 379         default:
 380                 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
 381                 goto err;
 382         }
 383         DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
 384                 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
 385         xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
 386         rte_spinlock_lock(&priv->xform_sl);
 387         LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
 388         rte_spinlock_unlock(&priv->xform_sl);
 389         *private_xform = xfrm;
 390         return 0;
 391 err:
 392         rte_free(xfrm);
 393         return -ENOTSUP;
 394 }
 395
 396 static void
 397 mlx5_compress_dev_stop(struct rte_compressdev *dev)
 398 {
 399         RTE_SET_USED(dev);
 400 }
 401
 402 static int
 403 mlx5_compress_dev_start(struct rte_compressdev *dev)
 404 {
 405         struct mlx5_compress_priv *priv = dev->data->dev_private;
 406
 407         return mlx5_dev_mempool_subscribe(priv->cdev);
 408 }
 409
 410 static void
 411 mlx5_compress_stats_get(struct rte_compressdev *dev,
 412                 struct rte_compressdev_stats *stats)
 413 {
 414         int qp_id;
 415
 416         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 417                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 418
 419                 stats->enqueued_count += qp->stats.enqueued_count;
 420                 stats->dequeued_count += qp->stats.dequeued_count;
 421                 stats->enqueue_err_count += qp->stats.enqueue_err_count;
 422                 stats->dequeue_err_count += qp->stats.dequeue_err_count;
 423         }
 424 }
 425
 426 static void
 427 mlx5_compress_stats_reset(struct rte_compressdev *dev)
 428 {
 429         int qp_id;
 430
 431         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 432                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 433
 434                 memset(&qp->stats, 0, sizeof(qp->stats));
 435         }
 436 }
 437
 438 static struct rte_compressdev_ops mlx5_compress_ops = {
 439         .dev_configure          = mlx5_compress_dev_configure,
 440         .dev_start              = mlx5_compress_dev_start,
 441         .dev_stop               = mlx5_compress_dev_stop,
 442         .dev_close              = mlx5_compress_dev_close,
 443         .dev_infos_get          = mlx5_compress_dev_info_get,
 444         .stats_get              = mlx5_compress_stats_get,
 445         .stats_reset            = mlx5_compress_stats_reset,
 446         .queue_pair_setup       = mlx5_compress_qp_setup,
 447         .queue_pair_release     = mlx5_compress_qp_release,
 448         .private_xform_create   = mlx5_compress_xform_create,
 449         .private_xform_free     = mlx5_compress_xform_free,
 450         .stream_create          = NULL,
 451         .stream_free            = NULL,
 452 };
 453
 454 static __rte_always_inline uint32_t
 455 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
 456                        volatile struct mlx5_wqe_dseg *restrict dseg,
 457                        struct rte_mbuf *restrict mbuf,
 458                        uint32_t offset, uint32_t len)
 459 {
 460         uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
 461
 462         dseg->bcount = rte_cpu_to_be_32(len);
 463         dseg->lkey = mlx5_mr_mb2mr(&qp->mr_ctrl, mbuf);
 464         dseg->pbuf = rte_cpu_to_be_64(addr);
 465         return dseg->lkey;
 466 }
 467
 468 static uint16_t
 469 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
 470                             uint16_t nb_ops)
 471 {
 472         struct mlx5_compress_qp *qp = queue_pair;
 473         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 474                                                               qp->qp.wqes, *wqe;
 475         struct mlx5_compress_xform *xform;
 476         struct rte_comp_op *op;
 477         uint16_t mask = qp->entries_n - 1;
 478         uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
 479         uint16_t idx;
 480         bool invalid;
 481
 482         if (remain < nb_ops)
 483                 nb_ops = remain;
 484         else
 485                 remain = nb_ops;
 486         if (unlikely(remain == 0))
 487                 return 0;
 488         do {
 489                 idx = qp->pi & mask;
 490                 wqe = &wqes[idx];
 491                 rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
 492                 op = *ops++;
 493                 xform = op->private_xform;
 494                 /*
 495                  * Check operation arguments and error cases:
 496                  *   - Operation type must be state-less.
 497                  *   - Compress operation flush flag must be FULL or FINAL.
 498                  *   - Source and destination buffers must be mapped internally.
 499                  */
 500                 invalid = op->op_type != RTE_COMP_OP_STATELESS ||
 501                                             (xform->type == RTE_COMP_COMPRESS &&
 502                                           op->flush_flag < RTE_COMP_FLUSH_FULL);
 503                 if (unlikely(invalid ||
 504                              (mlx5_compress_dseg_set(qp, &wqe->gather,
 505                                                      op->m_src,
 506                                                      op->src.offset,
 507                                                      op->src.length) ==
 508                                                                   UINT32_MAX) ||
 509                              (mlx5_compress_dseg_set(qp, &wqe->scatter,
 510                                                 op->m_dst,
 511                                                 op->dst.offset,
 512                                                 rte_pktmbuf_pkt_len(op->m_dst) -
 513                                                               op->dst.offset) ==
 514                                                                  UINT32_MAX))) {
 515                         op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
 516                                                        RTE_COMP_OP_STATUS_ERROR;
 517                         nb_ops -= remain;
 518                         if (unlikely(nb_ops == 0))
 519                                 return 0;
 520                         break;
 521                 }
 522                 wqe->gga_ctrl1 = xform->gga_ctrl1;
 523                 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
 524                 qp->ops[idx] = op;
 525                 qp->pi++;
 526         } while (--remain);
 527         qp->stats.enqueued_count += nb_ops;
 528         mlx5_doorbell_ring(&qp->priv->uar.bf_db, *(volatile uint64_t *)wqe,
 529                            qp->pi, &qp->qp.db_rec[MLX5_SND_DBR],
 530                            !qp->priv->uar.dbnc);
 531         return nb_ops;
 532 }
 533
 534 static void
 535 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
 536                              volatile uint32_t *opaq)
 537 {
 538         size_t i;
 539
 540         DRV_LOG(ERR, "Error cqe:");
 541         for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
 542                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 543                         cqe[i + 2], cqe[i + 3]);
 544         DRV_LOG(ERR, "\nError wqe:");
 545         for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
 546                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 547                         wqe[i + 2], wqe[i + 3]);
 548         DRV_LOG(ERR, "\nError opaq:");
 549         for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
 550                 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
 551                         opaq[i + 2], opaq[i + 3]);
 552 }
 553
 554 static void
 555 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
 556                              struct rte_comp_op *op)
 557 {
 558         const uint32_t idx = qp->ci & (qp->entries_n - 1);
 559         volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
 560                                                               &qp->cq.cqes[idx];
 561         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 562                                                                     qp->qp.wqes;
 563         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 564
 565         volatile uint32_t *synd_word = RTE_PTR_ADD(cqe, MLX5_ERROR_CQE_SYNDROME_OFFSET);
 566         switch (*synd_word) {
 567         case MLX5_GGA_COMP_OUT_OF_SPACE_SYNDROME_BE:
 568                 op->status = RTE_COMP_OP_STATUS_OUT_OF_SPACE_TERMINATED;
 569                 DRV_LOG(DEBUG, "OUT OF SPACE error, output is bigger than dst buffer.");
 570                 break;
 571         case MLX5_GGA_COMP_MISSING_BFINAL_SYNDROME_BE:
 572                 DRV_LOG(DEBUG, "The last compressed block missed the B-final flag; maybe the compressed data is not complete or garbaged?");
 573                 /* fallthrough */
 574         default:
 575                 op->status = RTE_COMP_OP_STATUS_ERROR;
 576         }
 577         op->consumed = 0;
 578         op->produced = 0;
 579         op->output_chksum = 0;
 580         op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
 581                               ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
 582         mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
 583                                  (volatile uint32_t *)&wqes[idx],
 584                                  (volatile uint32_t *)&opaq[idx]);
 585         qp->stats.dequeue_err_count++;
 586 }
 587
 588 static uint16_t
 589 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
 590                             uint16_t nb_ops)
 591 {
 592         struct mlx5_compress_qp *qp = queue_pair;
 593         volatile struct mlx5_compress_xform *restrict xform;
 594         volatile struct mlx5_cqe *restrict cqe;
 595         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 596         struct rte_comp_op *restrict op;
 597         const unsigned int cq_size = qp->entries_n;
 598         const unsigned int mask = cq_size - 1;
 599         uint32_t idx;
 600         uint32_t next_idx = qp->ci & mask;
 601         const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
 602         uint16_t i = 0;
 603         int ret;
 604
 605         if (unlikely(max == 0))
 606                 return 0;
 607         do {
 608                 idx = next_idx;
 609                 next_idx = (qp->ci + 1) & mask;
 610                 rte_prefetch0(&qp->cq.cqes[next_idx]);
 611                 rte_prefetch0(qp->ops[next_idx]);
 612                 op = qp->ops[idx];
 613                 cqe = &qp->cq.cqes[idx];
 614                 ret = check_cqe(cqe, cq_size, qp->ci);
 615                 /*
 616                  * Be sure owner read is done before any other cookie field or
 617                  * opaque field.
 618                  */
 619                 rte_io_rmb();
 620                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 621                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 622                                 break;
 623                         mlx5_compress_cqe_err_handle(qp, op);
 624                 } else {
 625                         xform = op->private_xform;
 626                         op->status = RTE_COMP_OP_STATUS_SUCCESS;
 627                         op->consumed = op->src.length;
 628                         op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
 629                         MLX5_ASSERT(cqe->byte_cnt ==
 630                                     opaq[idx].scattered_length);
 631                         switch (xform->csum_type) {
 632                         case RTE_COMP_CHECKSUM_CRC32:
 633                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 634                                                     (opaq[idx].crc32);
 635                                 break;
 636                         case RTE_COMP_CHECKSUM_ADLER32:
 637                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 638                                             (opaq[idx].adler32) << 32;
 639                                 break;
 640                         case RTE_COMP_CHECKSUM_CRC32_ADLER32:
 641                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 642                                                              (opaq[idx].crc32) |
 643                                                      ((uint64_t)rte_be_to_cpu_32
 644                                                      (opaq[idx].adler32) << 32);
 645                                 break;
 646                         default:
 647                                 break;
 648                         }
 649                 }
 650                 ops[i++] = op;
 651                 qp->ci++;
 652         } while (i < max);
 653         if (likely(i != 0)) {
 654                 rte_io_wmb();
 655                 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
 656                 qp->stats.dequeued_count += i;
 657         }
 658         return i;
 659 }
 660
 661 static int
 662 mlx5_compress_args_check_handler(const char *key, const char *val, void *opaque)
 663 {
 664         struct mlx5_compress_devarg_params *devarg_prms = opaque;
 665
 666         if (strcmp(key, "log-block-size") == 0) {
 667                 errno = 0;
 668                 devarg_prms->log_block_sz = (uint32_t)strtoul(val, NULL, 10);
 669                 if (errno) {
 670                         DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer.",
 671                                 key, val);
 672                         return -errno;
 673                 }
 674         }
 675         return 0;
 676 }
 677
 678 static int
 679 mlx5_compress_handle_devargs(struct mlx5_kvargs_ctrl *mkvlist,
 680                              struct mlx5_compress_devarg_params *devarg_prms,
 681                              struct mlx5_hca_attr *att)
 682 {
 683         const char **params = (const char *[]){
 684                 "log-block-size",
 685                 NULL,
 686         };
 687
 688         devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 689         if (mkvlist == NULL)
 690                 return 0;
 691         if (mlx5_kvargs_process(mkvlist, params,
 692                                 mlx5_compress_args_check_handler,
 693                                 devarg_prms) != 0) {
 694                 DRV_LOG(ERR, "Devargs handler function Failed.");
 695                 rte_errno = EINVAL;
 696                 return -1;
 697         }
 698         if (devarg_prms->log_block_sz > MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX ||
 699             devarg_prms->log_block_sz < att->compress_min_block_size) {
 700                 DRV_LOG(WARNING, "Log block size provided is out of range("
 701                         "%u); default it to %u.",
 702                         devarg_prms->log_block_sz,
 703                         MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX);
 704                 devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 705         }
 706         return 0;
 707 }
 708
 709 static int
 710 mlx5_compress_dev_probe(struct mlx5_common_device *cdev,
 711                         struct mlx5_kvargs_ctrl *mkvlist)
 712 {
 713         struct rte_compressdev *compressdev;
 714         struct mlx5_compress_priv *priv;
 715         struct mlx5_hca_attr *attr = &cdev->config.hca_attr;
 716         struct mlx5_compress_devarg_params devarg_prms = {0};
 717         struct rte_compressdev_pmd_init_params init_params = {
 718                 .name = "",
 719                 .socket_id = cdev->dev->numa_node,
 720         };
 721         const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);
 722
 723         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 724                 DRV_LOG(ERR, "Non-primary process type is not supported.");
 725                 rte_errno = ENOTSUP;
 726                 return -rte_errno;
 727         }
 728         if (!attr->mmo_decompress_qp_en && !attr->mmo_decompress_sq_en
 729                 && !attr->mmo_compress_qp_en && !attr->mmo_compress_sq_en
 730                 && !attr->mmo_dma_qp_en && !attr->mmo_dma_sq_en) {
 731                 DRV_LOG(ERR, "Not enough capabilities to support compress operations, maybe old FW/OFED version?");
 732                 rte_errno = ENOTSUP;
 733                 return -ENOTSUP;
 734         }
 735         mlx5_compress_handle_devargs(mkvlist, &devarg_prms, attr);
 736         compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev,
 737                                                  sizeof(*priv), &init_params);
 738         if (compressdev == NULL) {
 739                 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name);
 740                 return -ENODEV;
 741         }
 742         DRV_LOG(INFO,
 743                 "Compress device %s was created successfully.", ibdev_name);
 744         compressdev->dev_ops = &mlx5_compress_ops;
 745         compressdev->dequeue_burst = mlx5_compress_dequeue_burst;
 746         compressdev->enqueue_burst = mlx5_compress_enqueue_burst;
 747         compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 748         priv = compressdev->data->dev_private;
 749         priv->log_block_sz = devarg_prms.log_block_sz;
 750         priv->mmo_decomp_sq = attr->mmo_decompress_sq_en;
 751         priv->mmo_decomp_qp = attr->mmo_decompress_qp_en;
 752         priv->mmo_comp_sq = attr->mmo_compress_sq_en;
 753         priv->mmo_comp_qp = attr->mmo_compress_qp_en;
 754         priv->mmo_dma_sq = attr->mmo_dma_sq_en;
 755         priv->mmo_dma_qp = attr->mmo_dma_qp_en;
 756         priv->cdev = cdev;
 757         priv->compressdev = compressdev;
 758         priv->min_block_size = attr->compress_min_block_size;
 759         if (mlx5_devx_uar_prepare(cdev, &priv->uar) != 0) {
 760                 rte_compressdev_pmd_destroy(priv->compressdev);
 761                 return -1;
 762         }
 763         pthread_mutex_lock(&priv_list_lock);
 764         TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
 765         pthread_mutex_unlock(&priv_list_lock);
 766         return 0;
 767 }
 768
 769 static int
 770 mlx5_compress_dev_remove(struct mlx5_common_device *cdev)
 771 {
 772         struct mlx5_compress_priv *priv = NULL;
 773
 774         pthread_mutex_lock(&priv_list_lock);
 775         TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 776                 if (priv->compressdev->device == cdev->dev)
 777                         break;
 778         if (priv)
 779                 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
 780         pthread_mutex_unlock(&priv_list_lock);
 781         if (priv) {
 782                 mlx5_devx_uar_release(&priv->uar);
 783                 rte_compressdev_pmd_destroy(priv->compressdev);
 784         }
 785         return 0;
 786 }
 787
 788 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
 789         {
 790                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 791                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
 792         },
 793         {
 794                 .vendor_id = 0
 795         }
 796 };
 797
 798 static struct mlx5_class_driver mlx5_compress_driver = {
 799         .drv_class = MLX5_CLASS_COMPRESS,
 800         .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
 801         .id_table = mlx5_compress_pci_id_map,
 802         .probe = mlx5_compress_dev_probe,
 803         .remove = mlx5_compress_dev_remove,
 804 };
 805
 806 RTE_INIT(rte_mlx5_compress_init)
 807 {
 808         mlx5_common_init();
 809         if (mlx5_glue != NULL)
 810                 mlx5_class_driver_register(&mlx5_compress_driver);
 811 }
 812
 813 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE)
 814 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
 815 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
 816 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");