1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2021 Mellanox Technologies, Ltd
5 #include <rte_malloc.h>
9 #include <rte_spinlock.h>
11 #include <rte_compressdev.h>
12 #include <rte_compressdev_pmd.h>
14 #include <mlx5_glue.h>
15 #include <mlx5_common.h>
16 #include <mlx5_common_pci.h>
17 #include <mlx5_devx_cmds.h>
18 #include <mlx5_common_os.h>
19 #include <mlx5_common_devx.h>
20 #include <mlx5_common_mr.h>
23 #include "mlx5_compress_utils.h"
25 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
26 #define MLX5_COMPRESS_LOG_NAME pmd.compress.mlx5
27 #define MLX5_COMPRESS_MAX_QPS 1024
28 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
30 struct mlx5_compress_xform {
31 LIST_ENTRY(mlx5_compress_xform) next;
32 enum rte_comp_xform_type type;
33 enum rte_comp_checksum_type csum_type;
35 uint32_t gga_ctrl1; /* BE. */
38 struct mlx5_compress_priv {
39 TAILQ_ENTRY(mlx5_compress_priv) next;
40 struct ibv_context *ctx; /* Device context. */
41 struct rte_pci_device *pci_dev;
42 struct rte_compressdev *cdev;
44 uint32_t pdn; /* Protection Domain number. */
45 uint8_t min_block_size;
46 uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */
47 /* Minimum huffman block size supported by the device. */
49 struct rte_compressdev_config dev_config;
50 LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
51 rte_spinlock_t xform_sl;
52 struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
53 volatile uint64_t *uar_addr;
55 rte_spinlock_t uar32_sl;
56 #endif /* RTE_ARCH_64 */
59 struct mlx5_compress_qp {
64 struct mlx5_mr_ctrl mr_ctrl;
66 struct mlx5_devx_cq cq;
67 struct mlx5_devx_sq sq;
68 struct mlx5_pmd_mr opaque_mr;
69 struct rte_comp_op **ops;
70 struct mlx5_compress_priv *priv;
71 struct rte_compressdev_stats stats;
74 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
75 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
76 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
78 int mlx5_compress_logtype;
80 static const struct rte_compressdev_capabilities mlx5_caps[] = {
82 .algo = RTE_COMP_ALGO_NULL,
83 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
84 RTE_COMP_FF_CRC32_CHECKSUM |
85 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
86 RTE_COMP_FF_SHAREABLE_PRIV_XFORM,
89 .algo = RTE_COMP_ALGO_DEFLATE,
90 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
91 RTE_COMP_FF_CRC32_CHECKSUM |
92 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
93 RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
94 RTE_COMP_FF_HUFFMAN_FIXED |
95 RTE_COMP_FF_HUFFMAN_DYNAMIC,
96 .window_size = {.min = 10, .max = 15, .increment = 1},
99 .algo = RTE_COMP_ALGO_LIST_END,
104 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
105 struct rte_compressdev_info *info)
109 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
110 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
111 info->capabilities = mlx5_caps;
116 mlx5_compress_dev_configure(struct rte_compressdev *dev,
117 struct rte_compressdev_config *config)
119 struct mlx5_compress_priv *priv;
121 if (dev == NULL || config == NULL)
123 priv = dev->data->dev_private;
124 priv->dev_config = *config;
129 mlx5_compress_dev_close(struct rte_compressdev *dev)
136 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
138 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
140 if (qp->sq.sq != NULL)
141 mlx5_devx_sq_destroy(&qp->sq);
142 if (qp->cq.cq != NULL)
143 mlx5_devx_cq_destroy(&qp->cq);
144 if (qp->opaque_mr.obj != NULL) {
145 void *opaq = qp->opaque_mr.addr;
147 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
151 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
153 dev->data->queue_pairs[qp_id] = NULL;
158 mlx5_compress_init_sq(struct mlx5_compress_qp *qp)
160 volatile struct mlx5_gga_wqe *restrict wqe =
161 (volatile struct mlx5_gga_wqe *)qp->sq.wqes;
162 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
163 const uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u);
164 const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
165 MLX5_COMP_MODE_OFFSET);
166 const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
169 /* All the next fields state should stay constant. */
170 for (i = 0; i < qp->entries_n; ++i, ++wqe) {
173 wqe->opaque_lkey = opaq_lkey;
174 wqe->opaque_vaddr = rte_cpu_to_be_64
175 ((uint64_t)(uintptr_t)&opaq[i]);
180 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
181 uint32_t max_inflight_ops, int socket_id)
183 struct mlx5_compress_priv *priv = dev->data->dev_private;
184 struct mlx5_compress_qp *qp;
185 struct mlx5_devx_cq_attr cq_attr = {
186 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
188 struct mlx5_devx_create_sq_attr sq_attr = {
190 .wq_attr = (struct mlx5_devx_wq_attr){
192 .uar_page = mlx5_os_get_devx_uar_page_id(priv->uar),
195 struct mlx5_devx_modify_sq_attr modify_attr = {
196 .state = MLX5_SQC_STATE_RDY,
198 uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
199 uint32_t alloc_size = sizeof(*qp);
203 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
204 alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
205 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
208 DRV_LOG(ERR, "Failed to allocate qp memory.");
212 dev->data->queue_pairs[qp_id] = qp;
213 opaq_buf = rte_calloc(__func__, 1u << log_ops_n,
214 sizeof(struct mlx5_gga_compress_opaque),
215 sizeof(struct mlx5_gga_compress_opaque));
216 if (opaq_buf == NULL) {
217 DRV_LOG(ERR, "Failed to allocate opaque memory.");
221 if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,
222 priv->dev_config.socket_id)) {
223 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
228 qp->entries_n = 1 << log_ops_n;
229 qp->socket_id = socket_id;
232 qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
233 RTE_CACHE_LINE_SIZE);
234 if (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n *
235 sizeof(struct mlx5_gga_compress_opaque),
236 &qp->opaque_mr) != 0) {
238 DRV_LOG(ERR, "Failed to register opaque MR.");
242 ret = mlx5_devx_cq_create(priv->ctx, &qp->cq, log_ops_n, &cq_attr,
245 DRV_LOG(ERR, "Failed to create CQ.");
248 sq_attr.cqn = qp->cq.cq->id;
249 sq_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format);
250 ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,
253 DRV_LOG(ERR, "Failed to create SQ.");
256 mlx5_compress_init_sq(qp);
257 ret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr);
259 DRV_LOG(ERR, "Can't change SQ state to ready.");
262 DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u",
263 (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n);
266 mlx5_compress_qp_release(dev, qp_id);
271 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
273 struct mlx5_compress_priv *priv = dev->data->dev_private;
275 rte_spinlock_lock(&priv->xform_sl);
276 LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
277 rte_spinlock_unlock(&priv->xform_sl);
283 mlx5_compress_xform_create(struct rte_compressdev *dev,
284 const struct rte_comp_xform *xform,
285 void **private_xform)
287 struct mlx5_compress_priv *priv = dev->data->dev_private;
288 struct mlx5_compress_xform *xfrm;
291 if (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==
292 RTE_COMP_LEVEL_NONE) {
293 DRV_LOG(ERR, "Non-compressed block is not supported.");
296 if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=
297 RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&
298 xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {
299 DRV_LOG(ERR, "SHA is not supported.");
302 xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
303 priv->dev_config.socket_id);
306 xfrm->opcode = MLX5_OPCODE_MMO;
307 xfrm->type = xform->type;
308 switch (xform->type) {
309 case RTE_COMP_COMPRESS:
310 switch (xform->compress.algo) {
311 case RTE_COMP_ALGO_NULL:
312 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
313 WQE_CSEG_OPC_MOD_OFFSET;
315 case RTE_COMP_ALGO_DEFLATE:
316 size = 1 << xform->compress.window_size;
317 size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
318 xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
319 MLX5_COMP_MAX_WIN_SIZE_CONF) <<
320 WQE_GGA_COMP_WIN_SIZE_OFFSET;
321 if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
322 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
324 size = priv->min_block_size - 1 +
325 xform->compress.level;
326 xfrm->gga_ctrl1 += RTE_MIN(size,
327 MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
328 WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
329 xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
330 WQE_CSEG_OPC_MOD_OFFSET;
331 size = xform->compress.deflate.huffman ==
332 RTE_COMP_HUFFMAN_DYNAMIC ?
333 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
334 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
335 xfrm->gga_ctrl1 += size <<
336 WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
341 xfrm->csum_type = xform->compress.chksum;
343 case RTE_COMP_DECOMPRESS:
344 switch (xform->decompress.algo) {
345 case RTE_COMP_ALGO_NULL:
346 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
347 WQE_CSEG_OPC_MOD_OFFSET;
349 case RTE_COMP_ALGO_DEFLATE:
350 xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
351 WQE_CSEG_OPC_MOD_OFFSET;
356 xfrm->csum_type = xform->decompress.chksum;
359 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
362 DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
363 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
364 xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
365 rte_spinlock_lock(&priv->xform_sl);
366 LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
367 rte_spinlock_unlock(&priv->xform_sl);
368 *private_xform = xfrm;
376 mlx5_compress_dev_stop(struct rte_compressdev *dev)
382 mlx5_compress_dev_start(struct rte_compressdev *dev)
389 mlx5_compress_stats_get(struct rte_compressdev *dev,
390 struct rte_compressdev_stats *stats)
394 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
395 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
397 stats->enqueued_count += qp->stats.enqueued_count;
398 stats->dequeued_count += qp->stats.dequeued_count;
399 stats->enqueue_err_count += qp->stats.enqueue_err_count;
400 stats->dequeue_err_count += qp->stats.dequeue_err_count;
405 mlx5_compress_stats_reset(struct rte_compressdev *dev)
409 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
410 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
412 memset(&qp->stats, 0, sizeof(qp->stats));
416 static struct rte_compressdev_ops mlx5_compress_ops = {
417 .dev_configure = mlx5_compress_dev_configure,
418 .dev_start = mlx5_compress_dev_start,
419 .dev_stop = mlx5_compress_dev_stop,
420 .dev_close = mlx5_compress_dev_close,
421 .dev_infos_get = mlx5_compress_dev_info_get,
422 .stats_get = mlx5_compress_stats_get,
423 .stats_reset = mlx5_compress_stats_reset,
424 .queue_pair_setup = mlx5_compress_qp_setup,
425 .queue_pair_release = mlx5_compress_qp_release,
426 .private_xform_create = mlx5_compress_xform_create,
427 .private_xform_free = mlx5_compress_xform_free,
428 .stream_create = NULL,
432 static __rte_always_inline uint32_t
433 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
434 volatile struct mlx5_wqe_dseg *restrict dseg,
435 struct rte_mbuf *restrict mbuf,
436 uint32_t offset, uint32_t len)
438 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
440 dseg->bcount = rte_cpu_to_be_32(len);
441 dseg->lkey = mlx5_mr_addr2mr_bh(qp->priv->pd, 0, &qp->priv->mr_scache,
443 !!(mbuf->ol_flags & EXT_ATTACHED_MBUF));
444 dseg->pbuf = rte_cpu_to_be_64(addr);
449 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
450 * 64bit architectures.
452 static __rte_always_inline void
453 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv)
456 *priv->uar_addr = val;
457 #else /* !RTE_ARCH_64 */
458 rte_spinlock_lock(&priv->uar32_sl);
459 *(volatile uint32_t *)priv->uar_addr = val;
461 *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32;
462 rte_spinlock_unlock(&priv->uar32_sl);
467 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
470 struct mlx5_compress_qp *qp = queue_pair;
471 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
473 struct mlx5_compress_xform *xform;
474 struct rte_comp_op *op;
475 uint16_t mask = qp->entries_n - 1;
476 uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
484 if (unlikely(remain == 0))
489 rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
491 xform = op->private_xform;
493 * Check operation arguments and error cases:
494 * - Operation type must be state-less.
495 * - Compress operation flush flag must be FULL or FINAL.
496 * - Source and destination buffers must be mapped internally.
498 invalid = op->op_type != RTE_COMP_OP_STATELESS ||
499 (xform->type == RTE_COMP_COMPRESS &&
500 op->flush_flag < RTE_COMP_FLUSH_FULL);
501 if (unlikely(invalid ||
502 (mlx5_compress_dseg_set(qp, &wqe->gather,
507 (mlx5_compress_dseg_set(qp, &wqe->scatter,
510 rte_pktmbuf_pkt_len(op->m_dst) -
513 op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
514 RTE_COMP_OP_STATUS_ERROR;
516 if (unlikely(nb_ops == 0))
520 wqe->gga_ctrl1 = xform->gga_ctrl1;
521 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
525 qp->stats.enqueued_count += nb_ops;
527 qp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
529 mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv);
535 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
536 volatile uint32_t *opaq)
540 DRV_LOG(ERR, "Error cqe:");
541 for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
542 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
543 cqe[i + 2], cqe[i + 3]);
544 DRV_LOG(ERR, "\nError wqe:");
545 for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
546 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
547 wqe[i + 2], wqe[i + 3]);
548 DRV_LOG(ERR, "\nError opaq:");
549 for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
550 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
551 opaq[i + 2], opaq[i + 3]);
555 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
556 struct rte_comp_op *op)
558 const uint32_t idx = qp->ci & (qp->entries_n - 1);
559 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
561 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
563 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
565 op->status = RTE_COMP_OP_STATUS_ERROR;
568 op->output_chksum = 0;
569 op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
570 ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
571 mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
572 (volatile uint32_t *)&wqes[idx],
573 (volatile uint32_t *)&opaq[idx]);
574 qp->stats.dequeue_err_count++;
578 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
581 struct mlx5_compress_qp *qp = queue_pair;
582 volatile struct mlx5_compress_xform *restrict xform;
583 volatile struct mlx5_cqe *restrict cqe;
584 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
585 struct rte_comp_op *restrict op;
586 const unsigned int cq_size = qp->entries_n;
587 const unsigned int mask = cq_size - 1;
589 uint32_t next_idx = qp->ci & mask;
590 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
594 if (unlikely(max == 0))
598 next_idx = (qp->ci + 1) & mask;
599 rte_prefetch0(&qp->cq.cqes[next_idx]);
600 rte_prefetch0(qp->ops[next_idx]);
602 cqe = &qp->cq.cqes[idx];
603 ret = check_cqe(cqe, cq_size, qp->ci);
605 * Be sure owner read is done before any other cookie field or
609 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
610 if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
612 mlx5_compress_cqe_err_handle(qp, op);
614 xform = op->private_xform;
615 op->status = RTE_COMP_OP_STATUS_SUCCESS;
616 op->consumed = op->src.length;
617 op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
618 MLX5_ASSERT(cqe->byte_cnt ==
619 opaq[idx].scattered_length);
620 switch (xform->csum_type) {
621 case RTE_COMP_CHECKSUM_CRC32:
622 op->output_chksum = (uint64_t)rte_be_to_cpu_32
625 case RTE_COMP_CHECKSUM_ADLER32:
626 op->output_chksum = (uint64_t)rte_be_to_cpu_32
627 (opaq[idx].adler32) << 32;
629 case RTE_COMP_CHECKSUM_CRC32_ADLER32:
630 op->output_chksum = (uint64_t)rte_be_to_cpu_32
632 ((uint64_t)rte_be_to_cpu_32
633 (opaq[idx].adler32) << 32);
642 if (likely(i != 0)) {
644 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
645 qp->stats.dequeued_count += i;
650 static struct ibv_device *
651 mlx5_compress_get_ib_device_match(struct rte_pci_addr *addr)
654 struct ibv_device **ibv_list = mlx5_glue->get_device_list(&n);
655 struct ibv_device *ibv_match = NULL;
657 if (ibv_list == NULL) {
662 struct rte_pci_addr paddr;
664 DRV_LOG(DEBUG, "Checking device \"%s\"..", ibv_list[n]->name);
665 if (mlx5_dev_to_pci_addr(ibv_list[n]->ibdev_path, &paddr) != 0)
667 if (rte_pci_addr_cmp(addr, &paddr) != 0)
669 ibv_match = ibv_list[n];
672 if (ibv_match == NULL)
674 mlx5_glue->free_device_list(ibv_list);
679 mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv)
681 if (priv->pd != NULL) {
682 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
685 if (priv->uar != NULL) {
686 mlx5_glue->devx_free_uar(priv->uar);
692 mlx5_compress_pd_create(struct mlx5_compress_priv *priv)
694 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
695 struct mlx5dv_obj obj;
696 struct mlx5dv_pd pd_info;
699 priv->pd = mlx5_glue->alloc_pd(priv->ctx);
700 if (priv->pd == NULL) {
701 DRV_LOG(ERR, "Failed to allocate PD.");
702 return errno ? -errno : -ENOMEM;
704 obj.pd.in = priv->pd;
705 obj.pd.out = &pd_info;
706 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
708 DRV_LOG(ERR, "Fail to get PD object info.");
709 mlx5_glue->dealloc_pd(priv->pd);
713 priv->pdn = pd_info.pdn;
717 DRV_LOG(ERR, "Cannot get pdn - no DV support.");
719 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
723 mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv)
725 if (mlx5_compress_pd_create(priv) != 0)
727 priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
728 if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
731 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
732 DRV_LOG(ERR, "Failed to allocate UAR.");
735 priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
736 MLX5_ASSERT(priv->uar_addr);
738 rte_spinlock_init(&priv->uar32_sl);
739 #endif /* RTE_ARCH_64 */
744 * DPDK callback to register a PCI device.
746 * This function spawns compress device out of a given PCI device.
749 * PCI driver structure (mlx5_compress_driver).
751 * PCI device information.
754 * 0 on success, 1 to skip this driver, a negative errno value otherwise
755 * and rte_errno is set.
758 mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv,
759 struct rte_pci_device *pci_dev)
761 struct ibv_device *ibv;
762 struct rte_compressdev *cdev;
763 struct ibv_context *ctx;
764 struct mlx5_compress_priv *priv;
765 struct mlx5_hca_attr att = { 0 };
766 struct rte_compressdev_pmd_init_params init_params = {
768 .socket_id = pci_dev->device.numa_node,
771 RTE_SET_USED(pci_drv);
772 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
773 DRV_LOG(ERR, "Non-primary process type is not supported.");
777 ibv = mlx5_compress_get_ib_device_match(&pci_dev->addr);
779 DRV_LOG(ERR, "No matching IB device for PCI slot "
780 PCI_PRI_FMT ".", pci_dev->addr.domain,
781 pci_dev->addr.bus, pci_dev->addr.devid,
782 pci_dev->addr.function);
785 DRV_LOG(INFO, "PCI information matches for device \"%s\".", ibv->name);
786 ctx = mlx5_glue->dv_open_device(ibv);
788 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name);
792 if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 ||
793 att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 ||
794 att.mmo_dma_en == 0) {
795 DRV_LOG(ERR, "Not enough capabilities to support compress "
796 "operations, maybe old FW/OFED version?");
797 claim_zero(mlx5_glue->close_device(ctx));
801 cdev = rte_compressdev_pmd_create(ibv->name, &pci_dev->device,
802 sizeof(*priv), &init_params);
804 DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name);
805 claim_zero(mlx5_glue->close_device(ctx));
809 "Compress device %s was created successfully.", ibv->name);
810 cdev->dev_ops = &mlx5_compress_ops;
811 cdev->dequeue_burst = mlx5_compress_dequeue_burst;
812 cdev->enqueue_burst = mlx5_compress_enqueue_burst;
813 cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
814 priv = cdev->data->dev_private;
816 priv->pci_dev = pci_dev;
818 priv->min_block_size = att.compress_min_block_size;
819 priv->sq_ts_format = att.sq_ts_format;
820 if (mlx5_compress_hw_global_prepare(priv) != 0) {
821 rte_compressdev_pmd_destroy(priv->cdev);
822 claim_zero(mlx5_glue->close_device(priv->ctx));
825 if (mlx5_mr_btree_init(&priv->mr_scache.cache,
826 MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {
827 DRV_LOG(ERR, "Failed to allocate shared cache MR memory.");
828 mlx5_compress_hw_global_release(priv);
829 rte_compressdev_pmd_destroy(priv->cdev);
830 claim_zero(mlx5_glue->close_device(priv->ctx));
834 priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;
835 priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;
836 pthread_mutex_lock(&priv_list_lock);
837 TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
838 pthread_mutex_unlock(&priv_list_lock);
843 * DPDK callback to remove a PCI device.
845 * This function removes all compress devices belong to a given PCI device.
848 * Pointer to the PCI device.
851 * 0 on success, the function cannot fail.
854 mlx5_compress_pci_remove(struct rte_pci_device *pdev)
856 struct mlx5_compress_priv *priv = NULL;
858 pthread_mutex_lock(&priv_list_lock);
859 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
860 if (rte_pci_addr_cmp(&priv->pci_dev->addr, &pdev->addr) != 0)
863 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
864 pthread_mutex_unlock(&priv_list_lock);
866 mlx5_mr_release_cache(&priv->mr_scache);
867 mlx5_compress_hw_global_release(priv);
868 rte_compressdev_pmd_destroy(priv->cdev);
869 claim_zero(mlx5_glue->close_device(priv->ctx));
874 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
876 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
877 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
884 static struct mlx5_pci_driver mlx5_compress_driver = {
885 .driver_class = MLX5_CLASS_COMPRESS,
888 .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
890 .id_table = mlx5_compress_pci_id_map,
891 .probe = mlx5_compress_pci_probe,
892 .remove = mlx5_compress_pci_remove,
897 RTE_INIT(rte_mlx5_compress_init)
900 if (mlx5_glue != NULL)
901 mlx5_pci_driver_register(&mlx5_compress_driver);
904 RTE_LOG_REGISTER(mlx5_compress_logtype, MLX5_COMPRESS_LOG_NAME, NOTICE)
905 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
906 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
907 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");