1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2021 Mellanox Technologies, Ltd
5 #include <rte_malloc.h>
8 #include <rte_bus_pci.h>
9 #include <rte_spinlock.h>
11 #include <rte_compressdev.h>
12 #include <rte_compressdev_pmd.h>
14 #include <mlx5_glue.h>
15 #include <mlx5_common.h>
16 #include <mlx5_devx_cmds.h>
17 #include <mlx5_common_os.h>
18 #include <mlx5_common_devx.h>
19 #include <mlx5_common_mr.h>
22 #include "mlx5_compress_utils.h"
24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
25 #define MLX5_COMPRESS_MAX_QPS 1024
26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
28 struct mlx5_compress_xform {
29 LIST_ENTRY(mlx5_compress_xform) next;
30 enum rte_comp_xform_type type;
31 enum rte_comp_checksum_type csum_type;
33 uint32_t gga_ctrl1; /* BE. */
36 struct mlx5_compress_priv {
37 TAILQ_ENTRY(mlx5_compress_priv) next;
38 struct rte_compressdev *compressdev;
39 struct mlx5_common_device *cdev; /* Backend mlx5 device. */
41 uint8_t min_block_size;
42 /* Minimum huffman block size supported by the device. */
43 struct rte_compressdev_config dev_config;
44 LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
45 rte_spinlock_t xform_sl;
46 volatile uint64_t *uar_addr;
48 uint32_t mmo_decomp_sq:1;
49 uint32_t mmo_decomp_qp:1;
50 uint32_t mmo_comp_sq:1;
51 uint32_t mmo_comp_qp:1;
52 uint32_t mmo_dma_sq:1;
53 uint32_t mmo_dma_qp:1;
55 rte_spinlock_t uar32_sl;
56 #endif /* RTE_ARCH_64 */
59 struct mlx5_compress_qp {
64 struct mlx5_mr_ctrl mr_ctrl;
66 struct mlx5_devx_cq cq;
67 struct mlx5_devx_qp qp;
68 struct mlx5_pmd_mr opaque_mr;
69 struct rte_comp_op **ops;
70 struct mlx5_compress_priv *priv;
71 struct rte_compressdev_stats stats;
74 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
75 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
76 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
78 int mlx5_compress_logtype;
80 static const struct rte_compressdev_capabilities mlx5_caps[] = {
82 .algo = RTE_COMP_ALGO_NULL,
83 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
84 RTE_COMP_FF_CRC32_CHECKSUM |
85 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
86 RTE_COMP_FF_SHAREABLE_PRIV_XFORM,
89 .algo = RTE_COMP_ALGO_DEFLATE,
90 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
91 RTE_COMP_FF_CRC32_CHECKSUM |
92 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
93 RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
94 RTE_COMP_FF_HUFFMAN_FIXED |
95 RTE_COMP_FF_HUFFMAN_DYNAMIC,
96 .window_size = {.min = 10, .max = 15, .increment = 1},
99 .algo = RTE_COMP_ALGO_LIST_END,
104 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
105 struct rte_compressdev_info *info)
109 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
110 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
111 info->capabilities = mlx5_caps;
116 mlx5_compress_dev_configure(struct rte_compressdev *dev,
117 struct rte_compressdev_config *config)
119 struct mlx5_compress_priv *priv;
121 if (dev == NULL || config == NULL)
123 priv = dev->data->dev_private;
124 priv->dev_config = *config;
129 mlx5_compress_dev_close(struct rte_compressdev *dev)
136 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
138 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
140 if (qp->qp.qp != NULL)
141 mlx5_devx_qp_destroy(&qp->qp);
142 if (qp->cq.cq != NULL)
143 mlx5_devx_cq_destroy(&qp->cq);
144 if (qp->opaque_mr.obj != NULL) {
145 void *opaq = qp->opaque_mr.addr;
147 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
151 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
153 dev->data->queue_pairs[qp_id] = NULL;
158 mlx5_compress_init_qp(struct mlx5_compress_qp *qp)
160 volatile struct mlx5_gga_wqe *restrict wqe =
161 (volatile struct mlx5_gga_wqe *)qp->qp.wqes;
162 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
163 const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u);
164 const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
165 MLX5_COMP_MODE_OFFSET);
166 const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
169 /* All the next fields state should stay constant. */
170 for (i = 0; i < qp->entries_n; ++i, ++wqe) {
173 wqe->opaque_lkey = opaq_lkey;
174 wqe->opaque_vaddr = rte_cpu_to_be_64
175 ((uint64_t)(uintptr_t)&opaq[i]);
180 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
181 uint32_t max_inflight_ops, int socket_id)
183 struct mlx5_compress_priv *priv = dev->data->dev_private;
184 struct mlx5_compress_qp *qp;
185 struct mlx5_devx_cq_attr cq_attr = {
186 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
188 struct mlx5_devx_qp_attr qp_attr = {
189 .pd = priv->cdev->pdn,
190 .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar),
193 uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
194 uint32_t alloc_size = sizeof(*qp);
198 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
199 alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
200 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
203 DRV_LOG(ERR, "Failed to allocate qp memory.");
207 dev->data->queue_pairs[qp_id] = qp;
208 if (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->cdev->mr_scache.dev_gen,
209 priv->dev_config.socket_id)) {
210 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
215 opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n,
216 sizeof(struct mlx5_gga_compress_opaque),
217 sizeof(struct mlx5_gga_compress_opaque));
218 if (opaq_buf == NULL) {
219 DRV_LOG(ERR, "Failed to allocate opaque memory.");
223 qp->entries_n = 1 << log_ops_n;
224 qp->socket_id = socket_id;
227 qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
228 RTE_CACHE_LINE_SIZE);
229 if (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n *
230 sizeof(struct mlx5_gga_compress_opaque),
231 &qp->opaque_mr) != 0) {
233 DRV_LOG(ERR, "Failed to register opaque MR.");
237 ret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr,
240 DRV_LOG(ERR, "Failed to create CQ.");
243 qp_attr.cqn = qp->cq.cq->id;
245 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
247 qp_attr.sq_size = RTE_BIT32(log_ops_n);
248 qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp
250 ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, log_ops_n, &qp_attr,
253 DRV_LOG(ERR, "Failed to create QP.");
256 mlx5_compress_init_qp(qp);
257 ret = mlx5_devx_qp2rts(&qp->qp, 0);
260 DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u",
261 (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n);
264 mlx5_compress_qp_release(dev, qp_id);
269 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
271 struct mlx5_compress_priv *priv = dev->data->dev_private;
273 rte_spinlock_lock(&priv->xform_sl);
274 LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
275 rte_spinlock_unlock(&priv->xform_sl);
281 mlx5_compress_xform_create(struct rte_compressdev *dev,
282 const struct rte_comp_xform *xform,
283 void **private_xform)
285 struct mlx5_compress_priv *priv = dev->data->dev_private;
286 struct mlx5_compress_xform *xfrm;
289 if (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==
290 RTE_COMP_LEVEL_NONE) {
291 DRV_LOG(ERR, "Non-compressed block is not supported.");
294 if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=
295 RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&
296 xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {
297 DRV_LOG(ERR, "SHA is not supported.");
300 xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
301 priv->dev_config.socket_id);
304 xfrm->opcode = MLX5_OPCODE_MMO;
305 xfrm->type = xform->type;
306 switch (xform->type) {
307 case RTE_COMP_COMPRESS:
308 switch (xform->compress.algo) {
309 case RTE_COMP_ALGO_NULL:
310 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
311 WQE_CSEG_OPC_MOD_OFFSET;
313 case RTE_COMP_ALGO_DEFLATE:
314 size = 1 << xform->compress.window_size;
315 size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
316 xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
317 MLX5_COMP_MAX_WIN_SIZE_CONF) <<
318 WQE_GGA_COMP_WIN_SIZE_OFFSET;
319 switch (xform->compress.level) {
320 case RTE_COMP_LEVEL_PMD_DEFAULT:
321 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
323 case RTE_COMP_LEVEL_MAX:
324 size = priv->min_block_size;
327 size = RTE_MAX(MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX
328 + 1 - xform->compress.level,
329 priv->min_block_size);
331 xfrm->gga_ctrl1 += RTE_MIN(size,
332 MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
333 WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
334 xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
335 WQE_CSEG_OPC_MOD_OFFSET;
336 size = xform->compress.deflate.huffman ==
337 RTE_COMP_HUFFMAN_DYNAMIC ?
338 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
339 MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
340 xfrm->gga_ctrl1 += size <<
341 WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
346 xfrm->csum_type = xform->compress.chksum;
348 case RTE_COMP_DECOMPRESS:
349 switch (xform->decompress.algo) {
350 case RTE_COMP_ALGO_NULL:
351 xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
352 WQE_CSEG_OPC_MOD_OFFSET;
354 case RTE_COMP_ALGO_DEFLATE:
355 xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
356 WQE_CSEG_OPC_MOD_OFFSET;
361 xfrm->csum_type = xform->decompress.chksum;
364 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
367 DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
368 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
369 xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
370 rte_spinlock_lock(&priv->xform_sl);
371 LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
372 rte_spinlock_unlock(&priv->xform_sl);
373 *private_xform = xfrm;
381 mlx5_compress_dev_stop(struct rte_compressdev *dev)
387 mlx5_compress_dev_start(struct rte_compressdev *dev)
394 mlx5_compress_stats_get(struct rte_compressdev *dev,
395 struct rte_compressdev_stats *stats)
399 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
400 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
402 stats->enqueued_count += qp->stats.enqueued_count;
403 stats->dequeued_count += qp->stats.dequeued_count;
404 stats->enqueue_err_count += qp->stats.enqueue_err_count;
405 stats->dequeue_err_count += qp->stats.dequeue_err_count;
410 mlx5_compress_stats_reset(struct rte_compressdev *dev)
414 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
415 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
417 memset(&qp->stats, 0, sizeof(qp->stats));
421 static struct rte_compressdev_ops mlx5_compress_ops = {
422 .dev_configure = mlx5_compress_dev_configure,
423 .dev_start = mlx5_compress_dev_start,
424 .dev_stop = mlx5_compress_dev_stop,
425 .dev_close = mlx5_compress_dev_close,
426 .dev_infos_get = mlx5_compress_dev_info_get,
427 .stats_get = mlx5_compress_stats_get,
428 .stats_reset = mlx5_compress_stats_reset,
429 .queue_pair_setup = mlx5_compress_qp_setup,
430 .queue_pair_release = mlx5_compress_qp_release,
431 .private_xform_create = mlx5_compress_xform_create,
432 .private_xform_free = mlx5_compress_xform_free,
433 .stream_create = NULL,
437 static __rte_always_inline uint32_t
438 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
439 volatile struct mlx5_wqe_dseg *restrict dseg,
440 struct rte_mbuf *restrict mbuf,
441 uint32_t offset, uint32_t len)
443 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
445 dseg->bcount = rte_cpu_to_be_32(len);
446 dseg->lkey = mlx5_mr_mb2mr(qp->priv->cdev, 0, &qp->mr_ctrl, mbuf);
447 dseg->pbuf = rte_cpu_to_be_64(addr);
452 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
453 * 64bit architectures.
455 static __rte_always_inline void
456 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv)
459 *priv->uar_addr = val;
460 #else /* !RTE_ARCH_64 */
461 rte_spinlock_lock(&priv->uar32_sl);
462 *(volatile uint32_t *)priv->uar_addr = val;
464 *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32;
465 rte_spinlock_unlock(&priv->uar32_sl);
470 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
473 struct mlx5_compress_qp *qp = queue_pair;
474 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
476 struct mlx5_compress_xform *xform;
477 struct rte_comp_op *op;
478 uint16_t mask = qp->entries_n - 1;
479 uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
487 if (unlikely(remain == 0))
492 rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
494 xform = op->private_xform;
496 * Check operation arguments and error cases:
497 * - Operation type must be state-less.
498 * - Compress operation flush flag must be FULL or FINAL.
499 * - Source and destination buffers must be mapped internally.
501 invalid = op->op_type != RTE_COMP_OP_STATELESS ||
502 (xform->type == RTE_COMP_COMPRESS &&
503 op->flush_flag < RTE_COMP_FLUSH_FULL);
504 if (unlikely(invalid ||
505 (mlx5_compress_dseg_set(qp, &wqe->gather,
510 (mlx5_compress_dseg_set(qp, &wqe->scatter,
513 rte_pktmbuf_pkt_len(op->m_dst) -
516 op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
517 RTE_COMP_OP_STATUS_ERROR;
519 if (unlikely(nb_ops == 0))
523 wqe->gga_ctrl1 = xform->gga_ctrl1;
524 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
528 qp->stats.enqueued_count += nb_ops;
530 qp->qp.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
532 mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv);
538 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
539 volatile uint32_t *opaq)
543 DRV_LOG(ERR, "Error cqe:");
544 for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
545 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
546 cqe[i + 2], cqe[i + 3]);
547 DRV_LOG(ERR, "\nError wqe:");
548 for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
549 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
550 wqe[i + 2], wqe[i + 3]);
551 DRV_LOG(ERR, "\nError opaq:");
552 for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
553 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
554 opaq[i + 2], opaq[i + 3]);
558 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
559 struct rte_comp_op *op)
561 const uint32_t idx = qp->ci & (qp->entries_n - 1);
562 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
564 volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
566 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
568 op->status = RTE_COMP_OP_STATUS_ERROR;
571 op->output_chksum = 0;
572 op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
573 ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
574 mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
575 (volatile uint32_t *)&wqes[idx],
576 (volatile uint32_t *)&opaq[idx]);
577 qp->stats.dequeue_err_count++;
581 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
584 struct mlx5_compress_qp *qp = queue_pair;
585 volatile struct mlx5_compress_xform *restrict xform;
586 volatile struct mlx5_cqe *restrict cqe;
587 volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
588 struct rte_comp_op *restrict op;
589 const unsigned int cq_size = qp->entries_n;
590 const unsigned int mask = cq_size - 1;
592 uint32_t next_idx = qp->ci & mask;
593 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
597 if (unlikely(max == 0))
601 next_idx = (qp->ci + 1) & mask;
602 rte_prefetch0(&qp->cq.cqes[next_idx]);
603 rte_prefetch0(qp->ops[next_idx]);
605 cqe = &qp->cq.cqes[idx];
606 ret = check_cqe(cqe, cq_size, qp->ci);
608 * Be sure owner read is done before any other cookie field or
612 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
613 if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
615 mlx5_compress_cqe_err_handle(qp, op);
617 xform = op->private_xform;
618 op->status = RTE_COMP_OP_STATUS_SUCCESS;
619 op->consumed = op->src.length;
620 op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
621 MLX5_ASSERT(cqe->byte_cnt ==
622 opaq[idx].scattered_length);
623 switch (xform->csum_type) {
624 case RTE_COMP_CHECKSUM_CRC32:
625 op->output_chksum = (uint64_t)rte_be_to_cpu_32
628 case RTE_COMP_CHECKSUM_ADLER32:
629 op->output_chksum = (uint64_t)rte_be_to_cpu_32
630 (opaq[idx].adler32) << 32;
632 case RTE_COMP_CHECKSUM_CRC32_ADLER32:
633 op->output_chksum = (uint64_t)rte_be_to_cpu_32
635 ((uint64_t)rte_be_to_cpu_32
636 (opaq[idx].adler32) << 32);
645 if (likely(i != 0)) {
647 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
648 qp->stats.dequeued_count += i;
654 mlx5_compress_uar_release(struct mlx5_compress_priv *priv)
656 if (priv->uar != NULL) {
657 mlx5_glue->devx_free_uar(priv->uar);
663 mlx5_compress_uar_prepare(struct mlx5_compress_priv *priv)
665 priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);
666 if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
669 DRV_LOG(ERR, "Failed to allocate UAR.");
672 priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
673 MLX5_ASSERT(priv->uar_addr);
675 rte_spinlock_init(&priv->uar32_sl);
676 #endif /* RTE_ARCH_64 */
681 mlx5_compress_dev_probe(struct mlx5_common_device *cdev)
683 struct rte_compressdev *compressdev;
684 struct mlx5_compress_priv *priv;
685 struct mlx5_hca_attr *attr = &cdev->config.hca_attr;
686 struct rte_compressdev_pmd_init_params init_params = {
688 .socket_id = cdev->dev->numa_node,
690 const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);
692 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
693 DRV_LOG(ERR, "Non-primary process type is not supported.");
697 if ((attr->mmo_compress_sq_en == 0 || attr->mmo_decompress_sq_en == 0 ||
698 attr->mmo_dma_sq_en == 0) && (attr->mmo_compress_qp_en == 0 ||
699 attr->mmo_decompress_qp_en == 0 || attr->mmo_dma_qp_en == 0)) {
700 DRV_LOG(ERR, "Not enough capabilities to support compress "
701 "operations, maybe old FW/OFED version?");
705 compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev,
706 sizeof(*priv), &init_params);
707 if (compressdev == NULL) {
708 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name);
712 "Compress device %s was created successfully.", ibdev_name);
713 compressdev->dev_ops = &mlx5_compress_ops;
714 compressdev->dequeue_burst = mlx5_compress_dequeue_burst;
715 compressdev->enqueue_burst = mlx5_compress_enqueue_burst;
716 compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
717 priv = compressdev->data->dev_private;
718 priv->mmo_decomp_sq = attr->mmo_decompress_sq_en;
719 priv->mmo_decomp_qp = attr->mmo_decompress_qp_en;
720 priv->mmo_comp_sq = attr->mmo_compress_sq_en;
721 priv->mmo_comp_qp = attr->mmo_compress_qp_en;
722 priv->mmo_dma_sq = attr->mmo_dma_sq_en;
723 priv->mmo_dma_qp = attr->mmo_dma_qp_en;
725 priv->compressdev = compressdev;
726 priv->min_block_size = attr->compress_min_block_size;
727 if (mlx5_compress_uar_prepare(priv) != 0) {
728 rte_compressdev_pmd_destroy(priv->compressdev);
731 pthread_mutex_lock(&priv_list_lock);
732 TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
733 pthread_mutex_unlock(&priv_list_lock);
738 mlx5_compress_dev_remove(struct mlx5_common_device *cdev)
740 struct mlx5_compress_priv *priv = NULL;
742 pthread_mutex_lock(&priv_list_lock);
743 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
744 if (priv->compressdev->device == cdev->dev)
747 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
748 pthread_mutex_unlock(&priv_list_lock);
750 mlx5_compress_uar_release(priv);
751 rte_compressdev_pmd_destroy(priv->compressdev);
756 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
758 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
759 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
766 static struct mlx5_class_driver mlx5_compress_driver = {
767 .drv_class = MLX5_CLASS_COMPRESS,
768 .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
769 .id_table = mlx5_compress_pci_id_map,
770 .probe = mlx5_compress_dev_probe,
771 .remove = mlx5_compress_dev_remove,
774 RTE_INIT(rte_mlx5_compress_init)
777 if (mlx5_glue != NULL)
778 mlx5_class_driver_register(&mlx5_compress_driver);
781 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE)
782 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
783 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
784 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");