drivers/compress/mlx5/mlx5_compress.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_log.h>
   7 #include <rte_errno.h>
   8 #include <rte_bus_pci.h>
   9 #include <rte_spinlock.h>
  10 #include <rte_comp.h>
  11 #include <rte_compressdev.h>
  12 #include <rte_compressdev_pmd.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_common.h>
  16 #include <mlx5_devx_cmds.h>
  17 #include <mlx5_common_os.h>
  18 #include <mlx5_common_devx.h>
  19 #include <mlx5_common_mr.h>
  20 #include <mlx5_prm.h>
  21
  22 #include "mlx5_compress_utils.h"
  23
  24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
  25 #define MLX5_COMPRESS_MAX_QPS 1024
  26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
  27
  28 struct mlx5_compress_xform {
  29         LIST_ENTRY(mlx5_compress_xform) next;
  30         enum rte_comp_xform_type type;
  31         enum rte_comp_checksum_type csum_type;
  32         uint32_t opcode;
  33         uint32_t gga_ctrl1; /* BE. */
  34 };
  35
  36 struct mlx5_compress_priv {
  37         TAILQ_ENTRY(mlx5_compress_priv) next;
  38         struct rte_compressdev *compressdev;
  39         struct mlx5_common_device *cdev; /* Backend mlx5 device. */
  40         void *uar;
  41         uint8_t min_block_size;
  42         uint8_t qp_ts_format; /* Whether SQ supports timestamp formats. */
  43         /* Minimum huffman block size supported by the device. */
  44         struct rte_compressdev_config dev_config;
  45         LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
  46         rte_spinlock_t xform_sl;
  47         struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
  48         volatile uint64_t *uar_addr;
  49         /* HCA caps*/
  50         uint32_t mmo_decomp_sq:1;
  51         uint32_t mmo_decomp_qp:1;
  52         uint32_t mmo_comp_sq:1;
  53         uint32_t mmo_comp_qp:1;
  54         uint32_t mmo_dma_sq:1;
  55         uint32_t mmo_dma_qp:1;
  56 #ifndef RTE_ARCH_64
  57         rte_spinlock_t uar32_sl;
  58 #endif /* RTE_ARCH_64 */
  59 };
  60
  61 struct mlx5_compress_qp {
  62         uint16_t qp_id;
  63         uint16_t entries_n;
  64         uint16_t pi;
  65         uint16_t ci;
  66         struct mlx5_mr_ctrl mr_ctrl;
  67         int socket_id;
  68         struct mlx5_devx_cq cq;
  69         struct mlx5_devx_qp qp;
  70         struct mlx5_pmd_mr opaque_mr;
  71         struct rte_comp_op **ops;
  72         struct mlx5_compress_priv *priv;
  73         struct rte_compressdev_stats stats;
  74 };
  75
  76 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
  77                                 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
  78 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
  79
  80 int mlx5_compress_logtype;
  81
  82 static const struct rte_compressdev_capabilities mlx5_caps[] = {
  83         {
  84                 .algo = RTE_COMP_ALGO_NULL,
  85                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  86                                       RTE_COMP_FF_CRC32_CHECKSUM |
  87                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  88                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM,
  89         },
  90         {
  91                 .algo = RTE_COMP_ALGO_DEFLATE,
  92                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  93                                       RTE_COMP_FF_CRC32_CHECKSUM |
  94                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  95                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
  96                                       RTE_COMP_FF_HUFFMAN_FIXED |
  97                                       RTE_COMP_FF_HUFFMAN_DYNAMIC,
  98                 .window_size = {.min = 10, .max = 15, .increment = 1},
  99         },
 100         {
 101                 .algo = RTE_COMP_ALGO_LIST_END,
 102         }
 103 };
 104
 105 static void
 106 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
 107                            struct rte_compressdev_info *info)
 108 {
 109         RTE_SET_USED(dev);
 110         if (info != NULL) {
 111                 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
 112                 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 113                 info->capabilities = mlx5_caps;
 114         }
 115 }
 116
 117 static int
 118 mlx5_compress_dev_configure(struct rte_compressdev *dev,
 119                             struct rte_compressdev_config *config)
 120 {
 121         struct mlx5_compress_priv *priv;
 122
 123         if (dev == NULL || config == NULL)
 124                 return -EINVAL;
 125         priv = dev->data->dev_private;
 126         priv->dev_config = *config;
 127         return 0;
 128 }
 129
 130 static int
 131 mlx5_compress_dev_close(struct rte_compressdev *dev)
 132 {
 133         RTE_SET_USED(dev);
 134         return 0;
 135 }
 136
 137 static int
 138 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
 139 {
 140         struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 141
 142         if (qp->qp.qp != NULL)
 143                 mlx5_devx_qp_destroy(&qp->qp);
 144         if (qp->cq.cq != NULL)
 145                 mlx5_devx_cq_destroy(&qp->cq);
 146         if (qp->opaque_mr.obj != NULL) {
 147                 void *opaq = qp->opaque_mr.addr;
 148
 149                 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
 150                 if (opaq != NULL)
 151                         rte_free(opaq);
 152         }
 153         mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
 154         rte_free(qp);
 155         dev->data->queue_pairs[qp_id] = NULL;
 156         return 0;
 157 }
 158
 159 static void
 160 mlx5_compress_init_qp(struct mlx5_compress_qp *qp)
 161 {
 162         volatile struct mlx5_gga_wqe *restrict wqe =
 163                                     (volatile struct mlx5_gga_wqe *)qp->qp.wqes;
 164         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 165         const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u);
 166         const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 167                                         MLX5_COMP_MODE_OFFSET);
 168         const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
 169         int i;
 170
 171         /* All the next fields state should stay constant. */
 172         for (i = 0; i < qp->entries_n; ++i, ++wqe) {
 173                 wqe->sq_ds = sq_ds;
 174                 wqe->flags = flags;
 175                 wqe->opaque_lkey = opaq_lkey;
 176                 wqe->opaque_vaddr = rte_cpu_to_be_64
 177                                                 ((uint64_t)(uintptr_t)&opaq[i]);
 178         }
 179 }
 180
 181 static int
 182 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 183                        uint32_t max_inflight_ops, int socket_id)
 184 {
 185         struct mlx5_compress_priv *priv = dev->data->dev_private;
 186         struct mlx5_compress_qp *qp;
 187         struct mlx5_devx_cq_attr cq_attr = {
 188                 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
 189         };
 190         struct mlx5_devx_qp_attr qp_attr = {
 191                 .pd = priv->cdev->pdn,
 192                 .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar),
 193                 .user_index = qp_id,
 194         };
 195         uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
 196         uint32_t alloc_size = sizeof(*qp);
 197         void *opaq_buf;
 198         int ret;
 199
 200         alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
 201         alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
 202         qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
 203                                 socket_id);
 204         if (qp == NULL) {
 205                 DRV_LOG(ERR, "Failed to allocate qp memory.");
 206                 rte_errno = ENOMEM;
 207                 return -rte_errno;
 208         }
 209         dev->data->queue_pairs[qp_id] = qp;
 210         if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,
 211                                priv->dev_config.socket_id)) {
 212                 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
 213                         (uint32_t)qp_id);
 214                 rte_errno = ENOMEM;
 215                 goto err;
 216         }
 217         opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n,
 218                               sizeof(struct mlx5_gga_compress_opaque),
 219                               sizeof(struct mlx5_gga_compress_opaque));
 220         if (opaq_buf == NULL) {
 221                 DRV_LOG(ERR, "Failed to allocate opaque memory.");
 222                 rte_errno = ENOMEM;
 223                 goto err;
 224         }
 225         qp->entries_n = 1 << log_ops_n;
 226         qp->socket_id = socket_id;
 227         qp->qp_id = qp_id;
 228         qp->priv = priv;
 229         qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
 230                                                    RTE_CACHE_LINE_SIZE);
 231         if (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n *
 232                                         sizeof(struct mlx5_gga_compress_opaque),
 233                                                          &qp->opaque_mr) != 0) {
 234                 rte_free(opaq_buf);
 235                 DRV_LOG(ERR, "Failed to register opaque MR.");
 236                 rte_errno = ENOMEM;
 237                 goto err;
 238         }
 239         ret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr,
 240                                   socket_id);
 241         if (ret != 0) {
 242                 DRV_LOG(ERR, "Failed to create CQ.");
 243                 goto err;
 244         }
 245         qp_attr.cqn = qp->cq.cq->id;
 246         qp_attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format);
 247         qp_attr.rq_size = 0;
 248         qp_attr.sq_size = RTE_BIT32(log_ops_n);
 249         qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp
 250                         && priv->mmo_dma_qp;
 251         ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, log_ops_n, &qp_attr,
 252                                   socket_id);
 253         if (ret != 0) {
 254                 DRV_LOG(ERR, "Failed to create QP.");
 255                 goto err;
 256         }
 257         mlx5_compress_init_qp(qp);
 258         ret = mlx5_devx_qp2rts(&qp->qp, 0);
 259         if (ret)
 260                 goto err;
 261         /* Save pointer of global generation number to check memory event. */
 262         qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;
 263         DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u",
 264                 (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n);
 265         return 0;
 266 err:
 267         mlx5_compress_qp_release(dev, qp_id);
 268         return -1;
 269 }
 270
 271 static int
 272 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
 273 {
 274         struct mlx5_compress_priv *priv = dev->data->dev_private;
 275
 276         rte_spinlock_lock(&priv->xform_sl);
 277         LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
 278         rte_spinlock_unlock(&priv->xform_sl);
 279         rte_free(xform);
 280         return 0;
 281 }
 282
 283 static int
 284 mlx5_compress_xform_create(struct rte_compressdev *dev,
 285                            const struct rte_comp_xform *xform,
 286                            void **private_xform)
 287 {
 288         struct mlx5_compress_priv *priv = dev->data->dev_private;
 289         struct mlx5_compress_xform *xfrm;
 290         uint32_t size;
 291
 292         if (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==
 293                                                           RTE_COMP_LEVEL_NONE) {
 294                 DRV_LOG(ERR, "Non-compressed block is not supported.");
 295                 return -ENOTSUP;
 296         }
 297         if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=
 298              RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&
 299                       xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {
 300                 DRV_LOG(ERR, "SHA is not supported.");
 301                 return -ENOTSUP;
 302         }
 303         xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
 304                                                     priv->dev_config.socket_id);
 305         if (xfrm == NULL)
 306                 return -ENOMEM;
 307         xfrm->opcode = MLX5_OPCODE_MMO;
 308         xfrm->type = xform->type;
 309         switch (xform->type) {
 310         case RTE_COMP_COMPRESS:
 311                 switch (xform->compress.algo) {
 312                 case RTE_COMP_ALGO_NULL:
 313                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 314                                                         WQE_CSEG_OPC_MOD_OFFSET;
 315                         break;
 316                 case RTE_COMP_ALGO_DEFLATE:
 317                         size = 1 << xform->compress.window_size;
 318                         size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
 319                         xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 320                                          MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 321                                                 WQE_GGA_COMP_WIN_SIZE_OFFSET;
 322                         switch (xform->compress.level) {
 323                         case RTE_COMP_LEVEL_PMD_DEFAULT:
 324                                 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 325                                 break;
 326                         case RTE_COMP_LEVEL_MAX:
 327                                 size = priv->min_block_size;
 328                                 break;
 329                         default:
 330                                 size = RTE_MAX(MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX
 331                                         + 1 - xform->compress.level,
 332                                         priv->min_block_size);
 333                         }
 334                         xfrm->gga_ctrl1 += RTE_MIN(size,
 335                                             MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
 336                                                  WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 337                         xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
 338                                                         WQE_CSEG_OPC_MOD_OFFSET;
 339                         size = xform->compress.deflate.huffman ==
 340                                                       RTE_COMP_HUFFMAN_DYNAMIC ?
 341                                             MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
 342                                              MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
 343                         xfrm->gga_ctrl1 += size <<
 344                                                WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
 345                         break;
 346                 default:
 347                         goto err;
 348                 }
 349                 xfrm->csum_type = xform->compress.chksum;
 350                 break;
 351         case RTE_COMP_DECOMPRESS:
 352                 switch (xform->decompress.algo) {
 353                 case RTE_COMP_ALGO_NULL:
 354                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 355                                                         WQE_CSEG_OPC_MOD_OFFSET;
 356                         break;
 357                 case RTE_COMP_ALGO_DEFLATE:
 358                         xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
 359                                                         WQE_CSEG_OPC_MOD_OFFSET;
 360                         break;
 361                 default:
 362                         goto err;
 363                 }
 364                 xfrm->csum_type = xform->decompress.chksum;
 365                 break;
 366         default:
 367                 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
 368                 goto err;
 369         }
 370         DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
 371                 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
 372         xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
 373         rte_spinlock_lock(&priv->xform_sl);
 374         LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
 375         rte_spinlock_unlock(&priv->xform_sl);
 376         *private_xform = xfrm;
 377         return 0;
 378 err:
 379         rte_free(xfrm);
 380         return -ENOTSUP;
 381 }
 382
 383 static void
 384 mlx5_compress_dev_stop(struct rte_compressdev *dev)
 385 {
 386         RTE_SET_USED(dev);
 387 }
 388
 389 static int
 390 mlx5_compress_dev_start(struct rte_compressdev *dev)
 391 {
 392         RTE_SET_USED(dev);
 393         return 0;
 394 }
 395
 396 static void
 397 mlx5_compress_stats_get(struct rte_compressdev *dev,
 398                 struct rte_compressdev_stats *stats)
 399 {
 400         int qp_id;
 401
 402         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 403                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 404
 405                 stats->enqueued_count += qp->stats.enqueued_count;
 406                 stats->dequeued_count += qp->stats.dequeued_count;
 407                 stats->enqueue_err_count += qp->stats.enqueue_err_count;
 408                 stats->dequeue_err_count += qp->stats.dequeue_err_count;
 409         }
 410 }
 411
 412 static void
 413 mlx5_compress_stats_reset(struct rte_compressdev *dev)
 414 {
 415         int qp_id;
 416
 417         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 418                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 419
 420                 memset(&qp->stats, 0, sizeof(qp->stats));
 421         }
 422 }
 423
 424 static struct rte_compressdev_ops mlx5_compress_ops = {
 425         .dev_configure          = mlx5_compress_dev_configure,
 426         .dev_start              = mlx5_compress_dev_start,
 427         .dev_stop               = mlx5_compress_dev_stop,
 428         .dev_close              = mlx5_compress_dev_close,
 429         .dev_infos_get          = mlx5_compress_dev_info_get,
 430         .stats_get              = mlx5_compress_stats_get,
 431         .stats_reset            = mlx5_compress_stats_reset,
 432         .queue_pair_setup       = mlx5_compress_qp_setup,
 433         .queue_pair_release     = mlx5_compress_qp_release,
 434         .private_xform_create   = mlx5_compress_xform_create,
 435         .private_xform_free     = mlx5_compress_xform_free,
 436         .stream_create          = NULL,
 437         .stream_free            = NULL,
 438 };
 439
 440 /**
 441  * Query LKey from a packet buffer for QP. If not found, add the mempool.
 442  *
 443  * @param priv
 444  *   Pointer to the priv object.
 445  * @param addr
 446  *   Search key.
 447  * @param mr_ctrl
 448  *   Pointer to per-queue MR control structure.
 449  * @param ol_flags
 450  *   Mbuf offload features.
 451  *
 452  * @return
 453  *   Searched LKey on success, UINT32_MAX on no match.
 454  */
 455 static __rte_always_inline uint32_t
 456 mlx5_compress_addr2mr(struct mlx5_compress_priv *priv, uintptr_t addr,
 457                       struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags)
 458 {
 459         uint32_t lkey;
 460
 461         /* Check generation bit to see if there's any change on existing MRs. */
 462         if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
 463                 mlx5_mr_flush_local_cache(mr_ctrl);
 464         /* Linear search on MR cache array. */
 465         lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
 466                                    MLX5_MR_CACHE_N, addr);
 467         if (likely(lkey != UINT32_MAX))
 468                 return lkey;
 469         /* Take slower bottom-half on miss. */
 470         return mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl,
 471                                   addr, !!(ol_flags & EXT_ATTACHED_MBUF));
 472 }
 473
 474 static __rte_always_inline uint32_t
 475 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
 476                        volatile struct mlx5_wqe_dseg *restrict dseg,
 477                        struct rte_mbuf *restrict mbuf,
 478                        uint32_t offset, uint32_t len)
 479 {
 480         uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
 481
 482         dseg->bcount = rte_cpu_to_be_32(len);
 483         dseg->lkey = mlx5_compress_addr2mr(qp->priv, addr, &qp->mr_ctrl,
 484                                            mbuf->ol_flags);
 485         dseg->pbuf = rte_cpu_to_be_64(addr);
 486         return dseg->lkey;
 487 }
 488
 489 /*
 490  * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
 491  * 64bit architectures.
 492  */
 493 static __rte_always_inline void
 494 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv)
 495 {
 496 #ifdef RTE_ARCH_64
 497         *priv->uar_addr = val;
 498 #else /* !RTE_ARCH_64 */
 499         rte_spinlock_lock(&priv->uar32_sl);
 500         *(volatile uint32_t *)priv->uar_addr = val;
 501         rte_io_wmb();
 502         *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32;
 503         rte_spinlock_unlock(&priv->uar32_sl);
 504 #endif
 505 }
 506
 507 static uint16_t
 508 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
 509                             uint16_t nb_ops)
 510 {
 511         struct mlx5_compress_qp *qp = queue_pair;
 512         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 513                                                               qp->qp.wqes, *wqe;
 514         struct mlx5_compress_xform *xform;
 515         struct rte_comp_op *op;
 516         uint16_t mask = qp->entries_n - 1;
 517         uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
 518         uint16_t idx;
 519         bool invalid;
 520
 521         if (remain < nb_ops)
 522                 nb_ops = remain;
 523         else
 524                 remain = nb_ops;
 525         if (unlikely(remain == 0))
 526                 return 0;
 527         do {
 528                 idx = qp->pi & mask;
 529                 wqe = &wqes[idx];
 530                 rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
 531                 op = *ops++;
 532                 xform = op->private_xform;
 533                 /*
 534                  * Check operation arguments and error cases:
 535                  *   - Operation type must be state-less.
 536                  *   - Compress operation flush flag must be FULL or FINAL.
 537                  *   - Source and destination buffers must be mapped internally.
 538                  */
 539                 invalid = op->op_type != RTE_COMP_OP_STATELESS ||
 540                                             (xform->type == RTE_COMP_COMPRESS &&
 541                                           op->flush_flag < RTE_COMP_FLUSH_FULL);
 542                 if (unlikely(invalid ||
 543                              (mlx5_compress_dseg_set(qp, &wqe->gather,
 544                                                      op->m_src,
 545                                                      op->src.offset,
 546                                                      op->src.length) ==
 547                                                                   UINT32_MAX) ||
 548                              (mlx5_compress_dseg_set(qp, &wqe->scatter,
 549                                                 op->m_dst,
 550                                                 op->dst.offset,
 551                                                 rte_pktmbuf_pkt_len(op->m_dst) -
 552                                                               op->dst.offset) ==
 553                                                                  UINT32_MAX))) {
 554                         op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
 555                                                        RTE_COMP_OP_STATUS_ERROR;
 556                         nb_ops -= remain;
 557                         if (unlikely(nb_ops == 0))
 558                                 return 0;
 559                         break;
 560                 }
 561                 wqe->gga_ctrl1 = xform->gga_ctrl1;
 562                 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
 563                 qp->ops[idx] = op;
 564                 qp->pi++;
 565         } while (--remain);
 566         qp->stats.enqueued_count += nb_ops;
 567         rte_io_wmb();
 568         qp->qp.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
 569         rte_wmb();
 570         mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv);
 571         rte_wmb();
 572         return nb_ops;
 573 }
 574
 575 static void
 576 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
 577                              volatile uint32_t *opaq)
 578 {
 579         size_t i;
 580
 581         DRV_LOG(ERR, "Error cqe:");
 582         for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
 583                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 584                         cqe[i + 2], cqe[i + 3]);
 585         DRV_LOG(ERR, "\nError wqe:");
 586         for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
 587                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 588                         wqe[i + 2], wqe[i + 3]);
 589         DRV_LOG(ERR, "\nError opaq:");
 590         for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
 591                 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
 592                         opaq[i + 2], opaq[i + 3]);
 593 }
 594
 595 static void
 596 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
 597                              struct rte_comp_op *op)
 598 {
 599         const uint32_t idx = qp->ci & (qp->entries_n - 1);
 600         volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
 601                                                               &qp->cq.cqes[idx];
 602         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 603                                                                     qp->qp.wqes;
 604         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 605
 606         op->status = RTE_COMP_OP_STATUS_ERROR;
 607         op->consumed = 0;
 608         op->produced = 0;
 609         op->output_chksum = 0;
 610         op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
 611                               ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
 612         mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
 613                                  (volatile uint32_t *)&wqes[idx],
 614                                  (volatile uint32_t *)&opaq[idx]);
 615         qp->stats.dequeue_err_count++;
 616 }
 617
 618 static uint16_t
 619 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
 620                             uint16_t nb_ops)
 621 {
 622         struct mlx5_compress_qp *qp = queue_pair;
 623         volatile struct mlx5_compress_xform *restrict xform;
 624         volatile struct mlx5_cqe *restrict cqe;
 625         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 626         struct rte_comp_op *restrict op;
 627         const unsigned int cq_size = qp->entries_n;
 628         const unsigned int mask = cq_size - 1;
 629         uint32_t idx;
 630         uint32_t next_idx = qp->ci & mask;
 631         const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
 632         uint16_t i = 0;
 633         int ret;
 634
 635         if (unlikely(max == 0))
 636                 return 0;
 637         do {
 638                 idx = next_idx;
 639                 next_idx = (qp->ci + 1) & mask;
 640                 rte_prefetch0(&qp->cq.cqes[next_idx]);
 641                 rte_prefetch0(qp->ops[next_idx]);
 642                 op = qp->ops[idx];
 643                 cqe = &qp->cq.cqes[idx];
 644                 ret = check_cqe(cqe, cq_size, qp->ci);
 645                 /*
 646                  * Be sure owner read is done before any other cookie field or
 647                  * opaque field.
 648                  */
 649                 rte_io_rmb();
 650                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 651                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 652                                 break;
 653                         mlx5_compress_cqe_err_handle(qp, op);
 654                 } else {
 655                         xform = op->private_xform;
 656                         op->status = RTE_COMP_OP_STATUS_SUCCESS;
 657                         op->consumed = op->src.length;
 658                         op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
 659                         MLX5_ASSERT(cqe->byte_cnt ==
 660                                     opaq[idx].scattered_length);
 661                         switch (xform->csum_type) {
 662                         case RTE_COMP_CHECKSUM_CRC32:
 663                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 664                                                     (opaq[idx].crc32);
 665                                 break;
 666                         case RTE_COMP_CHECKSUM_ADLER32:
 667                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 668                                             (opaq[idx].adler32) << 32;
 669                                 break;
 670                         case RTE_COMP_CHECKSUM_CRC32_ADLER32:
 671                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 672                                                              (opaq[idx].crc32) |
 673                                                      ((uint64_t)rte_be_to_cpu_32
 674                                                      (opaq[idx].adler32) << 32);
 675                                 break;
 676                         default:
 677                                 break;
 678                         }
 679                 }
 680                 ops[i++] = op;
 681                 qp->ci++;
 682         } while (i < max);
 683         if (likely(i != 0)) {
 684                 rte_io_wmb();
 685                 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
 686                 qp->stats.dequeued_count += i;
 687         }
 688         return i;
 689 }
 690
 691 static void
 692 mlx5_compress_uar_release(struct mlx5_compress_priv *priv)
 693 {
 694         if (priv->uar != NULL) {
 695                 mlx5_glue->devx_free_uar(priv->uar);
 696                 priv->uar = NULL;
 697         }
 698 }
 699
 700 static int
 701 mlx5_compress_uar_prepare(struct mlx5_compress_priv *priv)
 702 {
 703         priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);
 704         if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
 705             NULL) {
 706                 rte_errno = errno;
 707                 DRV_LOG(ERR, "Failed to allocate UAR.");
 708                 return -1;
 709         }
 710         priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
 711         MLX5_ASSERT(priv->uar_addr);
 712 #ifndef RTE_ARCH_64
 713         rte_spinlock_init(&priv->uar32_sl);
 714 #endif /* RTE_ARCH_64 */
 715         return 0;
 716 }
 717
 718 /**
 719  * Callback for memory event.
 720  *
 721  * @param event_type
 722  *   Memory event type.
 723  * @param addr
 724  *   Address of memory.
 725  * @param len
 726  *   Size of memory.
 727  */
 728 static void
 729 mlx5_compress_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,
 730                               size_t len, void *arg __rte_unused)
 731 {
 732         struct mlx5_compress_priv *priv;
 733
 734         /* Must be called from the primary process. */
 735         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 736         switch (event_type) {
 737         case RTE_MEM_EVENT_FREE:
 738                 pthread_mutex_lock(&priv_list_lock);
 739                 /* Iterate all the existing mlx5 devices. */
 740                 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 741                         mlx5_free_mr_by_addr(&priv->mr_scache,
 742                                              mlx5_os_get_ctx_device_name
 743                                                               (priv->cdev->ctx),
 744                                              addr, len);
 745                 pthread_mutex_unlock(&priv_list_lock);
 746                 break;
 747         case RTE_MEM_EVENT_ALLOC:
 748         default:
 749                 break;
 750         }
 751 }
 752
 753 static int
 754 mlx5_compress_dev_probe(struct mlx5_common_device *cdev)
 755 {
 756         struct rte_compressdev *compressdev;
 757         struct mlx5_compress_priv *priv;
 758         struct mlx5_hca_attr att = { 0 };
 759         struct rte_compressdev_pmd_init_params init_params = {
 760                 .name = "",
 761                 .socket_id = cdev->dev->numa_node,
 762         };
 763         const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);
 764
 765         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 766                 DRV_LOG(ERR, "Non-primary process type is not supported.");
 767                 rte_errno = ENOTSUP;
 768                 return -rte_errno;
 769         }
 770         if (mlx5_devx_cmd_query_hca_attr(cdev->ctx, &att) != 0 ||
 771             ((att.mmo_compress_sq_en == 0 || att.mmo_decompress_sq_en == 0 ||
 772                 att.mmo_dma_sq_en == 0) && (att.mmo_compress_qp_en == 0 ||
 773                 att.mmo_decompress_qp_en == 0 || att.mmo_dma_qp_en == 0))) {
 774                 DRV_LOG(ERR, "Not enough capabilities to support compress "
 775                         "operations, maybe old FW/OFED version?");
 776                 rte_errno = ENOTSUP;
 777                 return -ENOTSUP;
 778         }
 779         compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev,
 780                                                  sizeof(*priv), &init_params);
 781         if (compressdev == NULL) {
 782                 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name);
 783                 return -ENODEV;
 784         }
 785         DRV_LOG(INFO,
 786                 "Compress device %s was created successfully.", ibdev_name);
 787         compressdev->dev_ops = &mlx5_compress_ops;
 788         compressdev->dequeue_burst = mlx5_compress_dequeue_burst;
 789         compressdev->enqueue_burst = mlx5_compress_enqueue_burst;
 790         compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 791         priv = compressdev->data->dev_private;
 792         priv->mmo_decomp_sq = att.mmo_decompress_sq_en;
 793         priv->mmo_decomp_qp = att.mmo_decompress_qp_en;
 794         priv->mmo_comp_sq = att.mmo_compress_sq_en;
 795         priv->mmo_comp_qp = att.mmo_compress_qp_en;
 796         priv->mmo_dma_sq = att.mmo_dma_sq_en;
 797         priv->mmo_dma_qp = att.mmo_dma_qp_en;
 798         priv->cdev = cdev;
 799         priv->compressdev = compressdev;
 800         priv->min_block_size = att.compress_min_block_size;
 801         priv->qp_ts_format = att.qp_ts_format;
 802         if (mlx5_compress_uar_prepare(priv) != 0) {
 803                 rte_compressdev_pmd_destroy(priv->compressdev);
 804                 return -1;
 805         }
 806         if (mlx5_mr_btree_init(&priv->mr_scache.cache,
 807                              MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {
 808                 DRV_LOG(ERR, "Failed to allocate shared cache MR memory.");
 809                 mlx5_compress_uar_release(priv);
 810                 rte_compressdev_pmd_destroy(priv->compressdev);
 811                 rte_errno = ENOMEM;
 812                 return -rte_errno;
 813         }
 814         priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;
 815         priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;
 816         /* Register callback function for global shared MR cache management. */
 817         if (TAILQ_EMPTY(&mlx5_compress_priv_list))
 818                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
 819                                                 mlx5_compress_mr_mem_event_cb,
 820                                                 NULL);
 821         pthread_mutex_lock(&priv_list_lock);
 822         TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
 823         pthread_mutex_unlock(&priv_list_lock);
 824         return 0;
 825 }
 826
 827 static int
 828 mlx5_compress_dev_remove(struct mlx5_common_device *cdev)
 829 {
 830         struct mlx5_compress_priv *priv = NULL;
 831
 832         pthread_mutex_lock(&priv_list_lock);
 833         TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 834                 if (priv->compressdev->device == cdev->dev)
 835                         break;
 836         if (priv)
 837                 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
 838         pthread_mutex_unlock(&priv_list_lock);
 839         if (priv) {
 840                 if (TAILQ_EMPTY(&mlx5_compress_priv_list))
 841                         rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB",
 842                                                           NULL);
 843                 mlx5_mr_release_cache(&priv->mr_scache);
 844                 mlx5_compress_uar_release(priv);
 845                 rte_compressdev_pmd_destroy(priv->compressdev);
 846         }
 847         return 0;
 848 }
 849
 850 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
 851         {
 852                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 853                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
 854         },
 855         {
 856                 .vendor_id = 0
 857         }
 858 };
 859
 860 static struct mlx5_class_driver mlx5_compress_driver = {
 861         .drv_class = MLX5_CLASS_COMPRESS,
 862         .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
 863         .id_table = mlx5_compress_pci_id_map,
 864         .probe = mlx5_compress_dev_probe,
 865         .remove = mlx5_compress_dev_remove,
 866 };
 867
 868 RTE_INIT(rte_mlx5_compress_init)
 869 {
 870         mlx5_common_init();
 871         if (mlx5_glue != NULL)
 872                 mlx5_class_driver_register(&mlx5_compress_driver);
 873 }
 874
 875 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE)
 876 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
 877 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
 878 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");