1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2021 Intel Corporation
6 #include "qat_comp_pmd.h"
7 #include "qat_comp_pmd_gens.h"
8 #include "icp_qat_hw_gen4_comp.h"
9 #include "icp_qat_hw_gen4_comp_defs.h"
11 #define QAT_NUM_INTERM_BUFS_GEN4 0
13 static const struct rte_compressdev_capabilities
14 qat_gen4_comp_capabilities[] = {
15 {/* COMPRESSION - deflate */
16 .algo = RTE_COMP_ALGO_DEFLATE,
17 .comp_feature_flags = RTE_COMP_FF_MULTI_PKT_CHECKSUM |
18 RTE_COMP_FF_CRC32_CHECKSUM |
19 RTE_COMP_FF_ADLER32_CHECKSUM |
20 RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
21 RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
22 RTE_COMP_FF_HUFFMAN_FIXED |
23 RTE_COMP_FF_HUFFMAN_DYNAMIC |
24 RTE_COMP_FF_OOP_SGL_IN_SGL_OUT |
25 RTE_COMP_FF_OOP_SGL_IN_LB_OUT |
26 RTE_COMP_FF_OOP_LB_IN_SGL_OUT,
27 .window_size = {.min = 15, .max = 15, .increment = 0} },
28 {RTE_COMP_ALGO_LIST_END, 0, {0, 0, 0} } };
31 qat_comp_dev_config_gen4(struct rte_compressdev *dev,
32 struct rte_compressdev_config *config)
34 /* QAT GEN4 doesn't need preallocated intermediate buffers */
36 return qat_comp_dev_config(dev, config);
39 static struct rte_compressdev_ops qat_comp_ops_gen4 = {
41 /* Device related operations */
42 .dev_configure = qat_comp_dev_config_gen4,
43 .dev_start = qat_comp_dev_start,
44 .dev_stop = qat_comp_dev_stop,
45 .dev_close = qat_comp_dev_close,
46 .dev_infos_get = qat_comp_dev_info_get,
48 .stats_get = qat_comp_stats_get,
49 .stats_reset = qat_comp_stats_reset,
50 .queue_pair_setup = qat_comp_qp_setup,
51 .queue_pair_release = qat_comp_qp_release,
53 /* Compression related operations */
54 .private_xform_create = qat_comp_private_xform_create,
55 .private_xform_free = qat_comp_private_xform_free,
56 .stream_create = qat_comp_stream_create,
57 .stream_free = qat_comp_stream_free
60 static struct qat_comp_capabilities_info
61 qat_comp_cap_get_gen4(struct qat_pci_device *qat_dev __rte_unused)
63 struct qat_comp_capabilities_info capa_info = {
64 .data = qat_gen4_comp_capabilities,
65 .size = sizeof(qat_gen4_comp_capabilities)
71 qat_comp_get_ram_bank_flags_gen4(void)
77 qat_comp_set_slice_cfg_word_gen4(struct qat_comp_xform *qat_xform,
78 const struct rte_comp_xform *xform,
79 enum rte_comp_op_type op_type, uint32_t *comp_slice_cfg_word)
81 if (qat_xform->qat_comp_request_type ==
82 QAT_COMP_REQUEST_FIXED_COMP_STATELESS ||
83 qat_xform->qat_comp_request_type ==
84 QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
86 struct icp_qat_hw_comp_20_config_csr_upper hw_comp_upper_csr;
87 struct icp_qat_hw_comp_20_config_csr_lower hw_comp_lower_csr;
89 memset(&hw_comp_upper_csr, 0, sizeof(hw_comp_upper_csr));
90 memset(&hw_comp_lower_csr, 0, sizeof(hw_comp_lower_csr));
92 hw_comp_lower_csr.lllbd =
93 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_DISABLED;
95 if (xform->compress.algo == RTE_COMP_ALGO_DEFLATE) {
96 hw_comp_lower_csr.skip_ctrl =
97 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL;
99 if (qat_xform->qat_comp_request_type ==
100 QAT_COMP_REQUEST_DYNAMIC_COMP_STATELESS) {
101 hw_comp_lower_csr.algo =
102 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77;
103 hw_comp_lower_csr.lllbd =
104 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED;
106 hw_comp_lower_csr.algo =
107 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE;
108 hw_comp_upper_csr.scb_ctrl =
109 ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE;
112 if (op_type == RTE_COMP_OP_STATEFUL) {
113 hw_comp_upper_csr.som_ctrl =
114 ICP_QAT_HW_COMP_20_SOM_CONTROL_REPLAY_MODE;
117 QAT_LOG(ERR, "Compression algorithm not supported");
121 switch (xform->compress.level) {
127 hw_comp_lower_csr.sd =
128 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1;
129 hw_comp_lower_csr.hash_col =
130 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_DONT_ALLOW;
135 case RTE_COMP_LEVEL_PMD_DEFAULT:
136 hw_comp_lower_csr.sd =
137 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_6;
143 hw_comp_lower_csr.sd =
144 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_9;
147 QAT_LOG(ERR, "Compression level not supported");
151 hw_comp_lower_csr.abd = ICP_QAT_HW_COMP_20_ABD_ABD_DISABLED;
152 hw_comp_lower_csr.hash_update =
153 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW;
154 hw_comp_lower_csr.edmm =
155 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED;
157 hw_comp_upper_csr.nice =
158 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL;
159 hw_comp_upper_csr.lazy =
160 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL;
162 comp_slice_cfg_word[0] =
163 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(
165 comp_slice_cfg_word[1] =
166 ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(
170 struct icp_qat_hw_decomp_20_config_csr_lower
173 memset(&hw_decomp_lower_csr, 0, sizeof(hw_decomp_lower_csr));
175 if (xform->compress.algo == RTE_COMP_ALGO_DEFLATE)
176 hw_decomp_lower_csr.algo =
177 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE;
179 QAT_LOG(ERR, "Compression algorithm not supported");
183 comp_slice_cfg_word[0] =
184 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(
185 hw_decomp_lower_csr);
186 comp_slice_cfg_word[1] = 0;
193 qat_comp_get_num_im_bufs_required_gen4(void)
195 return QAT_NUM_INTERM_BUFS_GEN4;
199 RTE_INIT(qat_comp_pmd_gen4_init)
201 qat_comp_gen_dev_ops[QAT_GEN4].compressdev_ops =
203 qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_capabilities =
204 qat_comp_cap_get_gen4;
205 qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_num_im_bufs_required =
206 qat_comp_get_num_im_bufs_required_gen4;
207 qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_ram_bank_flags =
208 qat_comp_get_ram_bank_flags_gen4;
209 qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_set_slice_cfg_word =
210 qat_comp_set_slice_cfg_word_gen4;
211 qat_comp_gen_dev_ops[QAT_GEN4].qat_comp_get_feature_flags =
212 qat_comp_get_features_gen1;