4 * Copyright(c) 2016 Intel Corporation. All rights reserved.
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33 #include <openssl/aes.h>
35 #include <rte_common.h>
36 #include <rte_config.h>
37 #include <rte_hexdump.h>
38 #include <rte_cryptodev.h>
39 #include <rte_cryptodev_pmd.h>
41 #include <rte_malloc.h>
42 #include <rte_cpuflags.h>
43 #include <rte_byteorder.h>
45 #include "aesni_gcm_pmd_private.h"
48 aesni_gcm_calculate_hash_sub_key(uint8_t *hsubkey, unsigned hsubkey_length,
49 uint8_t *aeskey, unsigned aeskey_length)
51 uint8_t key[aeskey_length] __rte_aligned(16);
54 if (hsubkey_length % 16 != 0 && aeskey_length % 16 != 0)
57 memcpy(key, aeskey, aeskey_length);
59 if (AES_set_encrypt_key(key, aeskey_length << 3, &enc_key) != 0)
62 AES_encrypt(hsubkey, hsubkey, &enc_key);
67 /** Get xform chain order */
69 aesni_gcm_get_mode(const struct rte_crypto_sym_xform *xform)
72 * GCM only supports authenticated encryption or authenticated
73 * decryption, all other options are invalid, so we must have exactly
74 * 2 xform structs chained together
76 if (xform->next == NULL || xform->next->next != NULL)
79 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
80 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
81 return AESNI_GCM_OP_AUTHENTICATED_ENCRYPTION;
84 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
85 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {
86 return AESNI_GCM_OP_AUTHENTICATED_DECRYPTION;
92 /** Parse crypto xform chain and set private session parameters */
94 aesni_gcm_set_session_parameters(const struct aesni_gcm_ops *gcm_ops,
95 struct aesni_gcm_session *sess,
96 const struct rte_crypto_sym_xform *xform)
98 const struct rte_crypto_sym_xform *auth_xform = NULL;
99 const struct rte_crypto_sym_xform *cipher_xform = NULL;
101 uint8_t hsubkey[16] __rte_aligned(16) = { 0 };
103 /* Select Crypto operation - hash then cipher / cipher then hash */
104 switch (aesni_gcm_get_mode(xform)) {
105 case AESNI_GCM_OP_AUTHENTICATED_ENCRYPTION:
106 sess->op = AESNI_GCM_OP_AUTHENTICATED_ENCRYPTION;
108 cipher_xform = xform;
109 auth_xform = xform->next;
111 case AESNI_GCM_OP_AUTHENTICATED_DECRYPTION:
112 sess->op = AESNI_GCM_OP_AUTHENTICATED_DECRYPTION;
115 cipher_xform = xform->next;
118 GCM_LOG_ERR("Unsupported operation chain order parameter");
122 /* We only support AES GCM */
123 if (cipher_xform->cipher.algo != RTE_CRYPTO_CIPHER_AES_GCM &&
124 auth_xform->auth.algo != RTE_CRYPTO_AUTH_AES_GCM)
127 /* Select cipher direction */
128 if (sess->op == AESNI_GCM_OP_AUTHENTICATED_ENCRYPTION &&
129 cipher_xform->cipher.op !=
130 RTE_CRYPTO_CIPHER_OP_ENCRYPT) {
131 GCM_LOG_ERR("xform chain (CIPHER/AUTH) and cipher operation "
132 "(DECRYPT) specified are an invalid selection");
134 } else if (sess->op == AESNI_GCM_OP_AUTHENTICATED_DECRYPTION &&
135 cipher_xform->cipher.op !=
136 RTE_CRYPTO_CIPHER_OP_DECRYPT) {
137 GCM_LOG_ERR("xform chain (AUTH/CIPHER) and cipher operation "
138 "(ENCRYPT) specified are an invalid selection");
142 /* Expand GCM AES128 key */
143 (*gcm_ops->aux.keyexp.aes128_enc)(cipher_xform->cipher.key.data,
144 sess->gdata.expanded_keys);
146 /* Calculate hash sub key here */
147 aesni_gcm_calculate_hash_sub_key(hsubkey, sizeof(hsubkey),
148 cipher_xform->cipher.key.data,
149 cipher_xform->cipher.key.length);
151 /* Calculate GCM pre-compute */
152 (*gcm_ops->gcm.precomp)(&sess->gdata, hsubkey);
157 /** Get gcm session */
158 static struct aesni_gcm_session *
159 aesni_gcm_get_session(struct aesni_gcm_qp *qp, struct rte_crypto_sym_op *op)
161 struct aesni_gcm_session *sess = NULL;
163 if (op->sess_type == RTE_CRYPTO_SYM_OP_WITH_SESSION) {
164 if (unlikely(op->session->dev_type
165 != RTE_CRYPTODEV_AESNI_GCM_PMD))
168 sess = (struct aesni_gcm_session *)op->session->_private;
172 if (rte_mempool_get(qp->sess_mp, &_sess))
175 sess = (struct aesni_gcm_session *)
176 ((struct rte_cryptodev_session *)_sess)->_private;
178 if (unlikely(aesni_gcm_set_session_parameters(qp->ops,
179 sess, op->xform) != 0)) {
180 rte_mempool_put(qp->sess_mp, _sess);
188 * Process a crypto operation and complete a JOB_AES_HMAC job structure for
189 * submission to the multi buffer library for processing.
191 * @param qp queue pair
192 * @param op symmetric crypto operation
193 * @param session GCM session
199 process_gcm_crypto_op(struct aesni_gcm_qp *qp, struct rte_crypto_sym_op *op,
200 struct aesni_gcm_session *session)
203 struct rte_mbuf *m = op->m_src;
205 src = rte_pktmbuf_mtod(m, uint8_t *) + op->cipher.data.offset;
207 rte_pktmbuf_mtod_offset(op->m_dst, uint8_t *,
208 op->cipher.data.offset) :
209 rte_pktmbuf_mtod_offset(m, uint8_t *,
210 op->cipher.data.offset);
213 if (op->cipher.iv.length != 16 && op->cipher.iv.length != 12 &&
214 op->cipher.iv.length != 0) {
220 * GCM working in 12B IV mode => 16B pre-counter block we need
221 * to set BE LSB to 1, driver expects that 16B is allocated
223 if (op->cipher.iv.length == 12) {
224 uint32_t *iv_padd = (uint32_t *)&op->cipher.iv.data[12];
225 *iv_padd = rte_bswap32(1);
228 if (op->auth.aad.length != 12 && op->auth.aad.length != 8 &&
229 op->auth.aad.length != 0) {
234 if (op->auth.digest.length != 16 &&
235 op->auth.digest.length != 12 &&
236 op->auth.digest.length != 8 &&
237 op->auth.digest.length != 0) {
242 if (session->op == AESNI_GCM_OP_AUTHENTICATED_ENCRYPTION) {
244 (*qp->ops->gcm.enc)(&session->gdata, dst, src,
245 (uint64_t)op->cipher.data.length,
248 (uint64_t)op->auth.aad.length,
249 op->auth.digest.data,
250 (uint64_t)op->auth.digest.length);
251 } else if (session->op == AESNI_GCM_OP_AUTHENTICATED_DECRYPTION) {
252 uint8_t *auth_tag = (uint8_t *)rte_pktmbuf_append(m,
253 op->auth.digest.length);
260 (*qp->ops->gcm.dec)(&session->gdata, dst, src,
261 (uint64_t)op->cipher.data.length,
264 (uint64_t)op->auth.aad.length,
266 (uint64_t)op->auth.digest.length);
276 * Process a completed job and return rte_mbuf which job processed
278 * @param job JOB_AES_HMAC job to process
281 * - Returns processed mbuf which is trimmed of output digest used in
282 * verification of supplied digest in the case of a HASH_CIPHER operation
283 * - Returns NULL on invalid job
286 post_process_gcm_crypto_op(struct rte_crypto_op *op)
288 struct rte_mbuf *m = op->sym->m_dst ? op->sym->m_dst : op->sym->m_src;
290 struct aesni_gcm_session *session =
291 (struct aesni_gcm_session *)op->sym->session->_private;
293 op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
295 /* Verify digest if required */
296 if (session->op == AESNI_GCM_OP_AUTHENTICATED_DECRYPTION) {
298 uint8_t *tag = rte_pktmbuf_mtod_offset(m, uint8_t *,
299 m->data_len - op->sym->auth.digest.length);
301 #ifdef RTE_LIBRTE_PMD_AESNI_GCM_DEBUG
302 rte_hexdump(stdout, "auth tag (orig):",
303 op->sym->auth.digest.data, op->sym->auth.digest.length);
304 rte_hexdump(stdout, "auth tag (calc):",
305 tag, op->sym->auth.digest.length);
308 if (memcmp(tag, op->sym->auth.digest.data,
309 op->sym->auth.digest.length) != 0)
310 op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
312 /* trim area used for digest from mbuf */
313 rte_pktmbuf_trim(m, op->sym->auth.digest.length);
318 * Process a completed GCM request
320 * @param qp Queue Pair to process
321 * @param job JOB_AES_HMAC job
324 * - Number of processed jobs
327 handle_completed_gcm_crypto_op(struct aesni_gcm_qp *qp,
328 struct rte_crypto_op *op)
330 post_process_gcm_crypto_op(op);
332 /* Free session if a session-less crypto op */
333 if (op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS) {
334 rte_mempool_put(qp->sess_mp, op->sym->session);
335 op->sym->session = NULL;
338 rte_ring_enqueue(qp->processed_pkts, (void *)op);
342 aesni_gcm_pmd_enqueue_burst(void *queue_pair,
343 struct rte_crypto_op **ops, uint16_t nb_ops)
345 struct aesni_gcm_session *sess;
346 struct aesni_gcm_qp *qp = queue_pair;
350 for (i = 0; i < nb_ops; i++) {
352 sess = aesni_gcm_get_session(qp, ops[i]->sym);
353 if (unlikely(sess == NULL)) {
354 ops[i]->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
355 qp->qp_stats.enqueue_err_count++;
359 #ifdef RTE_LIBRTE_PMD_AESNI_GCM_DEBUG
360 if (!rte_pktmbuf_is_contiguous(ops[i]->sym->m_src) ||
361 (ops[i]->sym->m_dst != NULL &&
362 !rte_pktmbuf_is_contiguous(
363 ops[i]->sym->m_dst))) {
364 ops[i]->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
365 GCM_LOG_ERR("PMD supports only contiguous mbufs, "
366 "op (%p) provides noncontiguous mbuf as "
367 "source/destination buffer.\n", ops[i]);
368 qp->qp_stats.enqueue_err_count++;
373 retval = process_gcm_crypto_op(qp, ops[i]->sym, sess);
375 ops[i]->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
376 qp->qp_stats.enqueue_err_count++;
380 handle_completed_gcm_crypto_op(qp, ops[i]);
382 qp->qp_stats.enqueued_count++;
388 aesni_gcm_pmd_dequeue_burst(void *queue_pair,
389 struct rte_crypto_op **ops, uint16_t nb_ops)
391 struct aesni_gcm_qp *qp = queue_pair;
393 unsigned nb_dequeued;
395 nb_dequeued = rte_ring_dequeue_burst(qp->processed_pkts,
396 (void **)ops, nb_ops);
397 qp->qp_stats.dequeued_count += nb_dequeued;
402 static int aesni_gcm_remove(const char *name);
405 aesni_gcm_create(struct rte_crypto_vdev_init_params *init_params)
407 struct rte_cryptodev *dev;
408 struct aesni_gcm_private *internals;
409 enum aesni_gcm_vector_mode vector_mode;
411 if (init_params->name[0] == '\0') {
412 int ret = rte_cryptodev_pmd_create_dev_name(
414 RTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD));
417 GCM_LOG_ERR("failed to create unique name");
422 /* Check CPU for support for AES instruction set */
423 if (!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AES)) {
424 GCM_LOG_ERR("AES instructions not supported by CPU");
428 /* Check CPU for supported vector instruction set */
429 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
430 vector_mode = RTE_AESNI_GCM_AVX2;
431 else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX))
432 vector_mode = RTE_AESNI_GCM_AVX;
433 else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
434 vector_mode = RTE_AESNI_GCM_SSE;
436 GCM_LOG_ERR("Vector instructions are not supported by CPU");
440 dev = rte_cryptodev_pmd_virtual_dev_init(init_params->name,
441 sizeof(struct aesni_gcm_private), init_params->socket_id);
443 GCM_LOG_ERR("failed to create cryptodev vdev");
447 dev->dev_type = RTE_CRYPTODEV_AESNI_GCM_PMD;
448 dev->dev_ops = rte_aesni_gcm_pmd_ops;
450 /* register rx/tx burst functions for data path */
451 dev->dequeue_burst = aesni_gcm_pmd_dequeue_burst;
452 dev->enqueue_burst = aesni_gcm_pmd_enqueue_burst;
454 dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
455 RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
456 RTE_CRYPTODEV_FF_CPU_AESNI;
458 switch (vector_mode) {
459 case RTE_AESNI_GCM_SSE:
460 dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_SSE;
462 case RTE_AESNI_GCM_AVX:
463 dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX;
465 case RTE_AESNI_GCM_AVX2:
466 dev->feature_flags |= RTE_CRYPTODEV_FF_CPU_AVX2;
472 /* Set vector instructions mode supported */
473 internals = dev->data->dev_private;
475 internals->vector_mode = vector_mode;
477 internals->max_nb_queue_pairs = init_params->max_nb_queue_pairs;
478 internals->max_nb_sessions = init_params->max_nb_sessions;
483 GCM_LOG_ERR("driver %s: create failed", init_params->name);
485 aesni_gcm_remove(init_params->name);
490 aesni_gcm_probe(const char *name, const char *input_args)
492 struct rte_crypto_vdev_init_params init_params = {
493 RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_QUEUE_PAIRS,
494 RTE_CRYPTODEV_VDEV_DEFAULT_MAX_NB_SESSIONS,
499 rte_cryptodev_parse_vdev_init_params(&init_params, input_args);
501 RTE_LOG(INFO, PMD, "Initialising %s on NUMA node %d\n", name,
502 init_params.socket_id);
503 if (init_params.name[0] != '\0')
504 RTE_LOG(INFO, PMD, " User defined name = %s\n",
506 RTE_LOG(INFO, PMD, " Max number of queue pairs = %d\n",
507 init_params.max_nb_queue_pairs);
508 RTE_LOG(INFO, PMD, " Max number of sessions = %d\n",
509 init_params.max_nb_sessions);
511 return aesni_gcm_create(&init_params);
515 aesni_gcm_remove(const char *name)
520 GCM_LOG_INFO("Closing AESNI crypto device %s on numa socket %u\n",
521 name, rte_socket_id());
526 static struct rte_vdev_driver aesni_gcm_pmd_drv = {
527 .probe = aesni_gcm_probe,
528 .remove = aesni_gcm_remove
531 RTE_PMD_REGISTER_VDEV(CRYPTODEV_NAME_AESNI_GCM_PMD, aesni_gcm_pmd_drv);
532 RTE_PMD_REGISTER_ALIAS(CRYPTODEV_NAME_AESNI_GCM_PMD, cryptodev_aesni_gcm_pmd);
533 RTE_PMD_REGISTER_PARAM_STRING(CRYPTODEV_NAME_AESNI_GCM_PMD,
534 "max_nb_queue_pairs=<int> "
535 "max_nb_sessions=<int> "