1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017-2019 NXP
10 #include <rte_byteorder.h>
11 #include <rte_common.h>
12 #include <rte_cryptodev_pmd.h>
13 #include <rte_crypto.h>
14 #include <rte_cryptodev.h>
15 #include <rte_bus_vdev.h>
16 #include <rte_malloc.h>
17 #include <rte_security_driver.h>
18 #include <rte_hexdump.h>
20 #include <caam_jr_capabilities.h>
21 #include <caam_jr_config.h>
22 #include <caam_jr_hw_specific.h>
23 #include <caam_jr_pvt.h>
24 #include <caam_jr_desc.h>
25 #include <caam_jr_log.h>
27 /* RTA header files */
28 #include <desc/common.h>
29 #include <desc/algo.h>
31 #ifdef RTE_LIBRTE_PMD_CAAM_JR_DEBUG
36 #define CRYPTODEV_NAME_CAAM_JR_PMD crypto_caam_jr
37 static uint8_t cryptodev_driver_id;
39 /* Lists the states possible for the SEC user space driver. */
40 enum sec_driver_state_e {
41 SEC_DRIVER_STATE_IDLE, /* Driver not initialized */
42 SEC_DRIVER_STATE_STARTED, /* Driver initialized and can be used*/
43 SEC_DRIVER_STATE_RELEASE, /* Driver release is in progress */
46 /* Job rings used for communication with SEC HW */
47 static struct sec_job_ring_t g_job_rings[MAX_SEC_JOB_RINGS];
49 /* The current state of SEC user space driver */
50 static enum sec_driver_state_e g_driver_state = SEC_DRIVER_STATE_IDLE;
52 /* The number of job rings used by SEC user space driver */
53 static int g_job_rings_no;
54 static int g_job_rings_max;
56 struct sec_outring_entry {
57 phys_addr_t desc; /* Pointer to completed descriptor */
58 uint32_t status; /* Status for completed descriptor */
61 /* virtual address conversin when mempool support is available for ctx */
62 static inline phys_addr_t
63 caam_jr_vtop_ctx(struct caam_jr_op_ctx *ctx, void *vaddr)
65 return (size_t)vaddr - ctx->vtop_offset;
69 caam_jr_op_ending(struct caam_jr_op_ctx *ctx)
71 /* report op status to sym->op and then free the ctx memory */
72 rte_mempool_put(ctx->ctx_pool, (void *)ctx);
75 static inline struct caam_jr_op_ctx *
76 caam_jr_alloc_ctx(struct caam_jr_session *ses)
78 struct caam_jr_op_ctx *ctx;
81 ret = rte_mempool_get(ses->ctx_pool, (void **)(&ctx));
83 CAAM_JR_DP_WARN("Alloc sec descriptor failed!");
87 * Clear SG memory. There are 16 SG entries of 16 Bytes each.
88 * one call to dcbz_64() clear 64 bytes, hence calling it 4 times
89 * to clear all the SG entries. caam_jr_alloc_ctx() is called for
90 * each packet, memset is costlier than dcbz_64().
92 dcbz_64(&ctx->sg[SG_CACHELINE_0]);
93 dcbz_64(&ctx->sg[SG_CACHELINE_1]);
94 dcbz_64(&ctx->sg[SG_CACHELINE_2]);
95 dcbz_64(&ctx->sg[SG_CACHELINE_3]);
97 ctx->ctx_pool = ses->ctx_pool;
98 ctx->vtop_offset = (size_t) ctx - rte_mempool_virt2iova(ctx);
104 void caam_jr_stats_get(struct rte_cryptodev *dev,
105 struct rte_cryptodev_stats *stats)
107 struct caam_jr_qp **qp = (struct caam_jr_qp **)
108 dev->data->queue_pairs;
111 PMD_INIT_FUNC_TRACE();
113 CAAM_JR_ERR("Invalid stats ptr NULL");
116 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
118 CAAM_JR_WARN("Uninitialised queue pair");
122 stats->enqueued_count += qp[i]->tx_pkts;
123 stats->dequeued_count += qp[i]->rx_pkts;
124 stats->enqueue_err_count += qp[i]->tx_errs;
125 stats->dequeue_err_count += qp[i]->rx_errs;
126 CAAM_JR_INFO("extra stats:\n\tRX Poll ERR = %" PRIu64
127 "\n\tTX Ring Full = %" PRIu64,
129 qp[i]->tx_ring_full);
134 void caam_jr_stats_reset(struct rte_cryptodev *dev)
137 struct caam_jr_qp **qp = (struct caam_jr_qp **)
138 (dev->data->queue_pairs);
140 PMD_INIT_FUNC_TRACE();
141 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
143 CAAM_JR_WARN("Uninitialised queue pair");
148 qp[i]->rx_poll_err = 0;
151 qp[i]->tx_ring_full = 0;
156 is_cipher_only(struct caam_jr_session *ses)
158 return ((ses->cipher_alg != RTE_CRYPTO_CIPHER_NULL) &&
159 (ses->auth_alg == RTE_CRYPTO_AUTH_NULL));
163 is_auth_only(struct caam_jr_session *ses)
165 return ((ses->cipher_alg == RTE_CRYPTO_CIPHER_NULL) &&
166 (ses->auth_alg != RTE_CRYPTO_AUTH_NULL));
170 is_aead(struct caam_jr_session *ses)
172 return ((ses->cipher_alg == 0) &&
173 (ses->auth_alg == 0) &&
174 (ses->aead_alg != 0));
178 is_auth_cipher(struct caam_jr_session *ses)
180 return ((ses->cipher_alg != RTE_CRYPTO_CIPHER_NULL) &&
181 (ses->auth_alg != RTE_CRYPTO_AUTH_NULL) &&
182 (ses->proto_alg != RTE_SECURITY_PROTOCOL_IPSEC));
186 is_proto_ipsec(struct caam_jr_session *ses)
188 return (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC);
192 is_encode(struct caam_jr_session *ses)
194 return ses->dir == DIR_ENC;
198 is_decode(struct caam_jr_session *ses)
200 return ses->dir == DIR_DEC;
204 caam_auth_alg(struct caam_jr_session *ses, struct alginfo *alginfo_a)
206 switch (ses->auth_alg) {
207 case RTE_CRYPTO_AUTH_NULL:
208 ses->digest_length = 0;
210 case RTE_CRYPTO_AUTH_MD5_HMAC:
212 (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ?
213 OP_PCL_IPSEC_HMAC_MD5_96 : OP_ALG_ALGSEL_MD5;
214 alginfo_a->algmode = OP_ALG_AAI_HMAC;
216 case RTE_CRYPTO_AUTH_SHA1_HMAC:
218 (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ?
219 OP_PCL_IPSEC_HMAC_SHA1_96 : OP_ALG_ALGSEL_SHA1;
220 alginfo_a->algmode = OP_ALG_AAI_HMAC;
222 case RTE_CRYPTO_AUTH_SHA224_HMAC:
224 (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ?
225 OP_PCL_IPSEC_HMAC_SHA1_160 : OP_ALG_ALGSEL_SHA224;
226 alginfo_a->algmode = OP_ALG_AAI_HMAC;
228 case RTE_CRYPTO_AUTH_SHA256_HMAC:
230 (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ?
231 OP_PCL_IPSEC_HMAC_SHA2_256_128 : OP_ALG_ALGSEL_SHA256;
232 alginfo_a->algmode = OP_ALG_AAI_HMAC;
234 case RTE_CRYPTO_AUTH_SHA384_HMAC:
236 (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ?
237 OP_PCL_IPSEC_HMAC_SHA2_384_192 : OP_ALG_ALGSEL_SHA384;
238 alginfo_a->algmode = OP_ALG_AAI_HMAC;
240 case RTE_CRYPTO_AUTH_SHA512_HMAC:
242 (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ?
243 OP_PCL_IPSEC_HMAC_SHA2_512_256 : OP_ALG_ALGSEL_SHA512;
244 alginfo_a->algmode = OP_ALG_AAI_HMAC;
247 CAAM_JR_DEBUG("unsupported auth alg %u", ses->auth_alg);
252 caam_cipher_alg(struct caam_jr_session *ses, struct alginfo *alginfo_c)
254 switch (ses->cipher_alg) {
255 case RTE_CRYPTO_CIPHER_NULL:
257 case RTE_CRYPTO_CIPHER_AES_CBC:
259 (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ?
260 OP_PCL_IPSEC_AES_CBC : OP_ALG_ALGSEL_AES;
261 alginfo_c->algmode = OP_ALG_AAI_CBC;
263 case RTE_CRYPTO_CIPHER_3DES_CBC:
265 (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ?
266 OP_PCL_IPSEC_3DES : OP_ALG_ALGSEL_3DES;
267 alginfo_c->algmode = OP_ALG_AAI_CBC;
269 case RTE_CRYPTO_CIPHER_AES_CTR:
271 (ses->proto_alg == RTE_SECURITY_PROTOCOL_IPSEC) ?
272 OP_PCL_IPSEC_AES_CTR : OP_ALG_ALGSEL_AES;
273 alginfo_c->algmode = OP_ALG_AAI_CTR;
276 CAAM_JR_DEBUG("unsupported cipher alg %d", ses->cipher_alg);
281 caam_aead_alg(struct caam_jr_session *ses, struct alginfo *alginfo)
283 switch (ses->aead_alg) {
284 case RTE_CRYPTO_AEAD_AES_GCM:
285 alginfo->algtype = OP_ALG_ALGSEL_AES;
286 alginfo->algmode = OP_ALG_AAI_GCM;
289 CAAM_JR_DEBUG("unsupported AEAD alg %d", ses->aead_alg);
293 /* prepare command block of the session */
295 caam_jr_prep_cdb(struct caam_jr_session *ses)
297 struct alginfo alginfo_c = {0}, alginfo_a = {0}, alginfo = {0};
298 int32_t shared_desc_len = 0;
301 #if CAAM_BYTE_ORDER == CORE_BYTE_ORDER
308 caam_jr_dma_free(ses->cdb);
310 cdb = caam_jr_dma_mem_alloc(L1_CACHE_BYTES, sizeof(struct sec_cdb));
312 CAAM_JR_ERR("failed to allocate memory for cdb\n");
318 memset(cdb, 0, sizeof(struct sec_cdb));
320 if (is_cipher_only(ses)) {
321 caam_cipher_alg(ses, &alginfo_c);
322 if (alginfo_c.algtype == (unsigned int)CAAM_JR_ALG_UNSUPPORT) {
323 CAAM_JR_ERR("not supported cipher alg");
328 alginfo_c.key = (size_t)ses->cipher_key.data;
329 alginfo_c.keylen = ses->cipher_key.length;
330 alginfo_c.key_enc_flags = 0;
331 alginfo_c.key_type = RTA_DATA_IMM;
333 shared_desc_len = cnstr_shdsc_blkcipher(
335 swap, SHR_NEVER, &alginfo_c,
338 } else if (is_auth_only(ses)) {
339 caam_auth_alg(ses, &alginfo_a);
340 if (alginfo_a.algtype == (unsigned int)CAAM_JR_ALG_UNSUPPORT) {
341 CAAM_JR_ERR("not supported auth alg");
346 alginfo_a.key = (size_t)ses->auth_key.data;
347 alginfo_a.keylen = ses->auth_key.length;
348 alginfo_a.key_enc_flags = 0;
349 alginfo_a.key_type = RTA_DATA_IMM;
351 shared_desc_len = cnstr_shdsc_hmac(cdb->sh_desc, true,
352 swap, SHR_NEVER, &alginfo_a,
355 } else if (is_aead(ses)) {
356 caam_aead_alg(ses, &alginfo);
357 if (alginfo.algtype == (unsigned int)CAAM_JR_ALG_UNSUPPORT) {
358 CAAM_JR_ERR("not supported aead alg");
362 alginfo.key = (size_t)ses->aead_key.data;
363 alginfo.keylen = ses->aead_key.length;
364 alginfo.key_enc_flags = 0;
365 alginfo.key_type = RTA_DATA_IMM;
367 if (ses->dir == DIR_ENC)
368 shared_desc_len = cnstr_shdsc_gcm_encap(
369 cdb->sh_desc, true, swap,
374 shared_desc_len = cnstr_shdsc_gcm_decap(
375 cdb->sh_desc, true, swap,
380 caam_cipher_alg(ses, &alginfo_c);
381 if (alginfo_c.algtype == (unsigned int)CAAM_JR_ALG_UNSUPPORT) {
382 CAAM_JR_ERR("not supported cipher alg");
387 alginfo_c.key = (size_t)ses->cipher_key.data;
388 alginfo_c.keylen = ses->cipher_key.length;
389 alginfo_c.key_enc_flags = 0;
390 alginfo_c.key_type = RTA_DATA_IMM;
392 caam_auth_alg(ses, &alginfo_a);
393 if (alginfo_a.algtype == (unsigned int)CAAM_JR_ALG_UNSUPPORT) {
394 CAAM_JR_ERR("not supported auth alg");
399 alginfo_a.key = (size_t)ses->auth_key.data;
400 alginfo_a.keylen = ses->auth_key.length;
401 alginfo_a.key_enc_flags = 0;
402 alginfo_a.key_type = RTA_DATA_IMM;
404 cdb->sh_desc[0] = alginfo_c.keylen;
405 cdb->sh_desc[1] = alginfo_a.keylen;
406 err = rta_inline_query(IPSEC_AUTH_VAR_AES_DEC_BASE_DESC_LEN,
408 (unsigned int *)cdb->sh_desc,
409 &cdb->sh_desc[2], 2);
412 CAAM_JR_ERR("Crypto: Incorrect key lengths");
416 if (cdb->sh_desc[2] & 1)
417 alginfo_c.key_type = RTA_DATA_IMM;
419 alginfo_c.key = (size_t)caam_jr_mem_vtop(
420 (void *)(size_t)alginfo_c.key);
421 alginfo_c.key_type = RTA_DATA_PTR;
423 if (cdb->sh_desc[2] & (1<<1))
424 alginfo_a.key_type = RTA_DATA_IMM;
426 alginfo_a.key = (size_t)caam_jr_mem_vtop(
427 (void *)(size_t)alginfo_a.key);
428 alginfo_a.key_type = RTA_DATA_PTR;
433 if (is_proto_ipsec(ses)) {
434 if (ses->dir == DIR_ENC) {
435 shared_desc_len = cnstr_shdsc_ipsec_new_encap(
437 true, swap, SHR_SERIAL,
439 (uint8_t *)&ses->ip4_hdr,
440 &alginfo_c, &alginfo_a);
441 } else if (ses->dir == DIR_DEC) {
442 shared_desc_len = cnstr_shdsc_ipsec_new_decap(
444 true, swap, SHR_SERIAL,
446 &alginfo_c, &alginfo_a);
449 /* Auth_only_len is overwritten in fd for each job */
450 shared_desc_len = cnstr_shdsc_authenc(cdb->sh_desc,
451 true, swap, SHR_SERIAL,
452 &alginfo_c, &alginfo_a,
454 ses->digest_length, ses->dir);
458 if (shared_desc_len < 0) {
459 CAAM_JR_ERR("error in preparing command block");
460 return shared_desc_len;
464 SEC_DUMP_DESC(cdb->sh_desc);
467 cdb->sh_hdr.hi.field.idlen = shared_desc_len;
472 /* @brief Poll the HW for already processed jobs in the JR
473 * and silently discard the available jobs or notify them to UA
474 * with indicated error code.
476 * @param [in,out] job_ring The job ring to poll.
477 * @param [in] do_notify Can be #TRUE or #FALSE. Indicates if
478 * descriptors are to be discarded
479 * or notified to UA with given error_code.
480 * @param [out] notified_descs Number of notified descriptors. Can be NULL
481 * if do_notify is #FALSE
484 hw_flush_job_ring(struct sec_job_ring_t *job_ring,
486 uint32_t *notified_descs)
488 int32_t jobs_no_to_discard = 0;
489 int32_t discarded_descs_no = 0;
491 CAAM_JR_DEBUG("Jr[%p] pi[%d] ci[%d].Flushing jr notify desc=[%d]",
492 job_ring, job_ring->pidx, job_ring->cidx, do_notify);
494 jobs_no_to_discard = hw_get_no_finished_jobs(job_ring);
496 /* Discard all jobs */
497 CAAM_JR_DEBUG("Jr[%p] pi[%d] ci[%d].Discarding %d descs",
498 job_ring, job_ring->pidx, job_ring->cidx,
501 while (jobs_no_to_discard > discarded_descs_no) {
502 discarded_descs_no++;
503 /* Now increment the consumer index for the current job ring,
504 * AFTER saving job in temporary location!
505 * Increment the consumer index for the current job ring
507 job_ring->cidx = SEC_CIRCULAR_COUNTER(job_ring->cidx,
510 hw_remove_entries(job_ring, 1);
513 if (do_notify == true) {
514 ASSERT(notified_descs != NULL);
515 *notified_descs = discarded_descs_no;
519 /* @brief Poll the HW for already processed jobs in the JR
520 * and notify the available jobs to UA.
522 * @param [in] job_ring The job ring to poll.
523 * @param [in] limit The maximum number of jobs to notify.
524 * If set to negative value, all available jobs are
527 * @retval >=0 for No of jobs notified to UA.
528 * @retval -1 for error
531 hw_poll_job_ring(struct sec_job_ring_t *job_ring,
532 struct rte_crypto_op **ops, int32_t limit,
533 struct caam_jr_qp *jr_qp)
535 int32_t jobs_no_to_notify = 0; /* the number of done jobs to notify*/
536 int32_t number_of_jobs_available = 0;
537 int32_t notified_descs_no = 0;
538 uint32_t sec_error_code = 0;
539 struct job_descriptor *current_desc;
540 phys_addr_t current_desc_addr;
541 phys_addr_t *temp_addr;
542 struct caam_jr_op_ctx *ctx;
544 /* TODO check for ops have memory*/
545 /* check here if any JR error that cannot be written
546 * in the output status word has occurred
548 if (JR_REG_JRINT_JRE_EXTRACT(GET_JR_REG(JRINT, job_ring))) {
549 CAAM_JR_INFO("err received");
550 sec_error_code = JR_REG_JRINT_ERR_TYPE_EXTRACT(
551 GET_JR_REG(JRINT, job_ring));
552 if (unlikely(sec_error_code)) {
553 hw_job_ring_error_print(job_ring, sec_error_code);
557 /* compute the number of jobs available in the job ring based on the
558 * producer and consumer index values.
560 number_of_jobs_available = hw_get_no_finished_jobs(job_ring);
561 /* Compute the number of notifications that need to be raised to UA
562 * If limit > total number of done jobs -> notify all done jobs
563 * If limit = 0 -> error
564 * If limit < total number of done jobs -> notify a number
565 * of done jobs equal with limit
567 jobs_no_to_notify = (limit > number_of_jobs_available) ?
568 number_of_jobs_available : limit;
570 "Jr[%p] pi[%d] ci[%d].limit =%d Available=%d.Jobs to notify=%d",
571 job_ring, job_ring->pidx, job_ring->cidx,
572 limit, number_of_jobs_available, jobs_no_to_notify);
576 while (jobs_no_to_notify > notified_descs_no) {
577 static uint64_t false_alarm;
578 static uint64_t real_poll;
580 /* Get job status here */
581 sec_error_code = job_ring->output_ring[job_ring->cidx].status;
582 /* Get completed descriptor */
583 temp_addr = &(job_ring->output_ring[job_ring->cidx].desc);
584 current_desc_addr = (phys_addr_t)sec_read_addr(temp_addr);
587 /* todo check if it is false alarm no desc present */
588 if (!current_desc_addr) {
590 printf("false alarm %" PRIu64 "real %" PRIu64
591 " sec_err =0x%x cidx Index =0%d\n",
592 false_alarm, real_poll,
593 sec_error_code, job_ring->cidx);
594 rte_panic("CAAM JR descriptor NULL");
595 return notified_descs_no;
597 current_desc = (struct job_descriptor *)
598 caam_jr_dma_ptov(current_desc_addr);
599 /* now increment the consumer index for the current job ring,
600 * AFTER saving job in temporary location!
602 job_ring->cidx = SEC_CIRCULAR_COUNTER(job_ring->cidx,
604 /* Signal that the job has been processed and the slot is free*/
605 hw_remove_entries(job_ring, 1);
606 /*TODO for multiple ops, packets*/
607 ctx = container_of(current_desc, struct caam_jr_op_ctx, jobdes);
608 if (unlikely(sec_error_code)) {
609 CAAM_JR_ERR("desc at cidx %d generated error 0x%x\n",
610 job_ring->cidx, sec_error_code);
611 hw_handle_job_ring_error(job_ring, sec_error_code);
612 //todo improve with exact errors
613 ctx->op->status = RTE_CRYPTO_OP_STATUS_ERROR;
616 ctx->op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
618 if (ctx->op->sym->m_dst) {
619 rte_hexdump(stdout, "PROCESSED",
620 rte_pktmbuf_mtod(ctx->op->sym->m_dst, void *),
621 rte_pktmbuf_data_len(ctx->op->sym->m_dst));
623 rte_hexdump(stdout, "PROCESSED",
624 rte_pktmbuf_mtod(ctx->op->sym->m_src, void *),
625 rte_pktmbuf_data_len(ctx->op->sym->m_src));
629 if (ctx->op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
632 if (ctx->op->sym->m_dst) {
633 /*TODO check for ip header or other*/
634 ip4_hdr = (struct ip *)
635 rte_pktmbuf_mtod(ctx->op->sym->m_dst, char*);
636 ctx->op->sym->m_dst->pkt_len =
637 rte_be_to_cpu_16(ip4_hdr->ip_len);
638 ctx->op->sym->m_dst->data_len =
639 rte_be_to_cpu_16(ip4_hdr->ip_len);
641 ip4_hdr = (struct ip *)
642 rte_pktmbuf_mtod(ctx->op->sym->m_src, char*);
643 ctx->op->sym->m_src->pkt_len =
644 rte_be_to_cpu_16(ip4_hdr->ip_len);
645 ctx->op->sym->m_src->data_len =
646 rte_be_to_cpu_16(ip4_hdr->ip_len);
650 caam_jr_op_ending(ctx);
654 return notified_descs_no;
658 caam_jr_dequeue_burst(void *qp, struct rte_crypto_op **ops,
661 struct caam_jr_qp *jr_qp = (struct caam_jr_qp *)qp;
662 struct sec_job_ring_t *ring = jr_qp->ring;
666 CAAM_JR_DP_DEBUG("Jr[%p]Polling. limit[%d]", ring, nb_ops);
669 * If nb_ops < 0 -> poll JR until no more notifications are available.
670 * If nb_ops > 0 -> poll JR until limit is reached.
673 /* Run hw poll job ring */
674 num_rx = hw_poll_job_ring(ring, ops, nb_ops, jr_qp);
676 CAAM_JR_ERR("Error polling SEC engine (%d)", num_rx);
680 CAAM_JR_DP_DEBUG("Jr[%p].Jobs notified[%d]. ", ring, num_rx);
682 if (ring->jr_mode == SEC_NOTIFICATION_TYPE_NAPI) {
683 if (num_rx < nb_ops) {
684 ret = caam_jr_enable_irqs(ring->irq_fd);
685 SEC_ASSERT(ret == 0, ret,
686 "Failed to enable irqs for job ring %p", ring);
688 } else if (ring->jr_mode == SEC_NOTIFICATION_TYPE_IRQ) {
690 /* Always enable IRQ generation when in pure IRQ mode */
691 ret = caam_jr_enable_irqs(ring->irq_fd);
692 SEC_ASSERT(ret == 0, ret,
693 "Failed to enable irqs for job ring %p", ring);
696 jr_qp->rx_pkts += num_rx;
703 * |<----data_len------->|
704 * |ip_header|ah_header|icv|payload|
709 static inline struct caam_jr_op_ctx *
710 build_auth_only_sg(struct rte_crypto_op *op, struct caam_jr_session *ses)
712 struct rte_crypto_sym_op *sym = op->sym;
713 struct rte_mbuf *mbuf = sym->m_src;
714 struct caam_jr_op_ctx *ctx;
715 struct sec4_sg_entry *sg;
718 uint64_t sdesc_offset;
719 struct sec_job_descriptor_t *jobdescr;
727 if ((mbuf->nb_segs + extra_segs) > MAX_SG_ENTRIES) {
728 CAAM_JR_DP_ERR("Auth: Max sec segs supported is %d",
733 ctx = caam_jr_alloc_ctx(ses);
740 sdesc_offset = (size_t) ((char *)&cdb->sh_desc - (char *)cdb);
742 jobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc;
744 SEC_JD_INIT(jobdescr);
745 SEC_JD_SET_SD(jobdescr,
746 (phys_addr_t)(caam_jr_dma_vtop(cdb)) + sdesc_offset,
747 cdb->sh_hdr.hi.field.idlen);
750 SEC_JD_SET_OUT_PTR(jobdescr, (uint64_t)sym->auth.digest.phys_addr,
751 0, ses->digest_length);
755 length = sym->auth.data.length;
756 sg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf) + sym->auth.data.offset);
757 sg->len = cpu_to_caam32(mbuf->data_len - sym->auth.data.offset);
759 /* Successive segs */
763 sg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf));
764 sg->len = cpu_to_caam32(mbuf->data_len);
768 if (is_decode(ses)) {
769 /* digest verification case */
771 /* hash result or digest, save digest first */
772 rte_memcpy(ctx->digest, sym->auth.digest.data,
775 rte_hexdump(stdout, "ICV", ctx->digest, ses->digest_length);
777 sg->ptr = cpu_to_caam64(caam_jr_vtop_ctx(ctx, ctx->digest));
778 sg->len = cpu_to_caam32(ses->digest_length);
779 length += ses->digest_length;
781 sg->len -= ses->digest_length;
785 sg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
787 SEC_JD_SET_IN_PTR(jobdescr,
788 (uint64_t)caam_jr_vtop_ctx(ctx, &ctx->sg[0]), 0, length);
789 /* enabling sg list */
790 (jobdescr)->seq_in.command.word |= 0x01000000;
795 static inline struct caam_jr_op_ctx *
796 build_auth_only(struct rte_crypto_op *op, struct caam_jr_session *ses)
798 struct rte_crypto_sym_op *sym = op->sym;
799 struct caam_jr_op_ctx *ctx;
800 struct sec4_sg_entry *sg;
801 rte_iova_t start_addr;
803 uint64_t sdesc_offset;
804 struct sec_job_descriptor_t *jobdescr;
806 ctx = caam_jr_alloc_ctx(ses);
813 sdesc_offset = (size_t) ((char *)&cdb->sh_desc - (char *)cdb);
815 start_addr = rte_pktmbuf_iova(sym->m_src);
817 jobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc;
819 SEC_JD_INIT(jobdescr);
820 SEC_JD_SET_SD(jobdescr,
821 (phys_addr_t)(caam_jr_dma_vtop(cdb)) + sdesc_offset,
822 cdb->sh_hdr.hi.field.idlen);
825 SEC_JD_SET_OUT_PTR(jobdescr, (uint64_t)sym->auth.digest.phys_addr,
826 0, ses->digest_length);
829 if (is_decode(ses)) {
831 SEC_JD_SET_IN_PTR(jobdescr,
832 (uint64_t)caam_jr_vtop_ctx(ctx, sg), 0,
833 (sym->auth.data.length + ses->digest_length));
834 /* enabling sg list */
835 (jobdescr)->seq_in.command.word |= 0x01000000;
837 /* hash result or digest, save digest first */
838 rte_memcpy(ctx->digest, sym->auth.digest.data,
840 sg->ptr = cpu_to_caam64(start_addr + sym->auth.data.offset);
841 sg->len = cpu_to_caam32(sym->auth.data.length);
844 rte_hexdump(stdout, "ICV", ctx->digest, ses->digest_length);
846 /* let's check digest by hw */
848 sg->ptr = cpu_to_caam64(caam_jr_vtop_ctx(ctx, ctx->digest));
849 sg->len = cpu_to_caam32(ses->digest_length);
851 sg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
853 SEC_JD_SET_IN_PTR(jobdescr, (uint64_t)start_addr,
854 sym->auth.data.offset, sym->auth.data.length);
859 static inline struct caam_jr_op_ctx *
860 build_cipher_only_sg(struct rte_crypto_op *op, struct caam_jr_session *ses)
862 struct rte_crypto_sym_op *sym = op->sym;
863 struct rte_mbuf *mbuf = sym->m_src;
864 struct caam_jr_op_ctx *ctx;
865 struct sec4_sg_entry *sg, *in_sg;
868 uint64_t sdesc_offset;
869 uint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
871 struct sec_job_descriptor_t *jobdescr;
876 reg_segs = mbuf->nb_segs + sym->m_src->nb_segs + 2;
879 reg_segs = mbuf->nb_segs * 2 + 2;
882 if (reg_segs > MAX_SG_ENTRIES) {
883 CAAM_JR_DP_ERR("Cipher: Max sec segs supported is %d",
888 ctx = caam_jr_alloc_ctx(ses);
894 sdesc_offset = (size_t) ((char *)&cdb->sh_desc - (char *)cdb);
896 jobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc;
898 SEC_JD_INIT(jobdescr);
899 SEC_JD_SET_SD(jobdescr,
900 (phys_addr_t)(caam_jr_dma_vtop(cdb)) + sdesc_offset,
901 cdb->sh_hdr.hi.field.idlen);
904 CAAM_JR_INFO("mbuf offset =%d, cipher offset = %d, length =%d+%d",
905 sym->m_src->data_off, sym->cipher.data.offset,
906 sym->cipher.data.length, ses->iv.length);
915 length = sym->cipher.data.length;
917 sg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf)
918 + sym->cipher.data.offset);
919 sg->len = cpu_to_caam32(mbuf->data_len - sym->cipher.data.offset);
921 /* Successive segs */
925 sg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf));
926 sg->len = cpu_to_caam32(mbuf->data_len);
930 sg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
932 SEC_JD_SET_OUT_PTR(jobdescr,
933 (uint64_t)caam_jr_vtop_ctx(ctx, &ctx->sg[0]), 0,
936 (jobdescr)->seq_out.command.word |= 0x01000000;
943 length = sym->cipher.data.length + ses->iv.length;
946 sg->ptr = cpu_to_caam64(caam_jr_dma_vtop(IV_ptr));
947 sg->len = cpu_to_caam32(ses->iv.length);
951 sg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf)
952 + sym->cipher.data.offset);
953 sg->len = cpu_to_caam32(mbuf->data_len - sym->cipher.data.offset);
955 /* Successive segs */
959 sg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf));
960 sg->len = cpu_to_caam32(mbuf->data_len);
964 sg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
967 SEC_JD_SET_IN_PTR(jobdescr, (uint64_t)caam_jr_vtop_ctx(ctx, in_sg), 0,
970 (jobdescr)->seq_in.command.word |= 0x01000000;
975 static inline struct caam_jr_op_ctx *
976 build_cipher_only(struct rte_crypto_op *op, struct caam_jr_session *ses)
978 struct rte_crypto_sym_op *sym = op->sym;
979 struct caam_jr_op_ctx *ctx;
980 struct sec4_sg_entry *sg;
981 rte_iova_t src_start_addr, dst_start_addr;
983 uint64_t sdesc_offset;
984 uint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
986 struct sec_job_descriptor_t *jobdescr;
988 ctx = caam_jr_alloc_ctx(ses);
994 sdesc_offset = (size_t) ((char *)&cdb->sh_desc - (char *)cdb);
996 src_start_addr = rte_pktmbuf_iova(sym->m_src);
998 dst_start_addr = rte_pktmbuf_iova(sym->m_dst);
1000 dst_start_addr = src_start_addr;
1002 jobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc;
1004 SEC_JD_INIT(jobdescr);
1005 SEC_JD_SET_SD(jobdescr,
1006 (phys_addr_t)(caam_jr_dma_vtop(cdb)) + sdesc_offset,
1007 cdb->sh_hdr.hi.field.idlen);
1010 CAAM_JR_INFO("mbuf offset =%d, cipher offset = %d, length =%d+%d",
1011 sym->m_src->data_off, sym->cipher.data.offset,
1012 sym->cipher.data.length, ses->iv.length);
1015 SEC_JD_SET_OUT_PTR(jobdescr, (uint64_t)dst_start_addr,
1016 sym->cipher.data.offset,
1017 sym->cipher.data.length + ses->iv.length);
1021 SEC_JD_SET_IN_PTR(jobdescr, (uint64_t)caam_jr_vtop_ctx(ctx, sg), 0,
1022 sym->cipher.data.length + ses->iv.length);
1023 /*enabling sg bit */
1024 (jobdescr)->seq_in.command.word |= 0x01000000;
1026 sg->ptr = cpu_to_caam64(caam_jr_dma_vtop(IV_ptr));
1027 sg->len = cpu_to_caam32(ses->iv.length);
1030 sg->ptr = cpu_to_caam64(src_start_addr + sym->cipher.data.offset);
1031 sg->len = cpu_to_caam32(sym->cipher.data.length);
1033 sg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
1038 /* For decapsulation:
1040 * +----+----------------+--------------------------------+-----+
1041 * | IV | Auth-only data | Authenticated & Encrypted data | ICV |
1042 * +----+----------------+--------------------------------+-----+
1044 * +----+--------------------------+
1045 * | Decrypted & authenticated data |
1046 * +----+--------------------------+
1049 static inline struct caam_jr_op_ctx *
1050 build_cipher_auth_sg(struct rte_crypto_op *op, struct caam_jr_session *ses)
1052 struct rte_crypto_sym_op *sym = op->sym;
1053 struct caam_jr_op_ctx *ctx;
1054 struct sec4_sg_entry *sg, *out_sg, *in_sg;
1055 struct rte_mbuf *mbuf;
1056 uint32_t length = 0;
1057 struct sec_cdb *cdb;
1058 uint64_t sdesc_offset;
1060 uint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
1062 struct sec_job_descriptor_t *jobdescr;
1063 uint16_t auth_hdr_len = sym->cipher.data.offset -
1064 sym->auth.data.offset;
1065 uint16_t auth_tail_len = sym->auth.data.length -
1066 sym->cipher.data.length - auth_hdr_len;
1067 uint32_t auth_only_len = (auth_tail_len << 16) | auth_hdr_len;
1071 req_segs = mbuf->nb_segs + sym->m_src->nb_segs + 3;
1074 req_segs = mbuf->nb_segs * 2 + 3;
1077 if (req_segs > MAX_SG_ENTRIES) {
1078 CAAM_JR_DP_ERR("Cipher-Auth: Max sec segs supported is %d",
1083 ctx = caam_jr_alloc_ctx(ses);
1089 sdesc_offset = (size_t) ((char *)&cdb->sh_desc - (char *)cdb);
1091 jobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc;
1093 SEC_JD_INIT(jobdescr);
1094 SEC_JD_SET_SD(jobdescr,
1095 (phys_addr_t)(caam_jr_dma_vtop(cdb)) + sdesc_offset,
1096 cdb->sh_hdr.hi.field.idlen);
1104 out_sg = &ctx->sg[0];
1106 length = sym->auth.data.length + ses->digest_length;
1108 length = sym->auth.data.length;
1113 sg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf)
1114 + sym->auth.data.offset);
1115 sg->len = cpu_to_caam32(mbuf->data_len - sym->auth.data.offset);
1117 /* Successive segs */
1121 sg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf));
1122 sg->len = cpu_to_caam32(mbuf->data_len);
1126 if (is_encode(ses)) {
1127 /* set auth output */
1129 sg->ptr = cpu_to_caam64(sym->auth.digest.phys_addr);
1130 sg->len = cpu_to_caam32(ses->digest_length);
1133 sg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
1135 SEC_JD_SET_OUT_PTR(jobdescr,
1136 (uint64_t)caam_jr_dma_vtop(out_sg), 0, length);
1138 (jobdescr)->seq_out.command.word |= 0x01000000;
1145 length = ses->iv.length + sym->auth.data.length;
1147 length = ses->iv.length + sym->auth.data.length
1148 + ses->digest_length;
1150 sg->ptr = cpu_to_caam64(caam_jr_dma_vtop(IV_ptr));
1151 sg->len = cpu_to_caam32(ses->iv.length);
1155 sg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf)
1156 + sym->auth.data.offset);
1157 sg->len = cpu_to_caam32(mbuf->data_len - sym->auth.data.offset);
1159 /* Successive segs */
1163 sg->ptr = cpu_to_caam64(rte_pktmbuf_iova(mbuf));
1164 sg->len = cpu_to_caam32(mbuf->data_len);
1168 if (is_decode(ses)) {
1170 rte_memcpy(ctx->digest, sym->auth.digest.data,
1171 ses->digest_length);
1172 sg->ptr = cpu_to_caam64(caam_jr_dma_vtop(ctx->digest));
1173 sg->len = cpu_to_caam32(ses->digest_length);
1176 sg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
1178 SEC_JD_SET_IN_PTR(jobdescr, (uint64_t)caam_jr_dma_vtop(in_sg), 0,
1181 (jobdescr)->seq_in.command.word |= 0x01000000;
1182 /* Auth_only_len is set as 0 in descriptor and it is
1183 * overwritten here in the jd which will update
1188 (jobdescr)->dpovrd = 0x80000000 | auth_only_len;
1193 static inline struct caam_jr_op_ctx *
1194 build_cipher_auth(struct rte_crypto_op *op, struct caam_jr_session *ses)
1196 struct rte_crypto_sym_op *sym = op->sym;
1197 struct caam_jr_op_ctx *ctx;
1198 struct sec4_sg_entry *sg;
1199 rte_iova_t src_start_addr, dst_start_addr;
1200 uint32_t length = 0;
1201 struct sec_cdb *cdb;
1202 uint64_t sdesc_offset;
1203 uint8_t *IV_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
1205 struct sec_job_descriptor_t *jobdescr;
1206 uint16_t auth_hdr_len = sym->cipher.data.offset -
1207 sym->auth.data.offset;
1208 uint16_t auth_tail_len = sym->auth.data.length -
1209 sym->cipher.data.length - auth_hdr_len;
1210 uint32_t auth_only_len = (auth_tail_len << 16) | auth_hdr_len;
1212 src_start_addr = rte_pktmbuf_iova(sym->m_src);
1214 dst_start_addr = rte_pktmbuf_iova(sym->m_dst);
1216 dst_start_addr = src_start_addr;
1218 ctx = caam_jr_alloc_ctx(ses);
1224 sdesc_offset = (size_t) ((char *)&cdb->sh_desc - (char *)cdb);
1226 jobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc;
1228 SEC_JD_INIT(jobdescr);
1229 SEC_JD_SET_SD(jobdescr,
1230 (phys_addr_t)(caam_jr_dma_vtop(cdb)) + sdesc_offset,
1231 cdb->sh_hdr.hi.field.idlen);
1235 if (is_encode(ses)) {
1236 sg->ptr = cpu_to_caam64(caam_jr_dma_vtop(IV_ptr));
1237 sg->len = cpu_to_caam32(ses->iv.length);
1238 length += ses->iv.length;
1241 sg->ptr = cpu_to_caam64(src_start_addr + sym->auth.data.offset);
1242 sg->len = cpu_to_caam32(sym->auth.data.length);
1243 length += sym->auth.data.length;
1245 sg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
1247 sg->ptr = cpu_to_caam64(caam_jr_dma_vtop(IV_ptr));
1248 sg->len = cpu_to_caam32(ses->iv.length);
1249 length += ses->iv.length;
1252 sg->ptr = cpu_to_caam64(src_start_addr + sym->auth.data.offset);
1253 sg->len = cpu_to_caam32(sym->auth.data.length);
1254 length += sym->auth.data.length;
1256 rte_memcpy(ctx->digest, sym->auth.digest.data,
1257 ses->digest_length);
1259 sg->ptr = cpu_to_caam64(caam_jr_dma_vtop(ctx->digest));
1260 sg->len = cpu_to_caam32(ses->digest_length);
1261 length += ses->digest_length;
1263 sg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
1266 SEC_JD_SET_IN_PTR(jobdescr, (uint64_t)caam_jr_dma_vtop(&ctx->sg[0]), 0,
1269 (jobdescr)->seq_in.command.word |= 0x01000000;
1274 sg->ptr = cpu_to_caam64(dst_start_addr + sym->cipher.data.offset);
1275 sg->len = cpu_to_caam32(sym->cipher.data.length);
1276 length = sym->cipher.data.length;
1278 if (is_encode(ses)) {
1279 /* set auth output */
1281 sg->ptr = cpu_to_caam64(sym->auth.digest.phys_addr);
1282 sg->len = cpu_to_caam32(ses->digest_length);
1283 length += ses->digest_length;
1286 sg->len |= cpu_to_caam32(SEC4_SG_LEN_FIN);
1288 SEC_JD_SET_OUT_PTR(jobdescr,
1289 (uint64_t)caam_jr_dma_vtop(&ctx->sg[6]), 0, length);
1291 (jobdescr)->seq_out.command.word |= 0x01000000;
1293 /* Auth_only_len is set as 0 in descriptor and it is
1294 * overwritten here in the jd which will update
1299 (jobdescr)->dpovrd = 0x80000000 | auth_only_len;
1304 static inline struct caam_jr_op_ctx *
1305 build_proto(struct rte_crypto_op *op, struct caam_jr_session *ses)
1307 struct rte_crypto_sym_op *sym = op->sym;
1308 struct caam_jr_op_ctx *ctx = NULL;
1309 phys_addr_t src_start_addr, dst_start_addr;
1310 struct sec_cdb *cdb;
1311 uint64_t sdesc_offset;
1312 struct sec_job_descriptor_t *jobdescr;
1314 ctx = caam_jr_alloc_ctx(ses);
1319 src_start_addr = rte_pktmbuf_iova(sym->m_src);
1321 dst_start_addr = rte_pktmbuf_iova(sym->m_dst);
1323 dst_start_addr = src_start_addr;
1326 sdesc_offset = (size_t) ((char *)&cdb->sh_desc - (char *)cdb);
1328 jobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc;
1330 SEC_JD_INIT(jobdescr);
1331 SEC_JD_SET_SD(jobdescr,
1332 (phys_addr_t)(caam_jr_dma_vtop(cdb)) + sdesc_offset,
1333 cdb->sh_hdr.hi.field.idlen);
1336 SEC_JD_SET_OUT_PTR(jobdescr, (uint64_t)dst_start_addr, 0,
1337 sym->m_src->buf_len - sym->m_src->data_off);
1339 SEC_JD_SET_IN_PTR(jobdescr, (uint64_t)src_start_addr, 0,
1340 sym->m_src->pkt_len);
1341 sym->m_src->packet_type &= ~RTE_PTYPE_L4_MASK;
1347 caam_jr_enqueue_op(struct rte_crypto_op *op, struct caam_jr_qp *qp)
1349 struct sec_job_ring_t *ring = qp->ring;
1350 struct caam_jr_session *ses;
1351 struct caam_jr_op_ctx *ctx = NULL;
1352 struct sec_job_descriptor_t *jobdescr __rte_unused;
1357 switch (op->sess_type) {
1358 case RTE_CRYPTO_OP_WITH_SESSION:
1359 ses = (struct caam_jr_session *)
1360 get_sym_session_private_data(op->sym->session,
1361 cryptodev_driver_id);
1363 case RTE_CRYPTO_OP_SECURITY_SESSION:
1364 ses = (struct caam_jr_session *)
1365 get_sec_session_private_data(
1366 op->sym->sec_session);
1369 CAAM_JR_DP_ERR("sessionless crypto op not supported");
1374 if (unlikely(!ses->qp || ses->qp != qp)) {
1375 CAAM_JR_DP_DEBUG("Old:sess->qp=%p New qp = %p\n", ses->qp, qp);
1377 caam_jr_prep_cdb(ses);
1380 if (rte_pktmbuf_is_contiguous(op->sym->m_src)) {
1381 if (is_auth_cipher(ses))
1382 ctx = build_cipher_auth(op, ses);
1383 else if (is_aead(ses))
1385 else if (is_auth_only(ses))
1386 ctx = build_auth_only(op, ses);
1387 else if (is_cipher_only(ses))
1388 ctx = build_cipher_only(op, ses);
1389 else if (is_proto_ipsec(ses))
1390 ctx = build_proto(op, ses);
1392 if (is_auth_cipher(ses))
1393 ctx = build_cipher_auth_sg(op, ses);
1394 else if (is_aead(ses))
1396 else if (is_auth_only(ses))
1397 ctx = build_auth_only_sg(op, ses);
1398 else if (is_cipher_only(ses))
1399 ctx = build_cipher_only_sg(op, ses);
1402 if (unlikely(!ctx)) {
1404 CAAM_JR_ERR("not supported sec op");
1409 rte_hexdump(stdout, "DECODE",
1410 rte_pktmbuf_mtod(op->sym->m_src, void *),
1411 rte_pktmbuf_data_len(op->sym->m_src));
1413 rte_hexdump(stdout, "ENCODE",
1414 rte_pktmbuf_mtod(op->sym->m_src, void *),
1415 rte_pktmbuf_data_len(op->sym->m_src));
1417 printf("\n JD before conversion\n");
1418 for (i = 0; i < 12; i++)
1419 printf("\n 0x%08x", ctx->jobdes.desc[i]);
1422 CAAM_JR_DP_DEBUG("Jr[%p] pi[%d] ci[%d].Before sending desc",
1423 ring, ring->pidx, ring->cidx);
1425 /* todo - do we want to retry */
1426 if (SEC_JOB_RING_IS_FULL(ring->pidx, ring->cidx,
1427 SEC_JOB_RING_SIZE, SEC_JOB_RING_SIZE)) {
1428 CAAM_JR_DP_DEBUG("Ring FULL Jr[%p] pi[%d] ci[%d].Size = %d",
1429 ring, ring->pidx, ring->cidx, SEC_JOB_RING_SIZE);
1430 caam_jr_op_ending(ctx);
1435 #if CORE_BYTE_ORDER != CAAM_BYTE_ORDER
1436 jobdescr = (struct sec_job_descriptor_t *) ctx->jobdes.desc;
1438 jobdescr->deschdr.command.word =
1439 cpu_to_caam32(jobdescr->deschdr.command.word);
1440 jobdescr->sd_ptr = cpu_to_caam64(jobdescr->sd_ptr);
1441 jobdescr->seq_out.command.word =
1442 cpu_to_caam32(jobdescr->seq_out.command.word);
1443 jobdescr->seq_out_ptr = cpu_to_caam64(jobdescr->seq_out_ptr);
1444 jobdescr->out_ext_length = cpu_to_caam32(jobdescr->out_ext_length);
1445 jobdescr->seq_in.command.word =
1446 cpu_to_caam32(jobdescr->seq_in.command.word);
1447 jobdescr->seq_in_ptr = cpu_to_caam64(jobdescr->seq_in_ptr);
1448 jobdescr->in_ext_length = cpu_to_caam32(jobdescr->in_ext_length);
1449 jobdescr->load_dpovrd.command.word =
1450 cpu_to_caam32(jobdescr->load_dpovrd.command.word);
1451 jobdescr->dpovrd = cpu_to_caam32(jobdescr->dpovrd);
1454 /* Set ptr in input ring to current descriptor */
1455 sec_write_addr(&ring->input_ring[ring->pidx],
1456 (phys_addr_t)caam_jr_vtop_ctx(ctx, ctx->jobdes.desc));
1459 /* Notify HW that a new job is enqueued */
1460 hw_enqueue_desc_on_job_ring(ring);
1462 /* increment the producer index for the current job ring */
1463 ring->pidx = SEC_CIRCULAR_COUNTER(ring->pidx, SEC_JOB_RING_SIZE);
1469 caam_jr_enqueue_burst(void *qp, struct rte_crypto_op **ops,
1472 /* Function to transmit the frames to given device and queuepair */
1475 struct caam_jr_qp *jr_qp = (struct caam_jr_qp *)qp;
1476 uint16_t num_tx = 0;
1477 /*Prepare each packet which is to be sent*/
1478 for (loop = 0; loop < nb_ops; loop++) {
1479 ret = caam_jr_enqueue_op(ops[loop], jr_qp);
1484 jr_qp->tx_pkts += num_tx;
1489 /* Release queue pair */
1491 caam_jr_queue_pair_release(struct rte_cryptodev *dev,
1494 struct sec_job_ring_t *internals;
1495 struct caam_jr_qp *qp = NULL;
1497 PMD_INIT_FUNC_TRACE();
1498 CAAM_JR_DEBUG("dev =%p, queue =%d", dev, qp_id);
1500 internals = dev->data->dev_private;
1501 if (qp_id >= internals->max_nb_queue_pairs) {
1502 CAAM_JR_ERR("Max supported qpid %d",
1503 internals->max_nb_queue_pairs);
1507 qp = &internals->qps[qp_id];
1509 dev->data->queue_pairs[qp_id] = NULL;
1514 /* Setup a queue pair */
1516 caam_jr_queue_pair_setup(
1517 struct rte_cryptodev *dev, uint16_t qp_id,
1518 __rte_unused const struct rte_cryptodev_qp_conf *qp_conf,
1519 __rte_unused int socket_id)
1521 struct sec_job_ring_t *internals;
1522 struct caam_jr_qp *qp = NULL;
1524 PMD_INIT_FUNC_TRACE();
1525 CAAM_JR_DEBUG("dev =%p, queue =%d, conf =%p", dev, qp_id, qp_conf);
1527 internals = dev->data->dev_private;
1528 if (qp_id >= internals->max_nb_queue_pairs) {
1529 CAAM_JR_ERR("Max supported qpid %d",
1530 internals->max_nb_queue_pairs);
1534 qp = &internals->qps[qp_id];
1535 qp->ring = internals;
1536 dev->data->queue_pairs[qp_id] = qp;
1541 /* Returns the size of the aesni gcm session structure */
1543 caam_jr_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
1545 PMD_INIT_FUNC_TRACE();
1547 return sizeof(struct caam_jr_session);
1551 caam_jr_cipher_init(struct rte_cryptodev *dev __rte_unused,
1552 struct rte_crypto_sym_xform *xform,
1553 struct caam_jr_session *session)
1555 session->cipher_alg = xform->cipher.algo;
1556 session->iv.length = xform->cipher.iv.length;
1557 session->iv.offset = xform->cipher.iv.offset;
1558 session->cipher_key.data = rte_zmalloc(NULL, xform->cipher.key.length,
1559 RTE_CACHE_LINE_SIZE);
1560 if (session->cipher_key.data == NULL && xform->cipher.key.length > 0) {
1561 CAAM_JR_ERR("No Memory for cipher key\n");
1564 session->cipher_key.length = xform->cipher.key.length;
1566 memcpy(session->cipher_key.data, xform->cipher.key.data,
1567 xform->cipher.key.length);
1568 session->dir = (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ?
1575 caam_jr_auth_init(struct rte_cryptodev *dev __rte_unused,
1576 struct rte_crypto_sym_xform *xform,
1577 struct caam_jr_session *session)
1579 session->auth_alg = xform->auth.algo;
1580 session->auth_key.data = rte_zmalloc(NULL, xform->auth.key.length,
1581 RTE_CACHE_LINE_SIZE);
1582 if (session->auth_key.data == NULL && xform->auth.key.length > 0) {
1583 CAAM_JR_ERR("No Memory for auth key\n");
1586 session->auth_key.length = xform->auth.key.length;
1587 session->digest_length = xform->auth.digest_length;
1589 memcpy(session->auth_key.data, xform->auth.key.data,
1590 xform->auth.key.length);
1591 session->dir = (xform->auth.op == RTE_CRYPTO_AUTH_OP_GENERATE) ?
1598 caam_jr_aead_init(struct rte_cryptodev *dev __rte_unused,
1599 struct rte_crypto_sym_xform *xform,
1600 struct caam_jr_session *session)
1602 session->aead_alg = xform->aead.algo;
1603 session->iv.length = xform->aead.iv.length;
1604 session->iv.offset = xform->aead.iv.offset;
1605 session->auth_only_len = xform->aead.aad_length;
1606 session->aead_key.data = rte_zmalloc(NULL, xform->aead.key.length,
1607 RTE_CACHE_LINE_SIZE);
1608 if (session->aead_key.data == NULL && xform->aead.key.length > 0) {
1609 CAAM_JR_ERR("No Memory for aead key\n");
1612 session->aead_key.length = xform->aead.key.length;
1613 session->digest_length = xform->aead.digest_length;
1615 memcpy(session->aead_key.data, xform->aead.key.data,
1616 xform->aead.key.length);
1617 session->dir = (xform->aead.op == RTE_CRYPTO_AEAD_OP_ENCRYPT) ?
1624 caam_jr_set_session_parameters(struct rte_cryptodev *dev,
1625 struct rte_crypto_sym_xform *xform, void *sess)
1627 struct sec_job_ring_t *internals = dev->data->dev_private;
1628 struct caam_jr_session *session = sess;
1630 PMD_INIT_FUNC_TRACE();
1632 if (unlikely(sess == NULL)) {
1633 CAAM_JR_ERR("invalid session struct");
1637 /* Default IV length = 0 */
1638 session->iv.length = 0;
1641 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL) {
1642 session->auth_alg = RTE_CRYPTO_AUTH_NULL;
1643 caam_jr_cipher_init(dev, xform, session);
1645 /* Authentication Only */
1646 } else if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
1647 xform->next == NULL) {
1648 session->cipher_alg = RTE_CRYPTO_CIPHER_NULL;
1649 caam_jr_auth_init(dev, xform, session);
1651 /* Cipher then Authenticate */
1652 } else if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
1653 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
1654 if (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) {
1655 caam_jr_cipher_init(dev, xform, session);
1656 caam_jr_auth_init(dev, xform->next, session);
1658 CAAM_JR_ERR("Not supported: Auth then Cipher");
1662 /* Authenticate then Cipher */
1663 } else if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
1664 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {
1665 if (xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT) {
1666 caam_jr_auth_init(dev, xform, session);
1667 caam_jr_cipher_init(dev, xform->next, session);
1669 CAAM_JR_ERR("Not supported: Auth then Cipher");
1673 /* AEAD operation for AES-GCM kind of Algorithms */
1674 } else if (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD &&
1675 xform->next == NULL) {
1676 caam_jr_aead_init(dev, xform, session);
1679 CAAM_JR_ERR("Invalid crypto type");
1682 session->ctx_pool = internals->ctx_pool;
1687 rte_free(session->cipher_key.data);
1688 rte_free(session->auth_key.data);
1689 memset(session, 0, sizeof(struct caam_jr_session));
1695 caam_jr_sym_session_configure(struct rte_cryptodev *dev,
1696 struct rte_crypto_sym_xform *xform,
1697 struct rte_cryptodev_sym_session *sess,
1698 struct rte_mempool *mempool)
1700 void *sess_private_data;
1703 PMD_INIT_FUNC_TRACE();
1705 if (rte_mempool_get(mempool, &sess_private_data)) {
1706 CAAM_JR_ERR("Couldn't get object from session mempool");
1710 memset(sess_private_data, 0, sizeof(struct caam_jr_session));
1711 ret = caam_jr_set_session_parameters(dev, xform, sess_private_data);
1713 CAAM_JR_ERR("failed to configure session parameters");
1714 /* Return session to mempool */
1715 rte_mempool_put(mempool, sess_private_data);
1719 set_sym_session_private_data(sess, dev->driver_id, sess_private_data);
1724 /* Clear the memory of session so it doesn't leave key material behind */
1726 caam_jr_sym_session_clear(struct rte_cryptodev *dev,
1727 struct rte_cryptodev_sym_session *sess)
1729 uint8_t index = dev->driver_id;
1730 void *sess_priv = get_sym_session_private_data(sess, index);
1731 struct caam_jr_session *s = (struct caam_jr_session *)sess_priv;
1733 PMD_INIT_FUNC_TRACE();
1736 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
1738 rte_free(s->cipher_key.data);
1739 rte_free(s->auth_key.data);
1740 memset(s, 0, sizeof(struct caam_jr_session));
1741 set_sym_session_private_data(sess, index, NULL);
1742 rte_mempool_put(sess_mp, sess_priv);
1747 caam_jr_set_ipsec_session(__rte_unused struct rte_cryptodev *dev,
1748 struct rte_security_session_conf *conf,
1751 struct sec_job_ring_t *internals = dev->data->dev_private;
1752 struct rte_security_ipsec_xform *ipsec_xform = &conf->ipsec;
1753 struct rte_crypto_auth_xform *auth_xform;
1754 struct rte_crypto_cipher_xform *cipher_xform;
1755 struct caam_jr_session *session = (struct caam_jr_session *)sess;
1757 PMD_INIT_FUNC_TRACE();
1759 if (ipsec_xform->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS) {
1760 cipher_xform = &conf->crypto_xform->cipher;
1761 auth_xform = &conf->crypto_xform->next->auth;
1763 auth_xform = &conf->crypto_xform->auth;
1764 cipher_xform = &conf->crypto_xform->next->cipher;
1766 session->proto_alg = conf->protocol;
1767 session->cipher_key.data = rte_zmalloc(NULL,
1768 cipher_xform->key.length,
1769 RTE_CACHE_LINE_SIZE);
1770 if (session->cipher_key.data == NULL &&
1771 cipher_xform->key.length > 0) {
1772 CAAM_JR_ERR("No Memory for cipher key\n");
1776 session->cipher_key.length = cipher_xform->key.length;
1777 session->auth_key.data = rte_zmalloc(NULL,
1778 auth_xform->key.length,
1779 RTE_CACHE_LINE_SIZE);
1780 if (session->auth_key.data == NULL &&
1781 auth_xform->key.length > 0) {
1782 CAAM_JR_ERR("No Memory for auth key\n");
1783 rte_free(session->cipher_key.data);
1786 session->auth_key.length = auth_xform->key.length;
1787 memcpy(session->cipher_key.data, cipher_xform->key.data,
1788 cipher_xform->key.length);
1789 memcpy(session->auth_key.data, auth_xform->key.data,
1790 auth_xform->key.length);
1792 switch (auth_xform->algo) {
1793 case RTE_CRYPTO_AUTH_SHA1_HMAC:
1794 session->auth_alg = RTE_CRYPTO_AUTH_SHA1_HMAC;
1796 case RTE_CRYPTO_AUTH_MD5_HMAC:
1797 session->auth_alg = RTE_CRYPTO_AUTH_MD5_HMAC;
1799 case RTE_CRYPTO_AUTH_SHA256_HMAC:
1800 session->auth_alg = RTE_CRYPTO_AUTH_SHA256_HMAC;
1802 case RTE_CRYPTO_AUTH_SHA384_HMAC:
1803 session->auth_alg = RTE_CRYPTO_AUTH_SHA384_HMAC;
1805 case RTE_CRYPTO_AUTH_SHA512_HMAC:
1806 session->auth_alg = RTE_CRYPTO_AUTH_SHA512_HMAC;
1808 case RTE_CRYPTO_AUTH_AES_CMAC:
1809 session->auth_alg = RTE_CRYPTO_AUTH_AES_CMAC;
1811 case RTE_CRYPTO_AUTH_NULL:
1812 session->auth_alg = RTE_CRYPTO_AUTH_NULL;
1814 case RTE_CRYPTO_AUTH_SHA224_HMAC:
1815 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
1816 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
1817 case RTE_CRYPTO_AUTH_SHA1:
1818 case RTE_CRYPTO_AUTH_SHA256:
1819 case RTE_CRYPTO_AUTH_SHA512:
1820 case RTE_CRYPTO_AUTH_SHA224:
1821 case RTE_CRYPTO_AUTH_SHA384:
1822 case RTE_CRYPTO_AUTH_MD5:
1823 case RTE_CRYPTO_AUTH_AES_GMAC:
1824 case RTE_CRYPTO_AUTH_KASUMI_F9:
1825 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
1826 case RTE_CRYPTO_AUTH_ZUC_EIA3:
1827 CAAM_JR_ERR("Crypto: Unsupported auth alg %u\n",
1831 CAAM_JR_ERR("Crypto: Undefined Auth specified %u\n",
1836 switch (cipher_xform->algo) {
1837 case RTE_CRYPTO_CIPHER_AES_CBC:
1838 session->cipher_alg = RTE_CRYPTO_CIPHER_AES_CBC;
1840 case RTE_CRYPTO_CIPHER_3DES_CBC:
1841 session->cipher_alg = RTE_CRYPTO_CIPHER_3DES_CBC;
1843 case RTE_CRYPTO_CIPHER_AES_CTR:
1844 session->cipher_alg = RTE_CRYPTO_CIPHER_AES_CTR;
1846 case RTE_CRYPTO_CIPHER_NULL:
1847 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
1848 case RTE_CRYPTO_CIPHER_3DES_ECB:
1849 case RTE_CRYPTO_CIPHER_AES_ECB:
1850 case RTE_CRYPTO_CIPHER_KASUMI_F8:
1851 CAAM_JR_ERR("Crypto: Unsupported Cipher alg %u\n",
1852 cipher_xform->algo);
1855 CAAM_JR_ERR("Crypto: Undefined Cipher specified %u\n",
1856 cipher_xform->algo);
1860 if (ipsec_xform->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS) {
1861 memset(&session->encap_pdb, 0, sizeof(struct ipsec_encap_pdb) +
1862 sizeof(session->ip4_hdr));
1863 session->ip4_hdr.ip_v = IPVERSION;
1864 session->ip4_hdr.ip_hl = 5;
1865 session->ip4_hdr.ip_len = rte_cpu_to_be_16(
1866 sizeof(session->ip4_hdr));
1867 session->ip4_hdr.ip_tos = ipsec_xform->tunnel.ipv4.dscp;
1868 session->ip4_hdr.ip_id = 0;
1869 session->ip4_hdr.ip_off = 0;
1870 session->ip4_hdr.ip_ttl = ipsec_xform->tunnel.ipv4.ttl;
1871 session->ip4_hdr.ip_p = (ipsec_xform->proto ==
1872 RTE_SECURITY_IPSEC_SA_PROTO_ESP) ? IPPROTO_ESP
1874 session->ip4_hdr.ip_sum = 0;
1875 session->ip4_hdr.ip_src = ipsec_xform->tunnel.ipv4.src_ip;
1876 session->ip4_hdr.ip_dst = ipsec_xform->tunnel.ipv4.dst_ip;
1877 session->ip4_hdr.ip_sum = calc_chksum((uint16_t *)
1878 (void *)&session->ip4_hdr,
1881 session->encap_pdb.options =
1882 (IPVERSION << PDBNH_ESP_ENCAP_SHIFT) |
1883 PDBOPTS_ESP_OIHI_PDB_INL |
1885 PDBHMO_ESP_ENCAP_DTTL;
1886 if (ipsec_xform->options.esn)
1887 session->encap_pdb.options |= PDBOPTS_ESP_ESN;
1888 session->encap_pdb.spi = ipsec_xform->spi;
1889 session->encap_pdb.ip_hdr_len = sizeof(struct ip);
1891 session->dir = DIR_ENC;
1892 } else if (ipsec_xform->direction ==
1893 RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {
1894 memset(&session->decap_pdb, 0, sizeof(struct ipsec_decap_pdb));
1895 session->decap_pdb.options = sizeof(struct ip) << 16;
1896 if (ipsec_xform->options.esn)
1897 session->decap_pdb.options |= PDBOPTS_ESP_ESN;
1898 session->dir = DIR_DEC;
1901 session->ctx_pool = internals->ctx_pool;
1905 rte_free(session->auth_key.data);
1906 rte_free(session->cipher_key.data);
1907 memset(session, 0, sizeof(struct caam_jr_session));
1912 caam_jr_security_session_create(void *dev,
1913 struct rte_security_session_conf *conf,
1914 struct rte_security_session *sess,
1915 struct rte_mempool *mempool)
1917 void *sess_private_data;
1918 struct rte_cryptodev *cdev = (struct rte_cryptodev *)dev;
1921 if (rte_mempool_get(mempool, &sess_private_data)) {
1922 CAAM_JR_ERR("Couldn't get object from session mempool");
1926 switch (conf->protocol) {
1927 case RTE_SECURITY_PROTOCOL_IPSEC:
1928 ret = caam_jr_set_ipsec_session(cdev, conf,
1931 case RTE_SECURITY_PROTOCOL_MACSEC:
1937 CAAM_JR_ERR("failed to configure session parameters");
1938 /* Return session to mempool */
1939 rte_mempool_put(mempool, sess_private_data);
1943 set_sec_session_private_data(sess, sess_private_data);
1948 /* Clear the memory of session so it doesn't leave key material behind */
1950 caam_jr_security_session_destroy(void *dev __rte_unused,
1951 struct rte_security_session *sess)
1953 PMD_INIT_FUNC_TRACE();
1954 void *sess_priv = get_sec_session_private_data(sess);
1956 struct caam_jr_session *s = (struct caam_jr_session *)sess_priv;
1959 struct rte_mempool *sess_mp = rte_mempool_from_obj(sess_priv);
1961 rte_free(s->cipher_key.data);
1962 rte_free(s->auth_key.data);
1963 memset(sess, 0, sizeof(struct caam_jr_session));
1964 set_sec_session_private_data(sess, NULL);
1965 rte_mempool_put(sess_mp, sess_priv);
1972 caam_jr_dev_configure(struct rte_cryptodev *dev,
1973 struct rte_cryptodev_config *config __rte_unused)
1976 struct sec_job_ring_t *internals;
1978 PMD_INIT_FUNC_TRACE();
1980 internals = dev->data->dev_private;
1981 snprintf(str, sizeof(str), "ctx_pool_%d", dev->data->dev_id);
1982 if (!internals->ctx_pool) {
1983 internals->ctx_pool = rte_mempool_create((const char *)str,
1985 sizeof(struct caam_jr_op_ctx),
1986 CTX_POOL_CACHE_SIZE, 0,
1987 NULL, NULL, NULL, NULL,
1989 if (!internals->ctx_pool) {
1990 CAAM_JR_ERR("%s create failed\n", str);
1994 CAAM_JR_INFO("mempool already created for dev_id : %d",
2001 caam_jr_dev_start(struct rte_cryptodev *dev __rte_unused)
2003 PMD_INIT_FUNC_TRACE();
2008 caam_jr_dev_stop(struct rte_cryptodev *dev __rte_unused)
2010 PMD_INIT_FUNC_TRACE();
2014 caam_jr_dev_close(struct rte_cryptodev *dev)
2016 struct sec_job_ring_t *internals;
2018 PMD_INIT_FUNC_TRACE();
2023 internals = dev->data->dev_private;
2024 rte_mempool_free(internals->ctx_pool);
2025 internals->ctx_pool = NULL;
2031 caam_jr_dev_infos_get(struct rte_cryptodev *dev,
2032 struct rte_cryptodev_info *info)
2034 struct sec_job_ring_t *internals = dev->data->dev_private;
2036 PMD_INIT_FUNC_TRACE();
2038 info->max_nb_queue_pairs = internals->max_nb_queue_pairs;
2039 info->feature_flags = dev->feature_flags;
2040 info->capabilities = caam_jr_get_cryptodev_capabilities();
2041 info->sym.max_nb_sessions = internals->max_nb_sessions;
2042 info->driver_id = cryptodev_driver_id;
2046 static struct rte_cryptodev_ops caam_jr_ops = {
2047 .dev_configure = caam_jr_dev_configure,
2048 .dev_start = caam_jr_dev_start,
2049 .dev_stop = caam_jr_dev_stop,
2050 .dev_close = caam_jr_dev_close,
2051 .dev_infos_get = caam_jr_dev_infos_get,
2052 .stats_get = caam_jr_stats_get,
2053 .stats_reset = caam_jr_stats_reset,
2054 .queue_pair_setup = caam_jr_queue_pair_setup,
2055 .queue_pair_release = caam_jr_queue_pair_release,
2056 .sym_session_get_size = caam_jr_sym_session_get_size,
2057 .sym_session_configure = caam_jr_sym_session_configure,
2058 .sym_session_clear = caam_jr_sym_session_clear
2061 static struct rte_security_ops caam_jr_security_ops = {
2062 .session_create = caam_jr_security_session_create,
2063 .session_update = NULL,
2064 .session_stats_get = NULL,
2065 .session_destroy = caam_jr_security_session_destroy,
2066 .set_pkt_metadata = NULL,
2067 .capabilities_get = caam_jr_get_security_capabilities
2070 /* @brief Flush job rings of any processed descs.
2071 * The processed descs are silently dropped,
2072 * WITHOUT being notified to UA.
2075 close_job_ring(struct sec_job_ring_t *job_ring)
2077 if (job_ring->irq_fd != -1) {
2078 /* Producer index is frozen. If consumer index is not equal
2079 * with producer index, then we have descs to flush.
2081 while (job_ring->pidx != job_ring->cidx)
2082 hw_flush_job_ring(job_ring, false, NULL);
2084 /* free the uio job ring */
2085 free_job_ring(job_ring->irq_fd);
2086 job_ring->irq_fd = -1;
2087 caam_jr_dma_free(job_ring->input_ring);
2088 caam_jr_dma_free(job_ring->output_ring);
2093 /** @brief Release the software and hardware resources tied to a job ring.
2094 * @param [in] job_ring The job ring
2096 * @retval 0 for success
2097 * @retval -1 for error
2100 shutdown_job_ring(struct sec_job_ring_t *job_ring)
2104 PMD_INIT_FUNC_TRACE();
2105 ASSERT(job_ring != NULL);
2106 ret = hw_shutdown_job_ring(job_ring);
2107 SEC_ASSERT(ret == 0, ret,
2108 "Failed to shutdown hardware job ring %p",
2111 if (job_ring->coalescing_en)
2112 hw_job_ring_disable_coalescing(job_ring);
2114 if (job_ring->jr_mode != SEC_NOTIFICATION_TYPE_POLL) {
2115 ret = caam_jr_disable_irqs(job_ring->irq_fd);
2116 SEC_ASSERT(ret == 0, ret,
2117 "Failed to disable irqs for job ring %p",
2125 * @brief Release the resources used by the SEC user space driver.
2127 * Reset and release SEC's job rings indicated by the User Application at
2128 * init_job_ring() and free any memory allocated internally.
2129 * Call once during application tear down.
2131 * @note In case there are any descriptors in-flight (descriptors received by
2132 * SEC driver for processing and for which no response was yet provided to UA),
2133 * the descriptors are discarded without any notifications to User Application.
2135 * @retval ::0 is returned for a successful execution
2136 * @retval ::-1 is returned if SEC driver release is in progress
2139 caam_jr_dev_uninit(struct rte_cryptodev *dev)
2141 struct sec_job_ring_t *internals;
2143 PMD_INIT_FUNC_TRACE();
2147 internals = dev->data->dev_private;
2148 rte_free(dev->security_ctx);
2150 /* If any descriptors in flight , poll and wait
2151 * until all descriptors are received and silently discarded.
2154 shutdown_job_ring(internals);
2155 close_job_ring(internals);
2156 rte_mempool_free(internals->ctx_pool);
2159 CAAM_JR_INFO("Closing crypto device %s", dev->data->name);
2161 /* last caam jr instance) */
2162 if (g_job_rings_no == 0)
2163 g_driver_state = SEC_DRIVER_STATE_IDLE;
2168 /* @brief Initialize the software and hardware resources tied to a job ring.
2169 * @param [in] jr_mode; Model to be used by SEC Driver to receive
2170 * notifications from SEC. Can be either
2171 * of the three: #SEC_NOTIFICATION_TYPE_NAPI
2172 * #SEC_NOTIFICATION_TYPE_IRQ or
2173 * #SEC_NOTIFICATION_TYPE_POLL
2174 * @param [in] NAPI_mode The NAPI work mode to configure a job ring at
2175 * startup. Used only when #SEC_NOTIFICATION_TYPE
2176 * is set to #SEC_NOTIFICATION_TYPE_NAPI.
2177 * @param [in] irq_coalescing_timer This value determines the maximum
2178 * amount of time after processing a
2179 * descriptor before raising an interrupt.
2180 * @param [in] irq_coalescing_count This value determines how many
2181 * descriptors are completed before
2182 * raising an interrupt.
2183 * @param [in] reg_base_addr, The job ring base address register
2184 * @param [in] irq_id The job ring interrupt identification number.
2185 * @retval job_ring_handle for successful job ring configuration
2186 * @retval NULL on error
2190 init_job_ring(void *reg_base_addr, int irq_id)
2192 struct sec_job_ring_t *job_ring = NULL;
2194 int jr_mode = SEC_NOTIFICATION_TYPE_POLL;
2196 int irq_coalescing_timer = 0;
2197 int irq_coalescing_count = 0;
2199 for (i = 0; i < MAX_SEC_JOB_RINGS; i++) {
2200 if (g_job_rings[i].irq_fd == -1) {
2201 job_ring = &g_job_rings[i];
2206 if (job_ring == NULL) {
2207 CAAM_JR_ERR("No free job ring\n");
2211 job_ring->register_base_addr = reg_base_addr;
2212 job_ring->jr_mode = jr_mode;
2213 job_ring->napi_mode = 0;
2214 job_ring->irq_fd = irq_id;
2216 /* Allocate mem for input and output ring */
2218 /* Allocate memory for input ring */
2219 job_ring->input_ring = caam_jr_dma_mem_alloc(L1_CACHE_BYTES,
2220 SEC_DMA_MEM_INPUT_RING_SIZE);
2221 memset(job_ring->input_ring, 0, SEC_DMA_MEM_INPUT_RING_SIZE);
2223 /* Allocate memory for output ring */
2224 job_ring->output_ring = caam_jr_dma_mem_alloc(L1_CACHE_BYTES,
2225 SEC_DMA_MEM_OUTPUT_RING_SIZE);
2226 memset(job_ring->output_ring, 0, SEC_DMA_MEM_OUTPUT_RING_SIZE);
2228 /* Reset job ring in SEC hw and configure job ring registers */
2229 ret = hw_reset_job_ring(job_ring);
2231 CAAM_JR_ERR("Failed to reset hardware job ring");
2235 if (jr_mode == SEC_NOTIFICATION_TYPE_NAPI) {
2236 /* When SEC US driver works in NAPI mode, the UA can select
2237 * if the driver starts with IRQs on or off.
2239 if (napi_mode == SEC_STARTUP_INTERRUPT_MODE) {
2240 CAAM_JR_INFO("Enabling DONE IRQ generationon job ring - %p",
2242 ret = caam_jr_enable_irqs(job_ring->irq_fd);
2244 CAAM_JR_ERR("Failed to enable irqs for job ring");
2248 } else if (jr_mode == SEC_NOTIFICATION_TYPE_IRQ) {
2249 /* When SEC US driver works in pure interrupt mode,
2250 * IRQ's are always enabled.
2252 CAAM_JR_INFO("Enabling DONE IRQ generation on job ring - %p",
2254 ret = caam_jr_enable_irqs(job_ring->irq_fd);
2256 CAAM_JR_ERR("Failed to enable irqs for job ring");
2260 if (irq_coalescing_timer || irq_coalescing_count) {
2261 hw_job_ring_set_coalescing_param(job_ring,
2262 irq_coalescing_timer,
2263 irq_coalescing_count);
2265 hw_job_ring_enable_coalescing(job_ring);
2266 job_ring->coalescing_en = 1;
2269 job_ring->jr_state = SEC_JOB_RING_STATE_STARTED;
2270 job_ring->max_nb_queue_pairs = RTE_CAAM_MAX_NB_SEC_QPS;
2271 job_ring->max_nb_sessions = RTE_CAAM_JR_PMD_MAX_NB_SESSIONS;
2275 caam_jr_dma_free(job_ring->output_ring);
2276 caam_jr_dma_free(job_ring->input_ring);
2282 caam_jr_dev_init(const char *name,
2283 struct rte_vdev_device *vdev,
2284 struct rte_cryptodev_pmd_init_params *init_params)
2286 struct rte_cryptodev *dev;
2287 struct rte_security_ctx *security_instance;
2288 struct uio_job_ring *job_ring;
2289 char str[RTE_CRYPTODEV_NAME_MAX_LEN];
2291 PMD_INIT_FUNC_TRACE();
2293 /* Validate driver state */
2294 if (g_driver_state == SEC_DRIVER_STATE_IDLE) {
2295 g_job_rings_max = sec_configure();
2296 if (!g_job_rings_max) {
2297 CAAM_JR_ERR("No job ring detected on UIO !!!!");
2300 /* Update driver state */
2301 g_driver_state = SEC_DRIVER_STATE_STARTED;
2304 if (g_job_rings_no >= g_job_rings_max) {
2305 CAAM_JR_ERR("No more job rings available max=%d!!!!",
2310 job_ring = config_job_ring();
2311 if (job_ring == NULL) {
2312 CAAM_JR_ERR("failed to create job ring");
2316 snprintf(str, sizeof(str), "caam_jr%d", job_ring->jr_id);
2318 dev = rte_cryptodev_pmd_create(name, &vdev->device, init_params);
2320 CAAM_JR_ERR("failed to create cryptodev vdev");
2323 /*TODO free it during teardown*/
2324 dev->data->dev_private = init_job_ring(job_ring->register_base_addr,
2327 if (!dev->data->dev_private) {
2328 CAAM_JR_ERR("Ring memory allocation failed\n");
2332 dev->driver_id = cryptodev_driver_id;
2333 dev->dev_ops = &caam_jr_ops;
2335 /* register rx/tx burst functions for data path */
2336 dev->dequeue_burst = caam_jr_dequeue_burst;
2337 dev->enqueue_burst = caam_jr_enqueue_burst;
2338 dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
2339 RTE_CRYPTODEV_FF_HW_ACCELERATED |
2340 RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
2341 RTE_CRYPTODEV_FF_SECURITY |
2342 RTE_CRYPTODEV_FF_IN_PLACE_SGL |
2343 RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |
2344 RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
2345 RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT |
2346 RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT;
2348 /* For secondary processes, we don't initialise any further as primary
2349 * has already done this work. Only check we don't need a different
2352 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2353 CAAM_JR_WARN("Device already init by primary process");
2357 /*TODO free it during teardown*/
2358 security_instance = rte_malloc("caam_jr",
2359 sizeof(struct rte_security_ctx), 0);
2360 if (security_instance == NULL) {
2361 CAAM_JR_ERR("memory allocation failed\n");
2362 //todo error handling.
2366 security_instance->device = (void *)dev;
2367 security_instance->ops = &caam_jr_security_ops;
2368 security_instance->sess_cnt = 0;
2369 dev->security_ctx = security_instance;
2371 RTE_LOG(INFO, PMD, "%s cryptodev init\n", dev->data->name);
2376 caam_jr_dev_uninit(dev);
2377 rte_cryptodev_pmd_release_device(dev);
2379 free_job_ring(job_ring->uio_fd);
2381 CAAM_JR_ERR("driver %s: cryptodev_caam_jr_create failed",
2387 /** Initialise CAAM JR crypto device */
2389 cryptodev_caam_jr_probe(struct rte_vdev_device *vdev)
2393 struct rte_cryptodev_pmd_init_params init_params = {
2395 sizeof(struct sec_job_ring_t),
2397 RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS
2400 const char *input_args;
2402 name = rte_vdev_device_name(vdev);
2406 input_args = rte_vdev_device_args(vdev);
2407 rte_cryptodev_pmd_parse_input_args(&init_params, input_args);
2412 "of_init failed\n");
2415 /* if sec device version is not configured */
2416 if (!rta_get_sec_era()) {
2417 const struct device_node *caam_node;
2419 for_each_compatible_node(caam_node, NULL, "fsl,sec-v4.0") {
2420 const uint32_t *prop = of_get_property(caam_node,
2425 INTL_SEC_ERA(rte_be_to_cpu_32(*prop)));
2430 #ifdef RTE_LIBRTE_PMD_CAAM_JR_BE
2431 if (rta_get_sec_era() > RTA_SEC_ERA_8) {
2433 "CAAM is compiled in BE mode for device with sec era > 8???\n");
2438 return caam_jr_dev_init(name, vdev, &init_params);
2441 /** Uninitialise CAAM JR crypto device */
2443 cryptodev_caam_jr_remove(struct rte_vdev_device *vdev)
2445 struct rte_cryptodev *cryptodev;
2448 name = rte_vdev_device_name(vdev);
2452 cryptodev = rte_cryptodev_pmd_get_named_dev(name);
2453 if (cryptodev == NULL)
2456 caam_jr_dev_uninit(cryptodev);
2458 return rte_cryptodev_pmd_destroy(cryptodev);
2462 sec_job_rings_init(void)
2466 for (i = 0; i < MAX_SEC_JOB_RINGS; i++)
2467 g_job_rings[i].irq_fd = -1;
2470 static struct rte_vdev_driver cryptodev_caam_jr_drv = {
2471 .probe = cryptodev_caam_jr_probe,
2472 .remove = cryptodev_caam_jr_remove
2475 static struct cryptodev_driver caam_jr_crypto_drv;
2477 RTE_PMD_REGISTER_VDEV(CRYPTODEV_NAME_CAAM_JR_PMD, cryptodev_caam_jr_drv);
2478 RTE_PMD_REGISTER_PARAM_STRING(CRYPTODEV_NAME_CAAM_JR_PMD,
2479 "max_nb_queue_pairs=<int>"
2481 RTE_PMD_REGISTER_CRYPTO_DRIVER(caam_jr_crypto_drv, cryptodev_caam_jr_drv.driver,
2482 cryptodev_driver_id);
2484 RTE_INIT(caam_jr_init)
2486 sec_uio_job_rings_init();
2487 sec_job_rings_init();
2490 RTE_LOG_REGISTER(caam_jr_logtype, pmd.crypto.caam, NOTICE);