1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
13 #include <rte_atomic.h>
14 #include <rte_byteorder.h>
17 #include <rte_spinlock.h>
18 #include <rte_crypto_sym.h>
19 #include <rte_cryptodev.h>
23 #define CCP_SHA3_CTX_SIZE 200
25 * CCP supported AES modes
42 enum ccp_aes_ghash_mode {
43 CCP_AES_MODE_GHASH_AAD = 0,
44 CCP_AES_MODE_GHASH_FINAL
48 * CCP supported AES types
57 /***** 3DES engine *****/
60 * CCP supported DES/3DES modes
63 CCP_DES_MODE_ECB = 0, /* Not supported */
69 * CCP supported DES types
72 CCP_DES_TYPE_128 = 0, /* 112 + 16 parity */
73 CCP_DES_TYPE_192, /* 168 + 24 parity */
77 /***** SHA engine *****/
80 * ccp_sha_type - type of SHA operation
82 * @CCP_SHA_TYPE_1: SHA-1 operation
83 * @CCP_SHA_TYPE_224: SHA-224 operation
84 * @CCP_SHA_TYPE_256: SHA-256 operation
102 * CCP supported cipher algorithms
104 enum ccp_cipher_algo {
105 CCP_CIPHER_ALGO_AES_CBC = 0,
106 CCP_CIPHER_ALGO_AES_ECB,
107 CCP_CIPHER_ALGO_AES_CTR,
108 CCP_CIPHER_ALGO_AES_GCM,
109 CCP_CIPHER_ALGO_3DES_CBC,
113 * CCP cipher operation type
115 enum ccp_cipher_dir {
116 CCP_CIPHER_DIR_DECRYPT = 0,
117 CCP_CIPHER_DIR_ENCRYPT = 1,
121 * CCP supported hash algorithms
124 CCP_AUTH_ALGO_SHA1 = 0,
125 CCP_AUTH_ALGO_SHA1_HMAC,
126 CCP_AUTH_ALGO_SHA224,
127 CCP_AUTH_ALGO_SHA224_HMAC,
128 CCP_AUTH_ALGO_SHA3_224,
129 CCP_AUTH_ALGO_SHA3_224_HMAC,
130 CCP_AUTH_ALGO_SHA256,
131 CCP_AUTH_ALGO_SHA256_HMAC,
132 CCP_AUTH_ALGO_SHA3_256,
133 CCP_AUTH_ALGO_SHA3_256_HMAC,
134 CCP_AUTH_ALGO_SHA384,
135 CCP_AUTH_ALGO_SHA384_HMAC,
136 CCP_AUTH_ALGO_SHA3_384,
137 CCP_AUTH_ALGO_SHA3_384_HMAC,
138 CCP_AUTH_ALGO_SHA512,
139 CCP_AUTH_ALGO_SHA512_HMAC,
140 CCP_AUTH_ALGO_SHA3_512,
141 CCP_AUTH_ALGO_SHA3_512_HMAC,
142 CCP_AUTH_ALGO_AES_CMAC,
143 CCP_AUTH_ALGO_AES_GCM,
144 #ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH
145 CCP_AUTH_ALGO_MD5_HMAC,
150 * CCP hash operation type
153 CCP_AUTH_OP_GENERATE = 0,
154 CCP_AUTH_OP_VERIFY = 1,
157 /* CCP crypto private session structure */
159 enum ccp_cmd_order cmd_id;
160 /**< chain order mode */
165 /**< IV parameters */
167 enum ccp_cipher_algo algo;
168 enum ccp_engine engine;
170 enum ccp_aes_mode aes_mode;
171 enum ccp_des_mode des_mode;
174 enum ccp_aes_type aes_type;
175 enum ccp_des_type des_type;
177 enum ccp_cipher_dir dir;
179 /**< max cipher key size 256 bits */
183 phys_addr_t key_phys;
184 /**AES-ctr nonce(4) iv(8) ctr*/
186 phys_addr_t nonce_phys;
188 /**< Cipher Parameters */
191 enum ccp_hash_algo algo;
192 enum ccp_engine engine;
194 enum ccp_aes_mode aes_mode;
197 enum ccp_sha_type sha_type;
198 enum ccp_aes_type aes_type;
202 /**< max hash key size 144 bytes (struct capabilties) */
204 /**< max be key size of AES is 32*/
206 phys_addr_t key_phys;
207 uint64_t digest_length;
212 /**< Buffer to store Software generated precomute values*/
213 /**< For HMAC H(ipad ^ key) and H(opad ^ key) */
214 /**< For CMAC K1 IV and K2 IV*/
215 uint8_t pre_compute[2 * CCP_SHA3_CTX_SIZE];
216 /**< SHA3 initial ctx all zeros*/
217 uint8_t sha3_ctx[200];
220 /**< Authentication Parameters */
221 enum rte_crypto_aead_algorithm aead_algo;
222 /**< AEAD Algorithm */
225 } __rte_cache_aligned;
227 extern uint8_t ccp_cryptodev_driver_id;
232 * Set and validate CCP crypto session parameters
234 * @param sess ccp private session
235 * @param xform crypto xform for this session
236 * @return 0 on success otherwise -1
238 int ccp_set_session_parameters(struct ccp_session *sess,
239 const struct rte_crypto_sym_xform *xform);
241 #endif /* _CCP_CRYPTO_H_ */