1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
13 #include <rte_atomic.h>
14 #include <rte_byteorder.h>
17 #include <rte_spinlock.h>
18 #include <rte_crypto_sym.h>
19 #include <rte_cryptodev.h>
23 #define AES_BLOCK_SIZE 16
24 #define CMAC_PAD_VALUE 0x80
25 #define CTR_NONCE_SIZE 4
27 #define CCP_SHA3_CTX_SIZE 200
29 /**Macro helpers for CCP command creation*/
30 #define CCP_AES_SIZE(p) ((p)->aes.size)
31 #define CCP_AES_ENCRYPT(p) ((p)->aes.encrypt)
32 #define CCP_AES_MODE(p) ((p)->aes.mode)
33 #define CCP_AES_TYPE(p) ((p)->aes.type)
34 #define CCP_DES_ENCRYPT(p) ((p)->des.encrypt)
35 #define CCP_DES_MODE(p) ((p)->des.mode)
36 #define CCP_DES_TYPE(p) ((p)->des.type)
37 #define CCP_SHA_TYPE(p) ((p)->sha.type)
38 #define CCP_PT_BYTESWAP(p) ((p)->pt.byteswap)
39 #define CCP_PT_BITWISE(p) ((p)->pt.bitwise)
42 #define HMAC_IPAD_VALUE 0x36
43 #define HMAC_OPAD_VALUE 0x5c
45 #ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH
46 #define MD5_DIGEST_SIZE 16
47 #define MD5_BLOCK_SIZE 64
51 #define SHA_COMMON_DIGEST_SIZE 32
52 #define SHA1_DIGEST_SIZE 20
53 #define SHA1_BLOCK_SIZE 64
55 /* SHA LSB intialiazation values */
57 #define SHA1_H0 0x67452301UL
58 #define SHA1_H1 0xefcdab89UL
59 #define SHA1_H2 0x98badcfeUL
60 #define SHA1_H3 0x10325476UL
61 #define SHA1_H4 0xc3d2e1f0UL
64 * CCP supported AES modes
81 enum ccp_aes_ghash_mode {
82 CCP_AES_MODE_GHASH_AAD = 0,
83 CCP_AES_MODE_GHASH_FINAL
87 * CCP supported AES types
96 /***** 3DES engine *****/
99 * CCP supported DES/3DES modes
102 CCP_DES_MODE_ECB = 0, /* Not supported */
108 * CCP supported DES types
111 CCP_DES_TYPE_128 = 0, /* 112 + 16 parity */
112 CCP_DES_TYPE_192, /* 168 + 24 parity */
116 /***** SHA engine *****/
119 * ccp_sha_type - type of SHA operation
121 * @CCP_SHA_TYPE_1: SHA-1 operation
122 * @CCP_SHA_TYPE_224: SHA-224 operation
123 * @CCP_SHA_TYPE_256: SHA-256 operation
141 * CCP supported cipher algorithms
143 enum ccp_cipher_algo {
144 CCP_CIPHER_ALGO_AES_CBC = 0,
145 CCP_CIPHER_ALGO_AES_ECB,
146 CCP_CIPHER_ALGO_AES_CTR,
147 CCP_CIPHER_ALGO_AES_GCM,
148 CCP_CIPHER_ALGO_3DES_CBC,
152 * CCP cipher operation type
154 enum ccp_cipher_dir {
155 CCP_CIPHER_DIR_DECRYPT = 0,
156 CCP_CIPHER_DIR_ENCRYPT = 1,
160 * CCP supported hash algorithms
163 CCP_AUTH_ALGO_SHA1 = 0,
164 CCP_AUTH_ALGO_SHA1_HMAC,
165 CCP_AUTH_ALGO_SHA224,
166 CCP_AUTH_ALGO_SHA224_HMAC,
167 CCP_AUTH_ALGO_SHA3_224,
168 CCP_AUTH_ALGO_SHA3_224_HMAC,
169 CCP_AUTH_ALGO_SHA256,
170 CCP_AUTH_ALGO_SHA256_HMAC,
171 CCP_AUTH_ALGO_SHA3_256,
172 CCP_AUTH_ALGO_SHA3_256_HMAC,
173 CCP_AUTH_ALGO_SHA384,
174 CCP_AUTH_ALGO_SHA384_HMAC,
175 CCP_AUTH_ALGO_SHA3_384,
176 CCP_AUTH_ALGO_SHA3_384_HMAC,
177 CCP_AUTH_ALGO_SHA512,
178 CCP_AUTH_ALGO_SHA512_HMAC,
179 CCP_AUTH_ALGO_SHA3_512,
180 CCP_AUTH_ALGO_SHA3_512_HMAC,
181 CCP_AUTH_ALGO_AES_CMAC,
182 CCP_AUTH_ALGO_AES_GCM,
183 #ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH
184 CCP_AUTH_ALGO_MD5_HMAC,
189 * CCP hash operation type
192 CCP_AUTH_OP_GENERATE = 0,
193 CCP_AUTH_OP_VERIFY = 1,
196 /* CCP crypto private session structure */
198 enum ccp_cmd_order cmd_id;
199 /**< chain order mode */
204 /**< IV parameters */
206 enum ccp_cipher_algo algo;
207 enum ccp_engine engine;
209 enum ccp_aes_mode aes_mode;
210 enum ccp_des_mode des_mode;
213 enum ccp_aes_type aes_type;
214 enum ccp_des_type des_type;
216 enum ccp_cipher_dir dir;
218 /**< max cipher key size 256 bits */
222 phys_addr_t key_phys;
223 /**AES-ctr nonce(4) iv(8) ctr*/
225 phys_addr_t nonce_phys;
227 /**< Cipher Parameters */
230 enum ccp_hash_algo algo;
231 enum ccp_engine engine;
233 enum ccp_aes_mode aes_mode;
236 enum ccp_sha_type sha_type;
237 enum ccp_aes_type aes_type;
241 /**< max hash key size 144 bytes (struct capabilties) */
243 /**< max be key size of AES is 32*/
245 phys_addr_t key_phys;
246 uint64_t digest_length;
251 /**< Buffer to store Software generated precomute values*/
252 /**< For HMAC H(ipad ^ key) and H(opad ^ key) */
253 /**< For CMAC K1 IV and K2 IV*/
254 uint8_t pre_compute[2 * CCP_SHA3_CTX_SIZE];
255 /**< SHA3 initial ctx all zeros*/
256 uint8_t sha3_ctx[200];
259 /**< Authentication Parameters */
260 enum rte_crypto_aead_algorithm aead_algo;
261 /**< AEAD Algorithm */
264 } __rte_cache_aligned;
266 extern uint8_t ccp_cryptodev_driver_id;
271 * Set and validate CCP crypto session parameters
273 * @param sess ccp private session
274 * @param xform crypto xform for this session
275 * @return 0 on success otherwise -1
277 int ccp_set_session_parameters(struct ccp_session *sess,
278 const struct rte_crypto_sym_xform *xform);
281 * Find count of slots
283 * @param session CCP private session
284 * @return count of free slots available
286 int ccp_compute_slot_count(struct ccp_session *session);
289 * process crypto ops to be enqueued
291 * @param qp CCP crypto queue-pair
292 * @param op crypto ops table
293 * @param cmd_q CCP cmd queue
294 * @param nb_ops No. of ops to be submitted
295 * @return 0 on success otherwise -1
297 int process_ops_to_enqueue(const struct ccp_qp *qp,
298 struct rte_crypto_op **op,
299 struct ccp_queue *cmd_q,
304 * process crypto ops to be dequeued
306 * @param qp CCP crypto queue-pair
307 * @param op crypto ops table
308 * @param nb_ops requested no. of ops
309 * @return 0 on success otherwise -1
311 int process_ops_to_dequeue(struct ccp_qp *qp,
312 struct rte_crypto_op **op,
315 #endif /* _CCP_CRYPTO_H_ */