1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
10 #include <sys/queue.h>
11 #include <sys/types.h>
15 #include <rte_hexdump.h>
16 #include <rte_memzone.h>
17 #include <rte_malloc.h>
18 #include <rte_memory.h>
19 #include <rte_spinlock.h>
20 #include <rte_string_fns.h>
24 #include "ccp_pmd_private.h"
27 struct ccp_list ccp_list = TAILQ_HEAD_INITIALIZER(ccp_list);
28 static int ccp_dev_id;
31 ccp_dev_start(struct rte_cryptodev *dev)
33 struct ccp_private *priv = dev->data->dev_private;
35 priv->last_dev = TAILQ_FIRST(&ccp_list);
40 ccp_allot_queue(struct rte_cryptodev *cdev, int slot_req)
43 struct ccp_device *dev;
44 struct ccp_private *priv = cdev->data->dev_private;
46 dev = TAILQ_NEXT(priv->last_dev, next);
47 if (unlikely(dev == NULL))
48 dev = TAILQ_FIRST(&ccp_list);
50 if (dev->qidx >= dev->cmd_q_count)
52 ret = rte_atomic64_read(&dev->cmd_q[dev->qidx].free_slots);
54 return &dev->cmd_q[dev->qidx];
55 for (i = 0; i < dev->cmd_q_count; i++) {
57 if (dev->qidx >= dev->cmd_q_count)
59 ret = rte_atomic64_read(&dev->cmd_q[dev->qidx].free_slots);
61 return &dev->cmd_q[dev->qidx];
67 ccp_read_hwrng(uint32_t *value)
69 struct ccp_device *dev;
71 TAILQ_FOREACH(dev, &ccp_list, next) {
72 void *vaddr = (void *)(dev->pci.mem_resource[2].addr);
74 while (dev->hwrng_retries++ < CCP_MAX_TRNG_RETRIES) {
75 *value = CCP_READ_REG(vaddr, TRNG_OUT_REG);
77 dev->hwrng_retries = 0;
81 dev->hwrng_retries = 0;
86 static const struct rte_memzone *
87 ccp_queue_dma_zone_reserve(const char *queue_name,
91 const struct rte_memzone *mz;
93 mz = rte_memzone_lookup(queue_name);
95 if (((size_t)queue_size <= mz->len) &&
96 ((socket_id == SOCKET_ID_ANY) ||
97 (socket_id == mz->socket_id))) {
98 CCP_LOG_INFO("re-use memzone already "
99 "allocated for %s", queue_name);
102 CCP_LOG_ERR("Incompatible memzone already "
103 "allocated %s, size %u, socket %d. "
104 "Requested size %u, socket %u",
105 queue_name, (uint32_t)mz->len,
106 mz->socket_id, queue_size, socket_id);
110 CCP_LOG_INFO("Allocate memzone for %s, size %u on socket %u",
111 queue_name, queue_size, socket_id);
113 return rte_memzone_reserve_aligned(queue_name, queue_size,
114 socket_id, RTE_MEMZONE_IOVA_CONTIG, queue_size);
117 /* bitmap support apis */
119 ccp_set_bit(unsigned long *bitmap, int n)
121 __sync_fetch_and_or(&bitmap[WORD_OFFSET(n)], (1UL << BIT_OFFSET(n)));
125 ccp_clear_bit(unsigned long *bitmap, int n)
127 __sync_fetch_and_and(&bitmap[WORD_OFFSET(n)], ~(1UL << BIT_OFFSET(n)));
130 static inline uint32_t
131 ccp_get_bit(unsigned long *bitmap, int n)
133 return ((bitmap[WORD_OFFSET(n)] & (1 << BIT_OFFSET(n))) != 0);
137 static inline uint32_t
138 ccp_ffz(unsigned long word)
140 unsigned long first_zero;
142 first_zero = __builtin_ffsl(~word);
143 return first_zero ? (first_zero - 1) :
147 static inline uint32_t
148 ccp_find_first_zero_bit(unsigned long *addr, uint32_t limit)
153 nwords = (limit - 1) / BITS_PER_WORD + 1;
154 for (i = 0; i < nwords; i++) {
156 return i * BITS_PER_WORD;
157 if (addr[i] < ~(0UL))
160 return (i == nwords) ? limit : i * BITS_PER_WORD + ccp_ffz(addr[i]);
164 ccp_bitmap_set(unsigned long *map, unsigned int start, int len)
166 unsigned long *p = map + WORD_OFFSET(start);
167 const unsigned int size = start + len;
168 int bits_to_set = BITS_PER_WORD - (start % BITS_PER_WORD);
169 unsigned long mask_to_set = CCP_BITMAP_FIRST_WORD_MASK(start);
171 while (len - bits_to_set >= 0) {
174 bits_to_set = BITS_PER_WORD;
179 mask_to_set &= CCP_BITMAP_LAST_WORD_MASK(size);
185 ccp_bitmap_clear(unsigned long *map, unsigned int start, int len)
187 unsigned long *p = map + WORD_OFFSET(start);
188 const unsigned int size = start + len;
189 int bits_to_clear = BITS_PER_WORD - (start % BITS_PER_WORD);
190 unsigned long mask_to_clear = CCP_BITMAP_FIRST_WORD_MASK(start);
192 while (len - bits_to_clear >= 0) {
193 *p &= ~mask_to_clear;
194 len -= bits_to_clear;
195 bits_to_clear = BITS_PER_WORD;
196 mask_to_clear = ~0UL;
200 mask_to_clear &= CCP_BITMAP_LAST_WORD_MASK(size);
201 *p &= ~mask_to_clear;
207 _ccp_find_next_bit(const unsigned long *addr,
210 unsigned long invert)
214 if (!nbits || start >= nbits)
217 tmp = addr[start / BITS_PER_WORD] ^ invert;
219 /* Handle 1st word. */
220 tmp &= CCP_BITMAP_FIRST_WORD_MASK(start);
221 start = ccp_round_down(start, BITS_PER_WORD);
224 start += BITS_PER_WORD;
228 tmp = addr[start / BITS_PER_WORD] ^ invert;
231 return RTE_MIN(start + (ffs(tmp) - 1), nbits);
235 ccp_find_next_bit(const unsigned long *addr,
237 unsigned long offset)
239 return _ccp_find_next_bit(addr, size, offset, 0UL);
243 ccp_find_next_zero_bit(const unsigned long *addr,
245 unsigned long offset)
247 return _ccp_find_next_bit(addr, size, offset, ~0UL);
251 * bitmap_find_next_zero_area - find a contiguous aligned zero area
252 * @map: The address to base the search on
253 * @size: The bitmap size in bits
254 * @start: The bitnumber to start searching at
255 * @nr: The number of zeroed bits we're looking for
258 ccp_bitmap_find_next_zero_area(unsigned long *map,
263 unsigned long index, end, i;
266 index = ccp_find_next_zero_bit(map, size, start);
271 i = ccp_find_next_bit(map, end, index);
280 ccp_lsb_alloc(struct ccp_queue *cmd_q, unsigned int count)
282 struct ccp_device *ccp;
285 /* First look at the map for the queue */
286 if (cmd_q->lsb >= 0) {
287 start = (uint32_t)ccp_bitmap_find_next_zero_area(cmd_q->lsbmap,
290 if (start < LSB_SIZE) {
291 ccp_bitmap_set(cmd_q->lsbmap, start, count);
292 return start + cmd_q->lsb * LSB_SIZE;
296 /* try to get an entry from the shared blocks */
299 rte_spinlock_lock(&ccp->lsb_lock);
301 start = (uint32_t)ccp_bitmap_find_next_zero_area(ccp->lsbmap,
302 MAX_LSB_CNT * LSB_SIZE,
304 if (start <= MAX_LSB_CNT * LSB_SIZE) {
305 ccp_bitmap_set(ccp->lsbmap, start, count);
306 rte_spinlock_unlock(&ccp->lsb_lock);
307 return start * LSB_ITEM_SIZE;
309 CCP_LOG_ERR("NO LSBs available");
311 rte_spinlock_unlock(&ccp->lsb_lock);
316 static void __rte_unused
317 ccp_lsb_free(struct ccp_queue *cmd_q,
321 int lsbno = start / LSB_SIZE;
326 if (cmd_q->lsb == lsbno) {
327 /* An entry from the private LSB */
328 ccp_bitmap_clear(cmd_q->lsbmap, start % LSB_SIZE, count);
330 /* From the shared LSBs */
331 struct ccp_device *ccp = cmd_q->dev;
333 rte_spinlock_lock(&ccp->lsb_lock);
334 ccp_bitmap_clear(ccp->lsbmap, start, count);
335 rte_spinlock_unlock(&ccp->lsb_lock);
340 ccp_find_lsb_regions(struct ccp_queue *cmd_q, uint64_t status)
342 int q_mask = 1 << cmd_q->id;
346 /* Build a bit mask to know which LSBs
347 * this queue has access to.
348 * Don't bother with segment 0
353 status >>= LSB_REGION_WIDTH;
354 for (j = 1; j < MAX_LSB_CNT; j++) {
356 ccp_set_bit(&cmd_q->lsbmask, j);
358 status >>= LSB_REGION_WIDTH;
361 for (j = 0; j < MAX_LSB_CNT; j++)
362 if (ccp_get_bit(&cmd_q->lsbmask, j))
365 printf("Queue %d can access %d LSB regions of mask %lu\n",
366 (int)cmd_q->id, weight, cmd_q->lsbmask);
368 return weight ? 0 : -EINVAL;
372 ccp_find_and_assign_lsb_to_q(struct ccp_device *ccp,
373 int lsb_cnt, int n_lsbs,
374 unsigned long *lsb_pub)
376 unsigned long qlsb = 0;
382 * If the count of potential LSBs available to a queue matches the
383 * ordinal given to us in lsb_cnt:
384 * Copy the mask of possible LSBs for this queue into "qlsb";
385 * For each bit in qlsb, see if the corresponding bit in the
386 * aggregation mask is set; if so, we have a match.
387 * If we have a match, clear the bit in the aggregation to
388 * mark it as no longer available.
389 * If there is no match, clear the bit in qlsb and keep looking.
391 for (i = 0; i < ccp->cmd_q_count; i++) {
392 struct ccp_queue *cmd_q = &ccp->cmd_q[i];
395 for (j = 0; j < MAX_LSB_CNT; j++)
396 if (ccp_get_bit(&cmd_q->lsbmask, j))
399 if (qlsb_wgt == lsb_cnt) {
400 qlsb = cmd_q->lsbmask;
402 bitno = ffs(qlsb) - 1;
403 while (bitno < MAX_LSB_CNT) {
404 if (ccp_get_bit(lsb_pub, bitno)) {
405 /* We found an available LSB
406 * that this queue can access
409 ccp_clear_bit(lsb_pub, bitno);
412 ccp_clear_bit(&qlsb, bitno);
413 bitno = ffs(qlsb) - 1;
415 if (bitno >= MAX_LSB_CNT)
423 /* For each queue, from the most- to least-constrained:
424 * find an LSB that can be assigned to the queue. If there are N queues that
425 * can only use M LSBs, where N > M, fail; otherwise, every queue will get a
426 * dedicated LSB. Remaining LSB regions become a shared resource.
427 * If we have fewer LSBs than queues, all LSB regions become shared
431 ccp_assign_lsbs(struct ccp_device *ccp)
433 unsigned long lsb_pub = 0, qlsb = 0;
439 rte_spinlock_init(&ccp->lsb_lock);
441 /* Create an aggregate bitmap to get a total count of available LSBs */
442 for (i = 0; i < ccp->cmd_q_count; i++)
443 lsb_pub |= ccp->cmd_q[i].lsbmask;
445 for (i = 0; i < MAX_LSB_CNT; i++)
446 if (ccp_get_bit(&lsb_pub, i))
449 if (n_lsbs >= ccp->cmd_q_count) {
450 /* We have enough LSBS to give every queue a private LSB.
451 * Brute force search to start with the queues that are more
452 * constrained in LSB choice. When an LSB is privately
453 * assigned, it is removed from the public mask.
454 * This is an ugly N squared algorithm with some optimization.
456 for (lsb_cnt = 1; n_lsbs && (lsb_cnt <= MAX_LSB_CNT);
458 rc = ccp_find_and_assign_lsb_to_q(ccp, lsb_cnt, n_lsbs,
467 /* What's left of the LSBs, according to the public mask, now become
468 * shared. Any zero bits in the lsb_pub mask represent an LSB region
469 * that can't be used as a shared resource, so mark the LSB slots for
473 bitno = ccp_find_first_zero_bit(&qlsb, MAX_LSB_CNT);
474 while (bitno < MAX_LSB_CNT) {
475 ccp_bitmap_set(ccp->lsbmap, bitno * LSB_SIZE, LSB_SIZE);
476 ccp_set_bit(&qlsb, bitno);
477 bitno = ccp_find_first_zero_bit(&qlsb, MAX_LSB_CNT);
484 ccp_add_device(struct ccp_device *dev, int type)
487 uint32_t qmr, status_lo, status_hi, dma_addr_lo, dma_addr_hi;
489 struct ccp_queue *cmd_q;
490 const struct rte_memzone *q_mz;
496 dev->id = ccp_dev_id++;
498 vaddr = (void *)(dev->pci.mem_resource[2].addr);
500 if (type == CCP_VERSION_5B) {
501 CCP_WRITE_REG(vaddr, CMD_TRNG_CTL_OFFSET, 0x00012D57);
502 CCP_WRITE_REG(vaddr, CMD_CONFIG_0_OFFSET, 0x00000003);
503 for (i = 0; i < 12; i++) {
504 CCP_WRITE_REG(vaddr, CMD_AES_MASK_OFFSET,
505 CCP_READ_REG(vaddr, TRNG_OUT_REG));
507 CCP_WRITE_REG(vaddr, CMD_QUEUE_MASK_OFFSET, 0x0000001F);
508 CCP_WRITE_REG(vaddr, CMD_QUEUE_PRIO_OFFSET, 0x00005B6D);
509 CCP_WRITE_REG(vaddr, CMD_CMD_TIMEOUT_OFFSET, 0x00000000);
511 CCP_WRITE_REG(vaddr, LSB_PRIVATE_MASK_LO_OFFSET, 0x3FFFFFFF);
512 CCP_WRITE_REG(vaddr, LSB_PRIVATE_MASK_HI_OFFSET, 0x000003FF);
514 CCP_WRITE_REG(vaddr, CMD_CLK_GATE_CTL_OFFSET, 0x00108823);
516 CCP_WRITE_REG(vaddr, CMD_REQID_CONFIG_OFFSET, 0x0);
518 /* Copy the private LSB mask to the public registers */
519 status_lo = CCP_READ_REG(vaddr, LSB_PRIVATE_MASK_LO_OFFSET);
520 status_hi = CCP_READ_REG(vaddr, LSB_PRIVATE_MASK_HI_OFFSET);
521 CCP_WRITE_REG(vaddr, LSB_PUBLIC_MASK_LO_OFFSET, status_lo);
522 CCP_WRITE_REG(vaddr, LSB_PUBLIC_MASK_HI_OFFSET, status_hi);
523 status = ((uint64_t)status_hi<<30) | ((uint64_t)status_lo);
525 dev->cmd_q_count = 0;
526 /* Find available queues */
527 qmr = CCP_READ_REG(vaddr, Q_MASK_REG);
528 for (i = 0; i < MAX_HW_QUEUES; i++) {
529 if (!(qmr & (1 << i)))
531 cmd_q = &dev->cmd_q[dev->cmd_q_count++];
535 cmd_q->qsize = Q_SIZE(Q_DESC_SIZE);
537 cmd_q->reg_base = (uint8_t *)vaddr +
538 CMD_Q_STATUS_INCR * (i + 1);
540 /* CCP queue memory */
541 snprintf(cmd_q->memz_name, sizeof(cmd_q->memz_name),
544 (int)dev->id, "queue",
545 (int)cmd_q->id, "mem");
546 q_mz = ccp_queue_dma_zone_reserve(cmd_q->memz_name,
547 cmd_q->qsize, SOCKET_ID_ANY);
548 cmd_q->qbase_addr = (void *)q_mz->addr;
549 cmd_q->qbase_desc = (void *)q_mz->addr;
550 cmd_q->qbase_phys_addr = q_mz->iova;
553 /* init control reg to zero */
554 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,
557 /* Disable the interrupts */
558 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_INT_ENABLE_BASE, 0x00);
559 CCP_READ_REG(cmd_q->reg_base, CMD_Q_INT_STATUS_BASE);
560 CCP_READ_REG(cmd_q->reg_base, CMD_Q_STATUS_BASE);
562 /* Clear the interrupts */
563 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_INTERRUPT_STATUS_BASE,
566 /* Configure size of each virtual queue accessible to host */
567 cmd_q->qcontrol &= ~(CMD_Q_SIZE << CMD_Q_SHIFT);
568 cmd_q->qcontrol |= QUEUE_SIZE_VAL << CMD_Q_SHIFT;
570 dma_addr_lo = low32_value(cmd_q->qbase_phys_addr);
571 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_TAIL_LO_BASE,
572 (uint32_t)dma_addr_lo);
573 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_HEAD_LO_BASE,
574 (uint32_t)dma_addr_lo);
576 dma_addr_hi = high32_value(cmd_q->qbase_phys_addr);
577 cmd_q->qcontrol |= (dma_addr_hi << 16);
578 CCP_WRITE_REG(cmd_q->reg_base, CMD_Q_CONTROL_BASE,
581 /* create LSB Mask map */
582 if (ccp_find_lsb_regions(cmd_q, status))
583 CCP_LOG_ERR("queue doesn't have lsb regions");
586 rte_atomic64_init(&cmd_q->free_slots);
587 rte_atomic64_set(&cmd_q->free_slots, (COMMANDS_PER_QUEUE - 1));
588 /* unused slot barrier b/w H&T */
591 if (ccp_assign_lsbs(dev))
592 CCP_LOG_ERR("Unable to assign lsb region");
594 /* pre-allocate LSB slots */
595 for (i = 0; i < dev->cmd_q_count; i++) {
596 dev->cmd_q[i].sb_key =
597 ccp_lsb_alloc(&dev->cmd_q[i], 1);
598 dev->cmd_q[i].sb_iv =
599 ccp_lsb_alloc(&dev->cmd_q[i], 1);
600 dev->cmd_q[i].sb_sha =
601 ccp_lsb_alloc(&dev->cmd_q[i], 2);
602 dev->cmd_q[i].sb_hmac =
603 ccp_lsb_alloc(&dev->cmd_q[i], 2);
606 TAILQ_INSERT_TAIL(&ccp_list, dev, next);
611 ccp_remove_device(struct ccp_device *dev)
616 TAILQ_REMOVE(&ccp_list, dev, next);
620 is_ccp_device(const char *dirname,
621 const struct rte_pci_id *ccp_id,
624 char filename[PATH_MAX];
625 const struct rte_pci_id *id;
626 uint16_t vendor, device_id;
631 snprintf(filename, sizeof(filename), "%s/vendor", dirname);
632 if (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)
634 vendor = (uint16_t)tmp;
637 snprintf(filename, sizeof(filename), "%s/device", dirname);
638 if (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)
640 device_id = (uint16_t)tmp;
642 for (id = ccp_id, i = 0; id->vendor_id != 0; id++, i++) {
643 if (vendor == id->vendor_id &&
644 device_id == id->device_id) {
646 return 1; /* Matched device */
653 ccp_probe_device(const char *dirname, uint16_t domain,
654 uint8_t bus, uint8_t devid,
655 uint8_t function, int ccp_type)
657 struct ccp_device *ccp_dev = NULL;
658 struct rte_pci_device *pci;
659 char filename[PATH_MAX];
663 ccp_dev = rte_zmalloc("ccp_device", sizeof(*ccp_dev),
664 RTE_CACHE_LINE_SIZE);
667 pci = &(ccp_dev->pci);
669 pci->addr.domain = domain;
671 pci->addr.devid = devid;
672 pci->addr.function = function;
675 snprintf(filename, sizeof(filename), "%s/vendor", dirname);
676 if (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)
678 pci->id.vendor_id = (uint16_t)tmp;
681 snprintf(filename, sizeof(filename), "%s/device", dirname);
682 if (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)
684 pci->id.device_id = (uint16_t)tmp;
686 /* get subsystem_vendor id */
687 snprintf(filename, sizeof(filename), "%s/subsystem_vendor",
689 if (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)
691 pci->id.subsystem_vendor_id = (uint16_t)tmp;
693 /* get subsystem_device id */
694 snprintf(filename, sizeof(filename), "%s/subsystem_device",
696 if (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)
698 pci->id.subsystem_device_id = (uint16_t)tmp;
701 snprintf(filename, sizeof(filename), "%s/class",
703 if (ccp_pci_parse_sysfs_value(filename, &tmp) < 0)
705 /* the least 24 bits are valid: class, subclass, program interface */
706 pci->id.class_id = (uint32_t)tmp & RTE_CLASS_ANY_ID;
708 /* parse resources */
709 snprintf(filename, sizeof(filename), "%s/resource", dirname);
710 if (ccp_pci_parse_sysfs_resource(filename, pci) < 0)
713 pci->kdrv = RTE_PCI_KDRV_VFIO;
714 else if (iommu_mode == 0)
715 pci->kdrv = RTE_PCI_KDRV_IGB_UIO;
716 else if (iommu_mode == 1)
717 pci->kdrv = RTE_PCI_KDRV_UIO_GENERIC;
719 rte_pci_map_device(pci);
721 /* device is valid, add in list */
722 if (ccp_add_device(ccp_dev, ccp_type)) {
723 ccp_remove_device(ccp_dev);
729 CCP_LOG_ERR("CCP Device probe failed");
738 ccp_probe_devices(const struct rte_pci_id *ccp_id)
747 uint8_t bus, devid, function;
748 char dirname[PATH_MAX];
750 module_idx = ccp_check_pci_uio_module();
754 iommu_mode = module_idx;
755 TAILQ_INIT(&ccp_list);
756 dir = opendir(SYSFS_PCI_DEVICES);
759 while ((d = readdir(dir)) != NULL) {
760 if (d->d_name[0] == '.')
762 if (ccp_parse_pci_addr_format(d->d_name, sizeof(d->d_name),
763 &domain, &bus, &devid, &function) != 0)
765 snprintf(dirname, sizeof(dirname), "%s/%s",
766 SYSFS_PCI_DEVICES, d->d_name);
767 if (is_ccp_device(dirname, ccp_id, &ccp_type)) {
768 printf("CCP : Detected CCP device with ID = 0x%x\n",
769 ccp_id[ccp_type].device_id);
770 ret = ccp_probe_device(dirname, domain, bus, devid,