1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include <rte_cryptodev.h>
6 #include <cryptodev_pmd.h>
7 #include <rte_event_crypto_adapter.h>
10 #include "cn10k_cryptodev.h"
11 #include "cn10k_cryptodev_ops.h"
12 #include "cn10k_ipsec_la_ops.h"
13 #include "cn10k_ipsec.h"
15 #include "cnxk_cryptodev.h"
16 #include "cnxk_cryptodev_ops.h"
21 static inline struct cnxk_se_sess *
22 cn10k_cpt_sym_temp_sess_create(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op)
24 const int driver_id = cn10k_cryptodev_driver_id;
25 struct rte_crypto_sym_op *sym_op = op->sym;
26 struct rte_cryptodev_sym_session *sess;
27 struct cnxk_se_sess *priv;
30 /* Create temporary session */
31 sess = rte_cryptodev_sym_session_create(qp->sess_mp);
35 ret = sym_session_configure(qp->lf.roc_cpt, driver_id, sym_op->xform,
36 sess, qp->sess_mp_priv);
40 priv = get_sym_session_private_data(sess, driver_id);
42 sym_op->session = sess;
47 rte_mempool_put(qp->sess_mp, sess);
51 static __rte_always_inline int __rte_hot
52 cpt_sec_inst_fill(struct rte_crypto_op *op, struct cn10k_sec_session *sess,
53 struct cpt_inst_s *inst)
55 struct rte_crypto_sym_op *sym_op = op->sym;
56 union roc_ot_ipsec_sa_word2 *w2;
57 struct cn10k_ipsec_sa *sa;
60 if (unlikely(sym_op->m_dst && sym_op->m_dst != sym_op->m_src)) {
61 plt_dp_err("Out of place is not supported");
65 if (unlikely(!rte_pktmbuf_is_contiguous(sym_op->m_src))) {
66 plt_dp_err("Scatter Gather mode is not supported");
71 w2 = (union roc_ot_ipsec_sa_word2 *)&sa->in_sa.w2;
73 if (w2->s.dir == ROC_IE_SA_DIR_OUTBOUND)
74 ret = process_outb_sa(op, sa, inst);
76 ret = process_inb_sa(op, sa, inst);
81 static __rte_always_inline int __rte_hot
82 cpt_sym_inst_fill(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,
83 struct cnxk_se_sess *sess, struct cpt_inflight_req *infl_req,
84 struct cpt_inst_s *inst)
89 cpt_op = sess->cpt_op;
91 if (cpt_op & ROC_SE_OP_CIPHER_MASK)
92 ret = fill_fc_params(op, sess, &qp->meta_info, infl_req, inst);
94 ret = fill_digest_params(op, sess, &qp->meta_info, infl_req,
101 cn10k_cpt_fill_inst(struct cnxk_cpt_qp *qp, struct rte_crypto_op *ops[],
102 struct cpt_inst_s inst[], struct cpt_inflight_req *infl_req)
104 struct cn10k_sec_session *sec_sess;
105 struct rte_crypto_asym_op *asym_op;
106 struct rte_crypto_sym_op *sym_op;
107 struct cnxk_ae_sess *ae_sess;
108 struct cnxk_se_sess *sess;
109 struct rte_crypto_op *op;
121 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
122 if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
123 sec_sess = get_sec_session_private_data(
124 sym_op->sec_session);
125 ret = cpt_sec_inst_fill(op, sec_sess, &inst[0]);
128 w7 = sec_sess->sa.inst.w7;
129 } else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
130 sess = get_sym_session_private_data(
131 sym_op->session, cn10k_cryptodev_driver_id);
132 ret = cpt_sym_inst_fill(qp, op, sess, infl_req,
136 w7 = sess->cpt_inst_w7;
138 sess = cn10k_cpt_sym_temp_sess_create(qp, op);
139 if (unlikely(sess == NULL)) {
140 plt_dp_err("Could not create temp session");
144 ret = cpt_sym_inst_fill(qp, op, sess, infl_req,
147 sym_session_clear(cn10k_cryptodev_driver_id,
149 rte_mempool_put(qp->sess_mp, op->sym->session);
152 w7 = sess->cpt_inst_w7;
154 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
156 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
158 ae_sess = get_asym_session_private_data(
159 asym_op->session, cn10k_cryptodev_driver_id);
160 ret = cnxk_ae_enqueue(qp, op, infl_req, &inst[0],
164 w7 = ae_sess->cpt_inst_w7;
166 plt_dp_err("Not supported Asym op without session");
170 plt_dp_err("Unsupported op type");
174 inst[0].res_addr = (uint64_t)&infl_req->res;
175 infl_req->res.cn10k.compcode = CPT_COMP_NOT_DONE;
183 #define PKTS_PER_LOOP 32
184 #define PKTS_PER_STEORL 16
187 cn10k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
189 uint64_t lmt_base, lmt_arg, io_addr;
190 struct cpt_inflight_req *infl_req;
191 uint16_t nb_allowed, count = 0;
192 struct cnxk_cpt_qp *qp = qptr;
193 struct pending_queue *pend_q;
194 struct cpt_inst_s *inst;
198 pend_q = &qp->pend_q;
200 nb_allowed = qp->lf.nb_desc - pend_q->pending_count;
201 nb_ops = RTE_MIN(nb_ops, nb_allowed);
203 if (unlikely(nb_ops == 0))
206 lmt_base = qp->lmtline.lmt_base;
207 io_addr = qp->lmtline.io_addr;
209 ROC_LMT_BASE_ID_GET(lmt_base, lmt_id);
210 inst = (struct cpt_inst_s *)lmt_base;
213 for (i = 0; i < RTE_MIN(PKTS_PER_LOOP, nb_ops); i++) {
214 infl_req = &pend_q->req_queue[pend_q->enq_tail];
215 infl_req->op_flags = 0;
217 ret = cn10k_cpt_fill_inst(qp, ops + i, &inst[2 * i], infl_req);
218 if (unlikely(ret != 1)) {
219 plt_dp_err("Could not process op: %p", ops + i);
225 MOD_INC(pend_q->enq_tail, qp->lf.nb_desc);
228 if (i > PKTS_PER_STEORL) {
229 lmt_arg = ROC_CN10K_CPT_LMT_ARG | (PKTS_PER_STEORL - 1) << 12 |
231 roc_lmt_submit_steorl(lmt_arg, io_addr);
232 lmt_arg = ROC_CN10K_CPT_LMT_ARG |
233 (i - PKTS_PER_STEORL - 1) << 12 |
234 (uint64_t)(lmt_id + PKTS_PER_STEORL);
235 roc_lmt_submit_steorl(lmt_arg, io_addr);
237 lmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - 1) << 12 |
239 roc_lmt_submit_steorl(lmt_arg, io_addr);
244 if (nb_ops - i > 0 && i == PKTS_PER_LOOP) {
252 pend_q->pending_count += count + i;
254 pend_q->time_out = rte_get_timer_cycles() +
255 DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
261 cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)
263 union rte_event_crypto_metadata *ec_mdata;
264 struct cpt_inflight_req *infl_req;
265 struct rte_event *rsp_info;
266 uint64_t lmt_base, lmt_arg;
267 struct cpt_inst_s *inst;
268 struct cnxk_cpt_qp *qp;
274 ec_mdata = cnxk_event_crypto_mdata_get(op);
280 cdev_id = ec_mdata->request_info.cdev_id;
281 qp_id = ec_mdata->request_info.queue_pair_id;
282 qp = rte_cryptodevs[cdev_id].data->queue_pairs[qp_id];
283 rsp_info = &ec_mdata->response_info;
285 if (unlikely(!qp->ca.enabled)) {
290 if (unlikely(rte_mempool_get(qp->ca.req_mp, (void **)&infl_req))) {
294 infl_req->op_flags = 0;
296 lmt_base = qp->lmtline.lmt_base;
297 ROC_LMT_BASE_ID_GET(lmt_base, lmt_id);
298 inst = (struct cpt_inst_s *)lmt_base;
300 ret = cn10k_cpt_fill_inst(qp, &op, inst, infl_req);
301 if (unlikely(ret != 1)) {
302 plt_dp_err("Could not process op: %p", op);
303 rte_mempool_put(qp->ca.req_mp, infl_req);
308 infl_req->res.cn10k.compcode = CPT_COMP_NOT_DONE;
311 inst->res_addr = (uint64_t)&infl_req->res;
312 inst->w2.u64 = CNXK_CPT_INST_W2(
313 (RTE_EVENT_TYPE_CRYPTODEV << 28) | rsp_info->flow_id,
314 rsp_info->sched_type, rsp_info->queue_id, 0);
315 inst->w3.u64 = CNXK_CPT_INST_W3(1, infl_req);
317 if (roc_cpt_is_iq_full(&qp->lf)) {
318 rte_mempool_put(qp->ca.req_mp, infl_req);
323 if (!rsp_info->sched_type)
324 roc_sso_hws_head_wait(tag_op);
326 lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id;
327 roc_lmt_submit_steorl(lmt_arg, qp->lmtline.io_addr);
335 cn10k_cpt_sec_post_process(struct rte_crypto_op *cop,
336 struct cpt_cn10k_res_s *res)
338 struct rte_mbuf *m = cop->sym->m_src;
339 const uint16_t m_len = res->rlen;
346 cn10k_cpt_dequeue_post_process(struct cnxk_cpt_qp *qp,
347 struct rte_crypto_op *cop,
348 struct cpt_inflight_req *infl_req)
350 struct cpt_cn10k_res_s *res = (struct cpt_cn10k_res_s *)&infl_req->res;
353 if (likely(res->compcode == CPT_COMP_GOOD ||
354 res->compcode == CPT_COMP_WARN)) {
355 if (unlikely(res->uc_compcode)) {
356 if (res->uc_compcode == ROC_SE_ERR_GC_ICV_MISCOMPARE)
357 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
359 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
361 plt_dp_info("Request failed with microcode error");
362 plt_dp_info("MC completion code 0x%x",
367 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
368 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
369 if (cop->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
370 cn10k_cpt_sec_post_process(cop, res);
374 /* Verify authentication data if required */
375 if (unlikely(infl_req->op_flags &
376 CPT_OP_FLAGS_AUTH_VERIFY)) {
377 uintptr_t *rsp = infl_req->mdata;
378 compl_auth_verify(cop, (uint8_t *)rsp[0],
381 } else if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
382 struct rte_crypto_asym_op *op = cop->asym;
383 uintptr_t *mdata = infl_req->mdata;
384 struct cnxk_ae_sess *sess;
386 sess = get_asym_session_private_data(
387 op->session, cn10k_cryptodev_driver_id);
389 cnxk_ae_post_process(cop, sess, (uint8_t *)mdata[0]);
392 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
393 plt_dp_info("HW completion code 0x%x", res->compcode);
395 switch (res->compcode) {
396 case CPT_COMP_INSTERR:
397 plt_dp_err("Request failed with instruction error");
400 plt_dp_err("Request failed with DMA fault");
403 plt_dp_err("Request failed with hardware error");
407 "Request failed with unknown completion code");
412 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
413 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
414 sym_session_clear(cn10k_cryptodev_driver_id,
416 sz = rte_cryptodev_sym_get_existing_header_session_size(
418 memset(cop->sym->session, 0, sz);
419 rte_mempool_put(qp->sess_mp, cop->sym->session);
420 cop->sym->session = NULL;
426 cn10k_cpt_crypto_adapter_dequeue(uintptr_t get_work1)
428 struct cpt_inflight_req *infl_req;
429 struct rte_crypto_op *cop;
430 struct cnxk_cpt_qp *qp;
432 infl_req = (struct cpt_inflight_req *)(get_work1);
436 cn10k_cpt_dequeue_post_process(qp, infl_req->cop, infl_req);
438 if (unlikely(infl_req->op_flags & CPT_OP_FLAGS_METABUF))
439 rte_mempool_put(qp->meta_info.pool, infl_req->mdata);
441 rte_mempool_put(qp->ca.req_mp, infl_req);
442 return (uintptr_t)cop;
446 cn10k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
448 struct cpt_inflight_req *infl_req;
449 struct cnxk_cpt_qp *qp = qptr;
450 struct pending_queue *pend_q;
451 struct cpt_cn10k_res_s *res;
452 struct rte_crypto_op *cop;
455 pend_q = &qp->pend_q;
457 nb_pending = pend_q->pending_count;
459 if (nb_ops > nb_pending)
462 for (i = 0; i < nb_ops; i++) {
463 infl_req = &pend_q->req_queue[pend_q->deq_head];
465 res = (struct cpt_cn10k_res_s *)&infl_req->res;
467 if (unlikely(res->compcode == CPT_COMP_NOT_DONE)) {
468 if (unlikely(rte_get_timer_cycles() >
470 plt_err("Request timed out");
471 pend_q->time_out = rte_get_timer_cycles() +
472 DEFAULT_COMMAND_TIMEOUT *
478 MOD_INC(pend_q->deq_head, qp->lf.nb_desc);
484 cn10k_cpt_dequeue_post_process(qp, cop, infl_req);
486 if (unlikely(infl_req->op_flags & CPT_OP_FLAGS_METABUF))
487 rte_mempool_put(qp->meta_info.pool, infl_req->mdata);
490 pend_q->pending_count -= i;
496 cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)
498 dev->enqueue_burst = cn10k_cpt_enqueue_burst;
499 dev->dequeue_burst = cn10k_cpt_dequeue_burst;
505 cn10k_cpt_dev_info_get(struct rte_cryptodev *dev,
506 struct rte_cryptodev_info *info)
509 cnxk_cpt_dev_info_get(dev, info);
510 info->driver_id = cn10k_cryptodev_driver_id;
514 struct rte_cryptodev_ops cn10k_cpt_ops = {
515 /* Device control ops */
516 .dev_configure = cnxk_cpt_dev_config,
517 .dev_start = cnxk_cpt_dev_start,
518 .dev_stop = cnxk_cpt_dev_stop,
519 .dev_close = cnxk_cpt_dev_close,
520 .dev_infos_get = cn10k_cpt_dev_info_get,
524 .queue_pair_setup = cnxk_cpt_queue_pair_setup,
525 .queue_pair_release = cnxk_cpt_queue_pair_release,
527 /* Symmetric crypto ops */
528 .sym_session_get_size = cnxk_cpt_sym_session_get_size,
529 .sym_session_configure = cnxk_cpt_sym_session_configure,
530 .sym_session_clear = cnxk_cpt_sym_session_clear,
532 /* Asymmetric crypto ops */
533 .asym_session_get_size = cnxk_ae_session_size_get,
534 .asym_session_configure = cnxk_ae_session_cfg,
535 .asym_session_clear = cnxk_ae_session_clear,