1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include <cryptodev_pmd.h>
8 #include <rte_malloc.h>
9 #include <rte_security.h>
10 #include <rte_security_driver.h>
13 #include "cn10k_ipsec.h"
14 #include "cnxk_cryptodev.h"
15 #include "cnxk_cryptodev_ops.h"
16 #include "cnxk_ipsec.h"
17 #include "cnxk_security.h"
22 ipsec_cpt_inst_w7_get(struct roc_cpt *roc_cpt, void *sa)
27 w7.s.egrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE];
29 w7.s.cptr = (uint64_t)sa;
36 cn10k_ipsec_outb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,
37 struct rte_security_ipsec_xform *ipsec_xfrm,
38 struct rte_crypto_sym_xform *crypto_xfrm,
39 struct rte_security_session *sec_sess)
41 union roc_ot_ipsec_outb_param1 param1;
42 struct roc_ot_ipsec_outb_sa *sa_dptr;
43 struct cnxk_ipsec_outb_rlens rlens;
44 struct cn10k_sec_session *sess;
45 struct cn10k_ipsec_sa *sa;
46 union cpt_inst_w4 inst_w4;
50 sess = get_sec_session_private_data(sec_sess);
54 /* Allocate memory to be used as dptr for CPT ucode WRITE_SA op */
55 sa_dptr = plt_zmalloc(sizeof(struct roc_ot_ipsec_outb_sa), 8);
56 if (sa_dptr == NULL) {
57 plt_err("Couldn't allocate memory for SA dptr");
61 /* Translate security parameters to SA */
62 ret = cnxk_ot_ipsec_outb_sa_fill(sa_dptr, ipsec_xfrm, crypto_xfrm);
64 plt_err("Could not fill outbound session parameters");
68 sa->inst.w7 = ipsec_cpt_inst_w7_get(roc_cpt, out_sa);
71 /* Use IV from application in debug mode */
72 if (ipsec_xfrm->options.iv_gen_disable == 1) {
73 sa_dptr->w2.s.iv_src = ROC_IE_OT_SA_IV_SRC_FROM_SA;
74 if (crypto_xfrm->type == RTE_CRYPTO_SYM_XFORM_AEAD) {
75 sa->iv_offset = crypto_xfrm->aead.iv.offset;
76 sa->iv_length = crypto_xfrm->aead.iv.length;
78 sa->iv_offset = crypto_xfrm->cipher.iv.offset;
79 sa->iv_length = crypto_xfrm->cipher.iv.length;
83 if (ipsec_xfrm->options.iv_gen_disable != 0) {
84 plt_err("Application provided IV not supported");
90 sa->is_outbound = true;
92 /* Get Rlen calculation data */
93 ret = cnxk_ipsec_outb_rlens_get(&rlens, ipsec_xfrm, crypto_xfrm);
97 sa->max_extended_len = rlens.max_extended_len;
99 /* pre-populate CPT INST word 4 */
101 inst_w4.s.opcode_major = ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC;
105 /* Disable IP checksum computation by default */
106 param1.s.ip_csum_disable = ROC_IE_OT_SA_INNER_PKT_IP_CSUM_DISABLE;
108 if (ipsec_xfrm->options.ip_csum_enable) {
109 param1.s.ip_csum_disable =
110 ROC_IE_OT_SA_INNER_PKT_IP_CSUM_ENABLE;
113 /* Disable L4 checksum computation by default */
114 param1.s.l4_csum_disable = ROC_IE_OT_SA_INNER_PKT_L4_CSUM_DISABLE;
116 if (ipsec_xfrm->options.l4_csum_enable) {
117 param1.s.l4_csum_disable =
118 ROC_IE_OT_SA_INNER_PKT_L4_CSUM_ENABLE;
121 inst_w4.s.param1 = param1.u16;
123 sa->inst.w4 = inst_w4.u64;
125 if (ipsec_xfrm->options.stats == 1) {
126 /* Enable mib counters */
127 sa_dptr->w0.s.count_mib_bytes = 1;
128 sa_dptr->w0.s.count_mib_pkts = 1;
131 memset(out_sa, 0, sizeof(struct roc_ot_ipsec_outb_sa));
133 /* Copy word0 from sa_dptr to populate ctx_push_sz ctx_size fields */
134 memcpy(out_sa, sa_dptr, 8);
136 plt_atomic_thread_fence(__ATOMIC_SEQ_CST);
138 /* Write session using microcode opcode */
139 ret = roc_cpt_ctx_write(lf, sa_dptr, out_sa,
140 sizeof(struct roc_ot_ipsec_outb_sa));
142 plt_err("Could not write outbound session to hardware");
146 /* Trigger CTX flush so that data is written back to DRAM */
147 roc_cpt_lf_ctx_flush(lf, out_sa, false);
149 plt_atomic_thread_fence(__ATOMIC_SEQ_CST);
158 cn10k_ipsec_inb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,
159 struct rte_security_ipsec_xform *ipsec_xfrm,
160 struct rte_crypto_sym_xform *crypto_xfrm,
161 struct rte_security_session *sec_sess)
163 union roc_ot_ipsec_inb_param1 param1;
164 struct roc_ot_ipsec_inb_sa *sa_dptr;
165 struct cn10k_sec_session *sess;
166 struct cn10k_ipsec_sa *sa;
167 union cpt_inst_w4 inst_w4;
171 sess = get_sec_session_private_data(sec_sess);
175 /* Allocate memory to be used as dptr for CPT ucode WRITE_SA op */
176 sa_dptr = plt_zmalloc(sizeof(struct roc_ot_ipsec_inb_sa), 8);
177 if (sa_dptr == NULL) {
178 plt_err("Couldn't allocate memory for SA dptr");
182 /* Translate security parameters to SA */
183 ret = cnxk_ot_ipsec_inb_sa_fill(sa_dptr, ipsec_xfrm, crypto_xfrm);
185 plt_err("Could not fill inbound session parameters");
189 sa->is_outbound = false;
190 sa->inst.w7 = ipsec_cpt_inst_w7_get(roc_cpt, in_sa);
192 /* pre-populate CPT INST word 4 */
194 inst_w4.s.opcode_major = ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC;
198 /* Disable IP checksum verification by default */
199 param1.s.ip_csum_disable = ROC_IE_OT_SA_INNER_PKT_IP_CSUM_DISABLE;
201 if (ipsec_xfrm->options.ip_csum_enable) {
202 param1.s.ip_csum_disable =
203 ROC_IE_OT_SA_INNER_PKT_IP_CSUM_ENABLE;
206 /* Disable L4 checksum verification by default */
207 param1.s.l4_csum_disable = ROC_IE_OT_SA_INNER_PKT_L4_CSUM_DISABLE;
209 if (ipsec_xfrm->options.l4_csum_enable) {
210 param1.s.l4_csum_disable =
211 ROC_IE_OT_SA_INNER_PKT_L4_CSUM_ENABLE;
214 param1.s.esp_trailer_disable = 1;
216 inst_w4.s.param1 = param1.u16;
218 sa->inst.w4 = inst_w4.u64;
220 if (ipsec_xfrm->options.stats == 1) {
221 /* Enable mib counters */
222 sa_dptr->w0.s.count_mib_bytes = 1;
223 sa_dptr->w0.s.count_mib_pkts = 1;
226 memset(in_sa, 0, sizeof(struct roc_ot_ipsec_inb_sa));
228 /* Copy word0 from sa_dptr to populate ctx_push_sz ctx_size fields */
229 memcpy(in_sa, sa_dptr, 8);
231 plt_atomic_thread_fence(__ATOMIC_SEQ_CST);
233 /* Write session using microcode opcode */
234 ret = roc_cpt_ctx_write(lf, sa_dptr, in_sa,
235 sizeof(struct roc_ot_ipsec_inb_sa));
237 plt_err("Could not write inbound session to hardware");
241 /* Trigger CTX flush so that data is written back to DRAM */
242 roc_cpt_lf_ctx_flush(lf, in_sa, true);
244 plt_atomic_thread_fence(__ATOMIC_SEQ_CST);
253 cn10k_ipsec_session_create(void *dev,
254 struct rte_security_ipsec_xform *ipsec_xfrm,
255 struct rte_crypto_sym_xform *crypto_xfrm,
256 struct rte_security_session *sess)
258 struct rte_cryptodev *crypto_dev = dev;
259 struct roc_cpt *roc_cpt;
260 struct cnxk_cpt_vf *vf;
261 struct cnxk_cpt_qp *qp;
264 qp = crypto_dev->data->queue_pairs[0];
266 plt_err("Setup cpt queue pair before creating security session");
270 ret = cnxk_ipsec_xform_verify(ipsec_xfrm, crypto_xfrm);
274 vf = crypto_dev->data->dev_private;
277 if (ipsec_xfrm->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS)
278 return cn10k_ipsec_inb_sa_create(roc_cpt, &qp->lf, ipsec_xfrm,
281 return cn10k_ipsec_outb_sa_create(roc_cpt, &qp->lf, ipsec_xfrm,
286 cn10k_sec_session_create(void *device, struct rte_security_session_conf *conf,
287 struct rte_security_session *sess,
288 struct rte_mempool *mempool)
290 struct cn10k_sec_session *priv;
293 if (conf->action_type != RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL)
296 if (rte_mempool_get(mempool, (void **)&priv)) {
297 plt_err("Could not allocate security session private data");
301 set_sec_session_private_data(sess, priv);
303 if (conf->protocol != RTE_SECURITY_PROTOCOL_IPSEC) {
307 ret = cn10k_ipsec_session_create(device, &conf->ipsec,
308 conf->crypto_xform, sess);
315 rte_mempool_put(mempool, priv);
316 set_sec_session_private_data(sess, NULL);
321 cn10k_sec_session_destroy(void *dev, struct rte_security_session *sec_sess)
323 struct rte_cryptodev *crypto_dev = dev;
324 union roc_ot_ipsec_sa_word2 *w2;
325 struct cn10k_sec_session *sess;
326 struct rte_mempool *sess_mp;
327 struct cn10k_ipsec_sa *sa;
328 struct cnxk_cpt_qp *qp;
329 struct roc_cpt_lf *lf;
331 sess = get_sec_session_private_data(sec_sess);
335 qp = crypto_dev->data->queue_pairs[0];
343 /* Trigger CTX flush to write dirty data back to DRAM */
344 roc_cpt_lf_ctx_flush(lf, &sa->in_sa, false);
346 /* Wait for 1 ms so that flush is complete */
349 w2 = (union roc_ot_ipsec_sa_word2 *)&sa->in_sa.w2;
352 plt_atomic_thread_fence(__ATOMIC_SEQ_CST);
354 /* Trigger CTX reload to fetch new data from DRAM */
355 roc_cpt_lf_ctx_reload(lf, &sa->in_sa);
357 sess_mp = rte_mempool_from_obj(sess);
359 set_sec_session_private_data(sec_sess, NULL);
360 rte_mempool_put(sess_mp, sess);
366 cn10k_sec_session_get_size(void *device __rte_unused)
368 return sizeof(struct cn10k_sec_session);
372 cn10k_sec_session_stats_get(void *device, struct rte_security_session *sess,
373 struct rte_security_stats *stats)
375 struct rte_cryptodev *crypto_dev = device;
376 struct roc_ot_ipsec_outb_sa *out_sa;
377 struct roc_ot_ipsec_inb_sa *in_sa;
378 union roc_ot_ipsec_sa_word2 *w2;
379 struct cn10k_sec_session *priv;
380 struct cn10k_ipsec_sa *sa;
381 struct cnxk_cpt_qp *qp;
383 priv = get_sec_session_private_data(sess);
387 qp = crypto_dev->data->queue_pairs[0];
392 w2 = (union roc_ot_ipsec_sa_word2 *)&sa->in_sa.w2;
394 stats->protocol = RTE_SECURITY_PROTOCOL_IPSEC;
396 if (w2->s.dir == ROC_IE_SA_DIR_OUTBOUND) {
397 out_sa = &sa->out_sa;
398 roc_cpt_lf_ctx_flush(&qp->lf, out_sa, false);
400 stats->ipsec.opackets = out_sa->ctx.mib_pkts;
401 stats->ipsec.obytes = out_sa->ctx.mib_octs;
404 roc_cpt_lf_ctx_flush(&qp->lf, in_sa, false);
406 stats->ipsec.ipackets = in_sa->ctx.mib_pkts;
407 stats->ipsec.ibytes = in_sa->ctx.mib_octs;
414 cn10k_sec_session_update(void *device, struct rte_security_session *sess,
415 struct rte_security_session_conf *conf)
417 struct rte_cryptodev *crypto_dev = device;
418 struct cn10k_sec_session *priv;
419 struct roc_cpt *roc_cpt;
420 struct cnxk_cpt_qp *qp;
421 struct cnxk_cpt_vf *vf;
424 priv = get_sec_session_private_data(sess);
428 qp = crypto_dev->data->queue_pairs[0];
432 if (conf->ipsec.direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS)
435 ret = cnxk_ipsec_xform_verify(&conf->ipsec, conf->crypto_xform);
439 vf = crypto_dev->data->dev_private;
442 return cn10k_ipsec_outb_sa_create(roc_cpt, &qp->lf, &conf->ipsec,
443 conf->crypto_xform, sess);
446 /* Update platform specific security ops */
448 cn10k_sec_ops_override(void)
450 /* Update platform specific ops */
451 cnxk_sec_ops.session_create = cn10k_sec_session_create;
452 cnxk_sec_ops.session_destroy = cn10k_sec_session_destroy;
453 cnxk_sec_ops.session_get_size = cn10k_sec_session_get_size;
454 cnxk_sec_ops.session_stats_get = cn10k_sec_session_stats_get;
455 cnxk_sec_ops.session_update = cn10k_sec_session_update;