drivers/crypto/cnxk/cn10k_ipsec_la_ops.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef __CN10K_IPSEC_LA_OPS_H__
   6 #define __CN10K_IPSEC_LA_OPS_H__
   7
   8 #include <rte_crypto_sym.h>
   9 #include <rte_security.h>
  10
  11 #include "cn10k_cryptodev.h"
  12 #include "cn10k_ipsec.h"
  13 #include "cnxk_cryptodev.h"
  14
  15 static inline void
  16 ipsec_po_sa_iv_set(struct cn10k_ipsec_sa *sess, struct rte_crypto_op *cop)
  17 {
  18         uint64_t *iv = &sess->out_sa.iv.u64[0];
  19         uint64_t *tmp_iv;
  20
  21         memcpy(iv, rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset),
  22                16);
  23         tmp_iv = (uint64_t *)iv;
  24         *tmp_iv = rte_be_to_cpu_64(*tmp_iv);
  25
  26         tmp_iv = (uint64_t *)(iv + 1);
  27         *tmp_iv = rte_be_to_cpu_64(*tmp_iv);
  28 }
  29
  30 static inline void
  31 ipsec_po_sa_aes_gcm_iv_set(struct cn10k_ipsec_sa *sess,
  32                            struct rte_crypto_op *cop)
  33 {
  34         uint8_t *iv = &sess->out_sa.iv.s.iv_dbg1[0];
  35         uint32_t *tmp_iv;
  36
  37         memcpy(iv, rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset),
  38                4);
  39         tmp_iv = (uint32_t *)iv;
  40         *tmp_iv = rte_be_to_cpu_32(*tmp_iv);
  41
  42         iv = &sess->out_sa.iv.s.iv_dbg2[0];
  43         memcpy(iv,
  44                rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset + 4),
  45                4);
  46         tmp_iv = (uint32_t *)iv;
  47         *tmp_iv = rte_be_to_cpu_32(*tmp_iv);
  48 }
  49
  50 static __rte_always_inline int
  51 process_outb_sa(struct rte_crypto_op *cop, struct cn10k_ipsec_sa *sess,
  52                 struct cpt_inst_s *inst)
  53 {
  54         struct rte_crypto_sym_op *sym_op = cop->sym;
  55         struct rte_mbuf *m_src = sym_op->m_src;
  56         uint64_t inst_w4_u64 = sess->inst.w4;
  57
  58         if (unlikely(rte_pktmbuf_tailroom(m_src) < sess->max_extended_len)) {
  59                 plt_dp_err("Not enough tail room");
  60                 return -ENOMEM;
  61         }
  62
  63 #ifdef LA_IPSEC_DEBUG
  64         if (sess->out_sa.w2.s.iv_src == ROC_IE_OT_SA_IV_SRC_FROM_SA) {
  65                 if (sess->out_sa.w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_GCM)
  66                         ipsec_po_sa_aes_gcm_iv_set(sess, cop);
  67                 else
  68                         ipsec_po_sa_iv_set(sess, cop);
  69         }
  70 #endif
  71
  72         if (m_src->ol_flags & PKT_TX_IP_CKSUM)
  73                 inst_w4_u64 &= ~BIT_ULL(33);
  74
  75         if (m_src->ol_flags & PKT_TX_L4_MASK)
  76                 inst_w4_u64 &= ~BIT_ULL(32);
  77
  78         /* Prepare CPT instruction */
  79         inst->w4.u64 = inst_w4_u64;
  80         inst->w4.s.dlen = rte_pktmbuf_pkt_len(m_src);
  81         inst->dptr = rte_pktmbuf_iova(m_src);
  82         inst->rptr = inst->dptr;
  83
  84         return 0;
  85 }
  86
  87 static __rte_always_inline int
  88 process_inb_sa(struct rte_crypto_op *cop, struct cn10k_ipsec_sa *sa,
  89                struct cpt_inst_s *inst)
  90 {
  91         struct rte_crypto_sym_op *sym_op = cop->sym;
  92         struct rte_mbuf *m_src = sym_op->m_src;
  93
  94         /* Prepare CPT instruction */
  95         inst->w4.u64 = sa->inst.w4;
  96         inst->w4.s.dlen = rte_pktmbuf_pkt_len(m_src);
  97         inst->dptr = rte_pktmbuf_iova(m_src);
  98         inst->rptr = inst->dptr;
  99
 100         return 0;
 101 }
 102
 103 #endif /* __CN10K_IPSEC_LA_OPS_H__ */