4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
5 * Copyright (c) 2016 NXP. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Freescale Semiconductor, Inc nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_cryptodev.h>
39 #include <rte_malloc.h>
40 #include <rte_memcpy.h>
41 #include <rte_string_fns.h>
42 #include <rte_cycles.h>
43 #include <rte_kvargs.h>
45 #include <rte_cryptodev_pmd.h>
46 #include <rte_common.h>
47 #include <rte_fslmc.h>
48 #include <fslmc_vfio.h>
49 #include <dpaa2_hw_pvt.h>
50 #include <dpaa2_hw_dpio.h>
51 #include <dpaa2_hw_mempool.h>
52 #include <fsl_dpseci.h>
53 #include <fsl_mc_sys.h>
55 #include "dpaa2_sec_priv.h"
56 #include "dpaa2_sec_logs.h"
58 /* RTA header files */
59 #include <hw/desc/ipsec.h>
60 #include <hw/desc/algo.h>
62 /* Minimum job descriptor consists of a oneword job descriptor HEADER and
63 * a pointer to the shared descriptor
65 #define MIN_JOB_DESC_SIZE (CAAM_CMD_SZ + CAAM_PTR_SZ)
66 #define FSL_VENDOR_ID 0x1957
67 #define FSL_DEVICE_ID 0x410
68 #define FSL_SUBSYSTEM_SEC 1
69 #define FSL_MC_DPSECI_DEVID 3
72 #define TDES_CBC_IV_LEN 8
73 #define AES_CBC_IV_LEN 16
74 enum rta_sec_era rta_sec_era = RTA_SEC_ERA_8;
77 build_authenc_fd(dpaa2_sec_session *sess,
78 struct rte_crypto_op *op,
79 struct qbman_fd *fd, uint16_t bpid)
81 struct rte_crypto_sym_op *sym_op = op->sym;
82 struct ctxt_priv *priv = sess->ctxt;
83 struct qbman_fle *fle, *sge;
84 struct sec_flow_context *flc;
85 uint32_t auth_only_len = sym_op->auth.data.length -
86 sym_op->cipher.data.length;
87 int icv_len = sess->digest_length;
89 uint32_t mem_len = (7 * sizeof(struct qbman_fle)) + icv_len;
90 uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
93 PMD_INIT_FUNC_TRACE();
95 /* we are using the first FLE entry to store Mbuf.
96 * Currently we donot know which FLE has the mbuf stored.
97 * So while retreiving we can go back 1 FLE from the FD -ADDR
98 * to get the MBUF Addr from the previous FLE.
99 * We can have a better approach to use the inline Mbuf
101 fle = rte_zmalloc(NULL, mem_len, RTE_CACHE_LINE_SIZE);
103 RTE_LOG(ERR, PMD, "Memory alloc failed for SGE\n");
106 DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
109 if (likely(bpid < MAX_BPID)) {
110 DPAA2_SET_FD_BPID(fd, bpid);
111 DPAA2_SET_FLE_BPID(fle, bpid);
112 DPAA2_SET_FLE_BPID(fle + 1, bpid);
113 DPAA2_SET_FLE_BPID(sge, bpid);
114 DPAA2_SET_FLE_BPID(sge + 1, bpid);
115 DPAA2_SET_FLE_BPID(sge + 2, bpid);
116 DPAA2_SET_FLE_BPID(sge + 3, bpid);
118 DPAA2_SET_FD_IVP(fd);
119 DPAA2_SET_FLE_IVP(fle);
120 DPAA2_SET_FLE_IVP((fle + 1));
121 DPAA2_SET_FLE_IVP(sge);
122 DPAA2_SET_FLE_IVP((sge + 1));
123 DPAA2_SET_FLE_IVP((sge + 2));
124 DPAA2_SET_FLE_IVP((sge + 3));
127 /* Save the shared descriptor */
128 flc = &priv->flc_desc[0].flc;
129 /* Configure FD as a FRAME LIST */
130 DPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(fle));
131 DPAA2_SET_FD_COMPOUND_FMT(fd);
132 DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));
134 PMD_TX_LOG(DEBUG, "auth_off: 0x%x/length %d, digest-len=%d\n"
135 "cipher_off: 0x%x/length %d, iv-len=%d data_off: 0x%x\n",
136 sym_op->auth.data.offset,
137 sym_op->auth.data.length,
139 sym_op->cipher.data.offset,
140 sym_op->cipher.data.length,
142 sym_op->m_src->data_off);
144 /* Configure Output FLE with Scatter/Gather Entry */
145 DPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sge));
147 DPAA2_SET_FLE_INTERNAL_JD(fle, auth_only_len);
148 fle->length = (sess->dir == DIR_ENC) ?
149 (sym_op->cipher.data.length + icv_len) :
150 sym_op->cipher.data.length;
152 DPAA2_SET_FLE_SG_EXT(fle);
154 /* Configure Output SGE for Encap/Decap */
155 DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));
156 DPAA2_SET_FLE_OFFSET(sge, sym_op->cipher.data.offset +
157 sym_op->m_src->data_off);
158 sge->length = sym_op->cipher.data.length;
160 if (sess->dir == DIR_ENC) {
162 DPAA2_SET_FLE_ADDR(sge,
163 DPAA2_VADDR_TO_IOVA(sym_op->auth.digest.data));
164 sge->length = sess->digest_length;
165 DPAA2_SET_FD_LEN(fd, (sym_op->auth.data.length +
168 DPAA2_SET_FLE_FIN(sge);
173 /* Configure Input FLE with Scatter/Gather Entry */
174 DPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sge));
175 DPAA2_SET_FLE_SG_EXT(fle);
176 DPAA2_SET_FLE_FIN(fle);
177 fle->length = (sess->dir == DIR_ENC) ?
178 (sym_op->auth.data.length + sess->iv.length) :
179 (sym_op->auth.data.length + sess->iv.length +
180 sess->digest_length);
182 /* Configure Input SGE for Encap/Decap */
183 DPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(iv_ptr));
184 sge->length = sess->iv.length;
187 DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));
188 DPAA2_SET_FLE_OFFSET(sge, sym_op->auth.data.offset +
189 sym_op->m_src->data_off);
190 sge->length = sym_op->auth.data.length;
191 if (sess->dir == DIR_DEC) {
193 old_icv = (uint8_t *)(sge + 1);
194 memcpy(old_icv, sym_op->auth.digest.data,
195 sess->digest_length);
196 memset(sym_op->auth.digest.data, 0, sess->digest_length);
197 DPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(old_icv));
198 sge->length = sess->digest_length;
199 DPAA2_SET_FD_LEN(fd, (sym_op->auth.data.length +
200 sess->digest_length +
203 DPAA2_SET_FLE_FIN(sge);
205 DPAA2_SET_FLE_INTERNAL_JD(fle, auth_only_len);
206 DPAA2_SET_FD_INTERNAL_JD(fd, auth_only_len);
212 build_auth_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
213 struct qbman_fd *fd, uint16_t bpid)
215 struct rte_crypto_sym_op *sym_op = op->sym;
216 struct qbman_fle *fle, *sge;
217 uint32_t mem_len = (sess->dir == DIR_ENC) ?
218 (3 * sizeof(struct qbman_fle)) :
219 (5 * sizeof(struct qbman_fle) +
220 sess->digest_length);
221 struct sec_flow_context *flc;
222 struct ctxt_priv *priv = sess->ctxt;
225 PMD_INIT_FUNC_TRACE();
227 fle = rte_zmalloc(NULL, mem_len, RTE_CACHE_LINE_SIZE);
229 RTE_LOG(ERR, PMD, "Memory alloc failed for FLE\n");
232 /* TODO we are using the first FLE entry to store Mbuf.
233 * Currently we donot know which FLE has the mbuf stored.
234 * So while retreiving we can go back 1 FLE from the FD -ADDR
235 * to get the MBUF Addr from the previous FLE.
236 * We can have a better approach to use the inline Mbuf
238 DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
241 if (likely(bpid < MAX_BPID)) {
242 DPAA2_SET_FD_BPID(fd, bpid);
243 DPAA2_SET_FLE_BPID(fle, bpid);
244 DPAA2_SET_FLE_BPID(fle + 1, bpid);
246 DPAA2_SET_FD_IVP(fd);
247 DPAA2_SET_FLE_IVP(fle);
248 DPAA2_SET_FLE_IVP((fle + 1));
250 flc = &priv->flc_desc[DESC_INITFINAL].flc;
251 DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));
253 DPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sym_op->auth.digest.data));
254 fle->length = sess->digest_length;
256 DPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(fle));
257 DPAA2_SET_FD_COMPOUND_FMT(fd);
260 if (sess->dir == DIR_ENC) {
261 DPAA2_SET_FLE_ADDR(fle,
262 DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));
263 DPAA2_SET_FLE_OFFSET(fle, sym_op->auth.data.offset +
264 sym_op->m_src->data_off);
265 DPAA2_SET_FD_LEN(fd, sym_op->auth.data.length);
266 fle->length = sym_op->auth.data.length;
269 DPAA2_SET_FLE_SG_EXT(fle);
270 DPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sge));
272 if (likely(bpid < MAX_BPID)) {
273 DPAA2_SET_FLE_BPID(sge, bpid);
274 DPAA2_SET_FLE_BPID(sge + 1, bpid);
276 DPAA2_SET_FLE_IVP(sge);
277 DPAA2_SET_FLE_IVP((sge + 1));
279 DPAA2_SET_FLE_ADDR(sge,
280 DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));
281 DPAA2_SET_FLE_OFFSET(sge, sym_op->auth.data.offset +
282 sym_op->m_src->data_off);
284 DPAA2_SET_FD_LEN(fd, sym_op->auth.data.length +
285 sess->digest_length);
286 sge->length = sym_op->auth.data.length;
288 old_digest = (uint8_t *)(sge + 1);
289 rte_memcpy(old_digest, sym_op->auth.digest.data,
290 sess->digest_length);
291 memset(sym_op->auth.digest.data, 0, sess->digest_length);
292 DPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(old_digest));
293 sge->length = sess->digest_length;
294 fle->length = sym_op->auth.data.length +
296 DPAA2_SET_FLE_FIN(sge);
298 DPAA2_SET_FLE_FIN(fle);
304 build_cipher_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
305 struct qbman_fd *fd, uint16_t bpid)
307 struct rte_crypto_sym_op *sym_op = op->sym;
308 struct qbman_fle *fle, *sge;
309 uint32_t mem_len = (5 * sizeof(struct qbman_fle));
310 struct sec_flow_context *flc;
311 struct ctxt_priv *priv = sess->ctxt;
312 uint8_t *iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
315 PMD_INIT_FUNC_TRACE();
317 /* todo - we can use some mempool to avoid malloc here */
318 fle = rte_zmalloc(NULL, mem_len, RTE_CACHE_LINE_SIZE);
320 RTE_LOG(ERR, PMD, "Memory alloc failed for SGE\n");
323 /* TODO we are using the first FLE entry to store Mbuf.
324 * Currently we donot know which FLE has the mbuf stored.
325 * So while retreiving we can go back 1 FLE from the FD -ADDR
326 * to get the MBUF Addr from the previous FLE.
327 * We can have a better approach to use the inline Mbuf
329 DPAA2_SET_FLE_ADDR(fle, DPAA2_OP_VADDR_TO_IOVA(op));
333 if (likely(bpid < MAX_BPID)) {
334 DPAA2_SET_FD_BPID(fd, bpid);
335 DPAA2_SET_FLE_BPID(fle, bpid);
336 DPAA2_SET_FLE_BPID(fle + 1, bpid);
337 DPAA2_SET_FLE_BPID(sge, bpid);
338 DPAA2_SET_FLE_BPID(sge + 1, bpid);
340 DPAA2_SET_FD_IVP(fd);
341 DPAA2_SET_FLE_IVP(fle);
342 DPAA2_SET_FLE_IVP((fle + 1));
343 DPAA2_SET_FLE_IVP(sge);
344 DPAA2_SET_FLE_IVP((sge + 1));
347 flc = &priv->flc_desc[0].flc;
348 DPAA2_SET_FD_ADDR(fd, DPAA2_VADDR_TO_IOVA(fle));
349 DPAA2_SET_FD_LEN(fd, sym_op->cipher.data.length +
351 DPAA2_SET_FD_COMPOUND_FMT(fd);
352 DPAA2_SET_FD_FLC(fd, DPAA2_VADDR_TO_IOVA(flc));
354 PMD_TX_LOG(DEBUG, "cipher_off: 0x%x/length %d,ivlen=%d data_off: 0x%x",
355 sym_op->cipher.data.offset,
356 sym_op->cipher.data.length,
358 sym_op->m_src->data_off);
360 DPAA2_SET_FLE_ADDR(fle, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));
361 DPAA2_SET_FLE_OFFSET(fle, sym_op->cipher.data.offset +
362 sym_op->m_src->data_off);
364 fle->length = sym_op->cipher.data.length + sess->iv.length;
366 PMD_TX_LOG(DEBUG, "1 - flc = %p, fle = %p FLEaddr = %x-%x, length %d",
367 flc, fle, fle->addr_hi, fle->addr_lo, fle->length);
371 DPAA2_SET_FLE_ADDR(fle, DPAA2_VADDR_TO_IOVA(sge));
372 fle->length = sym_op->cipher.data.length + sess->iv.length;
374 DPAA2_SET_FLE_SG_EXT(fle);
376 DPAA2_SET_FLE_ADDR(sge, DPAA2_VADDR_TO_IOVA(iv_ptr));
377 sge->length = sess->iv.length;
380 DPAA2_SET_FLE_ADDR(sge, DPAA2_MBUF_VADDR_TO_IOVA(sym_op->m_src));
381 DPAA2_SET_FLE_OFFSET(sge, sym_op->cipher.data.offset +
382 sym_op->m_src->data_off);
384 sge->length = sym_op->cipher.data.length;
385 DPAA2_SET_FLE_FIN(sge);
386 DPAA2_SET_FLE_FIN(fle);
388 PMD_TX_LOG(DEBUG, "fdaddr =%p bpid =%d meta =%d off =%d, len =%d",
389 (void *)DPAA2_GET_FD_ADDR(fd),
390 DPAA2_GET_FD_BPID(fd),
391 rte_dpaa2_bpid_info[bpid].meta_data_size,
392 DPAA2_GET_FD_OFFSET(fd),
393 DPAA2_GET_FD_LEN(fd));
399 build_sec_fd(dpaa2_sec_session *sess, struct rte_crypto_op *op,
400 struct qbman_fd *fd, uint16_t bpid)
404 PMD_INIT_FUNC_TRACE();
406 switch (sess->ctxt_type) {
407 case DPAA2_SEC_CIPHER:
408 ret = build_cipher_fd(sess, op, fd, bpid);
411 ret = build_auth_fd(sess, op, fd, bpid);
413 case DPAA2_SEC_CIPHER_HASH:
414 ret = build_authenc_fd(sess, op, fd, bpid);
416 case DPAA2_SEC_HASH_CIPHER:
418 RTE_LOG(ERR, PMD, "error: Unsupported session\n");
424 dpaa2_sec_enqueue_burst(void *qp, struct rte_crypto_op **ops,
427 /* Function to transmit the frames to given device and VQ*/
430 struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
431 uint32_t frames_to_send;
432 struct qbman_eq_desc eqdesc;
433 struct dpaa2_sec_qp *dpaa2_qp = (struct dpaa2_sec_qp *)qp;
434 struct qbman_swp *swp;
436 /*todo - need to support multiple buffer pools */
438 struct rte_mempool *mb_pool;
439 dpaa2_sec_session *sess;
441 if (unlikely(nb_ops == 0))
444 if (ops[0]->sess_type != RTE_CRYPTO_OP_WITH_SESSION) {
445 RTE_LOG(ERR, PMD, "sessionless crypto op not supported\n");
448 /*Prepare enqueue descriptor*/
449 qbman_eq_desc_clear(&eqdesc);
450 qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ);
451 qbman_eq_desc_set_response(&eqdesc, 0, 0);
452 qbman_eq_desc_set_fq(&eqdesc, dpaa2_qp->tx_vq.fqid);
454 if (!DPAA2_PER_LCORE_SEC_DPIO) {
455 ret = dpaa2_affine_qbman_swp_sec();
457 RTE_LOG(ERR, PMD, "Failure in affining portal\n");
461 swp = DPAA2_PER_LCORE_SEC_PORTAL;
464 frames_to_send = (nb_ops >> 3) ? MAX_TX_RING_SLOTS : nb_ops;
466 for (loop = 0; loop < frames_to_send; loop++) {
467 /*Clear the unused FD fields before sending*/
468 memset(&fd_arr[loop], 0, sizeof(struct qbman_fd));
469 sess = (dpaa2_sec_session *)
470 (*ops)->sym->session->_private;
471 mb_pool = (*ops)->sym->m_src->pool;
472 bpid = mempool_to_bpid(mb_pool);
473 ret = build_sec_fd(sess, *ops, &fd_arr[loop], bpid);
475 PMD_DRV_LOG(ERR, "error: Improper packet"
476 " contents for crypto operation\n");
482 while (loop < frames_to_send) {
483 loop += qbman_swp_send_multiple(swp, &eqdesc,
485 frames_to_send - loop);
488 num_tx += frames_to_send;
489 nb_ops -= frames_to_send;
492 dpaa2_qp->tx_vq.tx_pkts += num_tx;
493 dpaa2_qp->tx_vq.err_pkts += nb_ops;
497 static inline struct rte_crypto_op *
498 sec_fd_to_mbuf(const struct qbman_fd *fd)
500 struct qbman_fle *fle;
501 struct rte_crypto_op *op;
503 fle = (struct qbman_fle *)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
505 PMD_RX_LOG(DEBUG, "FLE addr = %x - %x, offset = %x",
506 fle->addr_hi, fle->addr_lo, fle->fin_bpid_offset);
508 /* we are using the first FLE entry to store Mbuf.
509 * Currently we donot know which FLE has the mbuf stored.
510 * So while retreiving we can go back 1 FLE from the FD -ADDR
511 * to get the MBUF Addr from the previous FLE.
512 * We can have a better approach to use the inline Mbuf
515 if (unlikely(DPAA2_GET_FD_IVP(fd))) {
516 /* TODO complete it. */
517 RTE_LOG(ERR, PMD, "error: Non inline buffer - WHAT to DO?");
520 op = (struct rte_crypto_op *)DPAA2_IOVA_TO_VADDR(
521 DPAA2_GET_FLE_ADDR((fle - 1)));
524 rte_prefetch0(op->sym->m_src);
526 PMD_RX_LOG(DEBUG, "mbuf %p BMAN buf addr %p",
527 (void *)op->sym->m_src, op->sym->m_src->buf_addr);
529 PMD_RX_LOG(DEBUG, "fdaddr =%p bpid =%d meta =%d off =%d, len =%d",
530 (void *)DPAA2_GET_FD_ADDR(fd),
531 DPAA2_GET_FD_BPID(fd),
532 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size,
533 DPAA2_GET_FD_OFFSET(fd),
534 DPAA2_GET_FD_LEN(fd));
536 /* free the fle memory */
543 dpaa2_sec_dequeue_burst(void *qp, struct rte_crypto_op **ops,
546 /* Function is responsible to receive frames for a given device and VQ*/
547 struct dpaa2_sec_qp *dpaa2_qp = (struct dpaa2_sec_qp *)qp;
548 struct qbman_result *dq_storage;
549 uint32_t fqid = dpaa2_qp->rx_vq.fqid;
551 uint8_t is_last = 0, status;
552 struct qbman_swp *swp;
553 const struct qbman_fd *fd;
554 struct qbman_pull_desc pulldesc;
556 if (!DPAA2_PER_LCORE_SEC_DPIO) {
557 ret = dpaa2_affine_qbman_swp_sec();
559 RTE_LOG(ERR, PMD, "Failure in affining portal\n");
563 swp = DPAA2_PER_LCORE_SEC_PORTAL;
564 dq_storage = dpaa2_qp->rx_vq.q_storage->dq_storage[0];
566 qbman_pull_desc_clear(&pulldesc);
567 qbman_pull_desc_set_numframes(&pulldesc,
568 (nb_ops > DPAA2_DQRR_RING_SIZE) ?
569 DPAA2_DQRR_RING_SIZE : nb_ops);
570 qbman_pull_desc_set_fq(&pulldesc, fqid);
571 qbman_pull_desc_set_storage(&pulldesc, dq_storage,
572 (dma_addr_t)DPAA2_VADDR_TO_IOVA(dq_storage),
575 /*Issue a volatile dequeue command. */
577 if (qbman_swp_pull(swp, &pulldesc)) {
578 RTE_LOG(WARNING, PMD, "SEC VDQ command is not issued."
580 /* Portal was busy, try again */
586 /* Receive the packets till Last Dequeue entry is found with
587 * respect to the above issues PULL command.
590 /* Check if the previous issued command is completed.
591 * Also seems like the SWP is shared between the Ethernet Driver
592 * and the SEC driver.
594 while (!qbman_check_command_complete(swp, dq_storage))
597 /* Loop until the dq_storage is updated with
600 while (!qbman_result_has_new_result(swp, dq_storage))
602 /* Check whether Last Pull command is Expired and
603 * setting Condition for Loop termination
605 if (qbman_result_DQ_is_pull_complete(dq_storage)) {
607 /* Check for valid frame. */
608 status = (uint8_t)qbman_result_DQ_flags(dq_storage);
610 (status & QBMAN_DQ_STAT_VALIDFRAME) == 0)) {
611 PMD_RX_LOG(DEBUG, "No frame is delivered");
616 fd = qbman_result_DQ_fd(dq_storage);
617 ops[num_rx] = sec_fd_to_mbuf(fd);
619 if (unlikely(fd->simple.frc)) {
620 /* TODO Parse SEC errors */
621 RTE_LOG(ERR, PMD, "SEC returned Error - %x\n",
623 ops[num_rx]->status = RTE_CRYPTO_OP_STATUS_ERROR;
625 ops[num_rx]->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
630 } /* End of Packet Rx loop */
632 dpaa2_qp->rx_vq.rx_pkts += num_rx;
634 PMD_RX_LOG(DEBUG, "SEC Received %d Packets", num_rx);
635 /*Return the total number of packets received to DPAA2 app*/
639 /** Release queue pair */
641 dpaa2_sec_queue_pair_release(struct rte_cryptodev *dev, uint16_t queue_pair_id)
643 struct dpaa2_sec_qp *qp =
644 (struct dpaa2_sec_qp *)dev->data->queue_pairs[queue_pair_id];
646 PMD_INIT_FUNC_TRACE();
648 if (qp->rx_vq.q_storage) {
649 dpaa2_free_dq_storage(qp->rx_vq.q_storage);
650 rte_free(qp->rx_vq.q_storage);
654 dev->data->queue_pairs[queue_pair_id] = NULL;
659 /** Setup a queue pair */
661 dpaa2_sec_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
662 __rte_unused const struct rte_cryptodev_qp_conf *qp_conf,
663 __rte_unused int socket_id)
665 struct dpaa2_sec_dev_private *priv = dev->data->dev_private;
666 struct dpaa2_sec_qp *qp;
667 struct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw;
668 struct dpseci_rx_queue_cfg cfg;
671 PMD_INIT_FUNC_TRACE();
673 /* If qp is already in use free ring memory and qp metadata. */
674 if (dev->data->queue_pairs[qp_id] != NULL) {
675 PMD_DRV_LOG(INFO, "QP already setup");
679 PMD_DRV_LOG(DEBUG, "dev =%p, queue =%d, conf =%p",
680 dev, qp_id, qp_conf);
682 memset(&cfg, 0, sizeof(struct dpseci_rx_queue_cfg));
684 qp = rte_malloc(NULL, sizeof(struct dpaa2_sec_qp),
685 RTE_CACHE_LINE_SIZE);
687 RTE_LOG(ERR, PMD, "malloc failed for rx/tx queues\n");
693 qp->rx_vq.q_storage = rte_malloc("sec dq storage",
694 sizeof(struct queue_storage_info_t),
695 RTE_CACHE_LINE_SIZE);
696 if (!qp->rx_vq.q_storage) {
697 RTE_LOG(ERR, PMD, "malloc failed for q_storage\n");
700 memset(qp->rx_vq.q_storage, 0, sizeof(struct queue_storage_info_t));
702 if (dpaa2_alloc_dq_storage(qp->rx_vq.q_storage)) {
703 RTE_LOG(ERR, PMD, "dpaa2_alloc_dq_storage failed\n");
707 dev->data->queue_pairs[qp_id] = qp;
709 cfg.options = cfg.options | DPSECI_QUEUE_OPT_USER_CTX;
710 cfg.user_ctx = (uint64_t)(&qp->rx_vq);
711 retcode = dpseci_set_rx_queue(dpseci, CMD_PRI_LOW, priv->token,
716 /** Start queue pair */
718 dpaa2_sec_queue_pair_start(__rte_unused struct rte_cryptodev *dev,
719 __rte_unused uint16_t queue_pair_id)
721 PMD_INIT_FUNC_TRACE();
726 /** Stop queue pair */
728 dpaa2_sec_queue_pair_stop(__rte_unused struct rte_cryptodev *dev,
729 __rte_unused uint16_t queue_pair_id)
731 PMD_INIT_FUNC_TRACE();
736 /** Return the number of allocated queue pairs */
738 dpaa2_sec_queue_pair_count(struct rte_cryptodev *dev)
740 PMD_INIT_FUNC_TRACE();
742 return dev->data->nb_queue_pairs;
745 /** Returns the size of the aesni gcm session structure */
747 dpaa2_sec_session_get_size(struct rte_cryptodev *dev __rte_unused)
749 PMD_INIT_FUNC_TRACE();
751 return sizeof(dpaa2_sec_session);
755 dpaa2_sec_session_initialize(struct rte_mempool *mp __rte_unused,
756 void *sess __rte_unused)
758 PMD_INIT_FUNC_TRACE();
762 dpaa2_sec_cipher_init(struct rte_cryptodev *dev,
763 struct rte_crypto_sym_xform *xform,
764 dpaa2_sec_session *session)
766 struct dpaa2_sec_cipher_ctxt *ctxt = &session->ext_params.cipher_ctxt;
767 struct alginfo cipherdata;
769 struct ctxt_priv *priv;
770 struct sec_flow_context *flc;
772 PMD_INIT_FUNC_TRACE();
774 /* For SEC CIPHER only one descriptor is required. */
775 priv = (struct ctxt_priv *)rte_zmalloc(NULL,
776 sizeof(struct ctxt_priv) + sizeof(struct sec_flc_desc),
777 RTE_CACHE_LINE_SIZE);
779 RTE_LOG(ERR, PMD, "No Memory for priv CTXT");
783 flc = &priv->flc_desc[0].flc;
785 session->cipher_key.data = rte_zmalloc(NULL, xform->cipher.key.length,
786 RTE_CACHE_LINE_SIZE);
787 if (session->cipher_key.data == NULL) {
788 RTE_LOG(ERR, PMD, "No Memory for cipher key");
792 session->cipher_key.length = xform->cipher.key.length;
794 memcpy(session->cipher_key.data, xform->cipher.key.data,
795 xform->cipher.key.length);
796 cipherdata.key = (uint64_t)session->cipher_key.data;
797 cipherdata.keylen = session->cipher_key.length;
798 cipherdata.key_enc_flags = 0;
799 cipherdata.key_type = RTA_DATA_IMM;
801 /* Set IV parameters */
802 session->iv.offset = xform->cipher.iv.offset;
803 session->iv.length = xform->cipher.iv.length;
805 switch (xform->cipher.algo) {
806 case RTE_CRYPTO_CIPHER_AES_CBC:
807 cipherdata.algtype = OP_ALG_ALGSEL_AES;
808 cipherdata.algmode = OP_ALG_AAI_CBC;
809 session->cipher_alg = RTE_CRYPTO_CIPHER_AES_CBC;
810 ctxt->iv.length = AES_CBC_IV_LEN;
812 case RTE_CRYPTO_CIPHER_3DES_CBC:
813 cipherdata.algtype = OP_ALG_ALGSEL_3DES;
814 cipherdata.algmode = OP_ALG_AAI_CBC;
815 session->cipher_alg = RTE_CRYPTO_CIPHER_3DES_CBC;
816 ctxt->iv.length = TDES_CBC_IV_LEN;
818 case RTE_CRYPTO_CIPHER_AES_CTR:
819 case RTE_CRYPTO_CIPHER_3DES_CTR:
820 case RTE_CRYPTO_CIPHER_AES_ECB:
821 case RTE_CRYPTO_CIPHER_3DES_ECB:
822 case RTE_CRYPTO_CIPHER_AES_XTS:
823 case RTE_CRYPTO_CIPHER_AES_F8:
824 case RTE_CRYPTO_CIPHER_ARC4:
825 case RTE_CRYPTO_CIPHER_KASUMI_F8:
826 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
827 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
828 case RTE_CRYPTO_CIPHER_NULL:
829 RTE_LOG(ERR, PMD, "Crypto: Unsupported Cipher alg %u",
833 RTE_LOG(ERR, PMD, "Crypto: Undefined Cipher specified %u\n",
837 session->dir = (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ?
840 bufsize = cnstr_shdsc_blkcipher(priv->flc_desc[0].desc, 1, 0,
841 &cipherdata, NULL, ctxt->iv.length,
844 RTE_LOG(ERR, PMD, "Crypto: Descriptor build failed\n");
849 flc->mode_bits = 0x8000;
851 flc->word1_sdl = (uint8_t)bufsize;
852 flc->word2_rflc_31_0 = lower_32_bits(
853 (uint64_t)&(((struct dpaa2_sec_qp *)
854 dev->data->queue_pairs[0])->rx_vq));
855 flc->word3_rflc_63_32 = upper_32_bits(
856 (uint64_t)&(((struct dpaa2_sec_qp *)
857 dev->data->queue_pairs[0])->rx_vq));
858 session->ctxt = priv;
860 for (i = 0; i < bufsize; i++)
861 PMD_DRV_LOG(DEBUG, "DESC[%d]:0x%x\n",
862 i, priv->flc_desc[0].desc[i]);
867 rte_free(session->cipher_key.data);
873 dpaa2_sec_auth_init(struct rte_cryptodev *dev,
874 struct rte_crypto_sym_xform *xform,
875 dpaa2_sec_session *session)
877 struct dpaa2_sec_auth_ctxt *ctxt = &session->ext_params.auth_ctxt;
878 struct alginfo authdata;
879 unsigned int bufsize;
880 struct ctxt_priv *priv;
881 struct sec_flow_context *flc;
883 PMD_INIT_FUNC_TRACE();
885 /* For SEC AUTH three descriptors are required for various stages */
886 priv = (struct ctxt_priv *)rte_zmalloc(NULL,
887 sizeof(struct ctxt_priv) + 3 *
888 sizeof(struct sec_flc_desc),
889 RTE_CACHE_LINE_SIZE);
891 RTE_LOG(ERR, PMD, "No Memory for priv CTXT");
895 flc = &priv->flc_desc[DESC_INITFINAL].flc;
897 session->auth_key.data = rte_zmalloc(NULL, xform->auth.key.length,
898 RTE_CACHE_LINE_SIZE);
899 if (session->auth_key.data == NULL) {
900 RTE_LOG(ERR, PMD, "No Memory for auth key");
904 session->auth_key.length = xform->auth.key.length;
906 memcpy(session->auth_key.data, xform->auth.key.data,
907 xform->auth.key.length);
908 authdata.key = (uint64_t)session->auth_key.data;
909 authdata.keylen = session->auth_key.length;
910 authdata.key_enc_flags = 0;
911 authdata.key_type = RTA_DATA_IMM;
913 session->digest_length = xform->auth.digest_length;
915 switch (xform->auth.algo) {
916 case RTE_CRYPTO_AUTH_SHA1_HMAC:
917 authdata.algtype = OP_ALG_ALGSEL_SHA1;
918 authdata.algmode = OP_ALG_AAI_HMAC;
919 session->auth_alg = RTE_CRYPTO_AUTH_SHA1_HMAC;
921 case RTE_CRYPTO_AUTH_MD5_HMAC:
922 authdata.algtype = OP_ALG_ALGSEL_MD5;
923 authdata.algmode = OP_ALG_AAI_HMAC;
924 session->auth_alg = RTE_CRYPTO_AUTH_MD5_HMAC;
926 case RTE_CRYPTO_AUTH_SHA256_HMAC:
927 authdata.algtype = OP_ALG_ALGSEL_SHA256;
928 authdata.algmode = OP_ALG_AAI_HMAC;
929 session->auth_alg = RTE_CRYPTO_AUTH_SHA256_HMAC;
931 case RTE_CRYPTO_AUTH_SHA384_HMAC:
932 authdata.algtype = OP_ALG_ALGSEL_SHA384;
933 authdata.algmode = OP_ALG_AAI_HMAC;
934 session->auth_alg = RTE_CRYPTO_AUTH_SHA384_HMAC;
936 case RTE_CRYPTO_AUTH_SHA512_HMAC:
937 authdata.algtype = OP_ALG_ALGSEL_SHA512;
938 authdata.algmode = OP_ALG_AAI_HMAC;
939 session->auth_alg = RTE_CRYPTO_AUTH_SHA512_HMAC;
941 case RTE_CRYPTO_AUTH_SHA224_HMAC:
942 authdata.algtype = OP_ALG_ALGSEL_SHA224;
943 authdata.algmode = OP_ALG_AAI_HMAC;
944 session->auth_alg = RTE_CRYPTO_AUTH_SHA224_HMAC;
946 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
947 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
948 case RTE_CRYPTO_AUTH_NULL:
949 case RTE_CRYPTO_AUTH_SHA1:
950 case RTE_CRYPTO_AUTH_SHA256:
951 case RTE_CRYPTO_AUTH_SHA512:
952 case RTE_CRYPTO_AUTH_SHA224:
953 case RTE_CRYPTO_AUTH_SHA384:
954 case RTE_CRYPTO_AUTH_MD5:
955 case RTE_CRYPTO_AUTH_AES_GMAC:
956 case RTE_CRYPTO_AUTH_KASUMI_F9:
957 case RTE_CRYPTO_AUTH_AES_CMAC:
958 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
959 case RTE_CRYPTO_AUTH_ZUC_EIA3:
960 RTE_LOG(ERR, PMD, "Crypto: Unsupported auth alg %u",
964 RTE_LOG(ERR, PMD, "Crypto: Undefined Auth specified %u\n",
968 session->dir = (xform->auth.op == RTE_CRYPTO_AUTH_OP_GENERATE) ?
971 bufsize = cnstr_shdsc_hmac(priv->flc_desc[DESC_INITFINAL].desc,
972 1, 0, &authdata, !session->dir,
975 flc->word1_sdl = (uint8_t)bufsize;
976 flc->word2_rflc_31_0 = lower_32_bits(
977 (uint64_t)&(((struct dpaa2_sec_qp *)
978 dev->data->queue_pairs[0])->rx_vq));
979 flc->word3_rflc_63_32 = upper_32_bits(
980 (uint64_t)&(((struct dpaa2_sec_qp *)
981 dev->data->queue_pairs[0])->rx_vq));
982 session->ctxt = priv;
987 rte_free(session->auth_key.data);
993 dpaa2_sec_aead_init(struct rte_cryptodev *dev,
994 struct rte_crypto_sym_xform *xform,
995 dpaa2_sec_session *session)
997 struct dpaa2_sec_aead_ctxt *ctxt = &session->ext_params.aead_ctxt;
998 struct alginfo authdata, cipherdata;
999 unsigned int bufsize;
1000 struct ctxt_priv *priv;
1001 struct sec_flow_context *flc;
1002 struct rte_crypto_cipher_xform *cipher_xform;
1003 struct rte_crypto_auth_xform *auth_xform;
1006 PMD_INIT_FUNC_TRACE();
1008 if (session->ext_params.aead_ctxt.auth_cipher_text) {
1009 cipher_xform = &xform->cipher;
1010 auth_xform = &xform->next->auth;
1011 session->ctxt_type =
1012 (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ?
1013 DPAA2_SEC_CIPHER_HASH : DPAA2_SEC_HASH_CIPHER;
1015 cipher_xform = &xform->next->cipher;
1016 auth_xform = &xform->auth;
1017 session->ctxt_type =
1018 (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ?
1019 DPAA2_SEC_HASH_CIPHER : DPAA2_SEC_CIPHER_HASH;
1022 /* Set IV parameters */
1023 session->iv.offset = cipher_xform->iv.offset;
1024 session->iv.length = cipher_xform->iv.length;
1026 /* For SEC AEAD only one descriptor is required */
1027 priv = (struct ctxt_priv *)rte_zmalloc(NULL,
1028 sizeof(struct ctxt_priv) + sizeof(struct sec_flc_desc),
1029 RTE_CACHE_LINE_SIZE);
1031 RTE_LOG(ERR, PMD, "No Memory for priv CTXT");
1035 flc = &priv->flc_desc[0].flc;
1037 session->cipher_key.data = rte_zmalloc(NULL, cipher_xform->key.length,
1038 RTE_CACHE_LINE_SIZE);
1039 if (session->cipher_key.data == NULL && cipher_xform->key.length > 0) {
1040 RTE_LOG(ERR, PMD, "No Memory for cipher key");
1044 session->cipher_key.length = cipher_xform->key.length;
1045 session->auth_key.data = rte_zmalloc(NULL, auth_xform->key.length,
1046 RTE_CACHE_LINE_SIZE);
1047 if (session->auth_key.data == NULL && auth_xform->key.length > 0) {
1048 RTE_LOG(ERR, PMD, "No Memory for auth key");
1049 rte_free(session->cipher_key.data);
1053 session->auth_key.length = auth_xform->key.length;
1054 memcpy(session->cipher_key.data, cipher_xform->key.data,
1055 cipher_xform->key.length);
1056 memcpy(session->auth_key.data, auth_xform->key.data,
1057 auth_xform->key.length);
1059 ctxt->trunc_len = auth_xform->digest_length;
1060 authdata.key = (uint64_t)session->auth_key.data;
1061 authdata.keylen = session->auth_key.length;
1062 authdata.key_enc_flags = 0;
1063 authdata.key_type = RTA_DATA_IMM;
1065 session->digest_length = auth_xform->digest_length;
1067 switch (auth_xform->algo) {
1068 case RTE_CRYPTO_AUTH_SHA1_HMAC:
1069 authdata.algtype = OP_ALG_ALGSEL_SHA1;
1070 authdata.algmode = OP_ALG_AAI_HMAC;
1071 session->auth_alg = RTE_CRYPTO_AUTH_SHA1_HMAC;
1073 case RTE_CRYPTO_AUTH_MD5_HMAC:
1074 authdata.algtype = OP_ALG_ALGSEL_MD5;
1075 authdata.algmode = OP_ALG_AAI_HMAC;
1076 session->auth_alg = RTE_CRYPTO_AUTH_MD5_HMAC;
1078 case RTE_CRYPTO_AUTH_SHA224_HMAC:
1079 authdata.algtype = OP_ALG_ALGSEL_SHA224;
1080 authdata.algmode = OP_ALG_AAI_HMAC;
1081 session->auth_alg = RTE_CRYPTO_AUTH_SHA224_HMAC;
1083 case RTE_CRYPTO_AUTH_SHA256_HMAC:
1084 authdata.algtype = OP_ALG_ALGSEL_SHA256;
1085 authdata.algmode = OP_ALG_AAI_HMAC;
1086 session->auth_alg = RTE_CRYPTO_AUTH_SHA256_HMAC;
1088 case RTE_CRYPTO_AUTH_SHA384_HMAC:
1089 authdata.algtype = OP_ALG_ALGSEL_SHA384;
1090 authdata.algmode = OP_ALG_AAI_HMAC;
1091 session->auth_alg = RTE_CRYPTO_AUTH_SHA384_HMAC;
1093 case RTE_CRYPTO_AUTH_SHA512_HMAC:
1094 authdata.algtype = OP_ALG_ALGSEL_SHA512;
1095 authdata.algmode = OP_ALG_AAI_HMAC;
1096 session->auth_alg = RTE_CRYPTO_AUTH_SHA512_HMAC;
1098 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
1099 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
1100 case RTE_CRYPTO_AUTH_NULL:
1101 case RTE_CRYPTO_AUTH_SHA1:
1102 case RTE_CRYPTO_AUTH_SHA256:
1103 case RTE_CRYPTO_AUTH_SHA512:
1104 case RTE_CRYPTO_AUTH_SHA224:
1105 case RTE_CRYPTO_AUTH_SHA384:
1106 case RTE_CRYPTO_AUTH_MD5:
1107 case RTE_CRYPTO_AUTH_AES_GMAC:
1108 case RTE_CRYPTO_AUTH_KASUMI_F9:
1109 case RTE_CRYPTO_AUTH_AES_CMAC:
1110 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
1111 case RTE_CRYPTO_AUTH_ZUC_EIA3:
1112 RTE_LOG(ERR, PMD, "Crypto: Unsupported auth alg %u",
1116 RTE_LOG(ERR, PMD, "Crypto: Undefined Auth specified %u\n",
1120 cipherdata.key = (uint64_t)session->cipher_key.data;
1121 cipherdata.keylen = session->cipher_key.length;
1122 cipherdata.key_enc_flags = 0;
1123 cipherdata.key_type = RTA_DATA_IMM;
1125 switch (cipher_xform->algo) {
1126 case RTE_CRYPTO_CIPHER_AES_CBC:
1127 cipherdata.algtype = OP_ALG_ALGSEL_AES;
1128 cipherdata.algmode = OP_ALG_AAI_CBC;
1129 session->cipher_alg = RTE_CRYPTO_CIPHER_AES_CBC;
1130 ctxt->iv.length = AES_CBC_IV_LEN;
1132 case RTE_CRYPTO_CIPHER_3DES_CBC:
1133 cipherdata.algtype = OP_ALG_ALGSEL_3DES;
1134 cipherdata.algmode = OP_ALG_AAI_CBC;
1135 session->cipher_alg = RTE_CRYPTO_CIPHER_3DES_CBC;
1136 ctxt->iv.length = TDES_CBC_IV_LEN;
1138 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
1139 case RTE_CRYPTO_CIPHER_NULL:
1140 case RTE_CRYPTO_CIPHER_3DES_ECB:
1141 case RTE_CRYPTO_CIPHER_AES_ECB:
1142 case RTE_CRYPTO_CIPHER_AES_CTR:
1143 case RTE_CRYPTO_CIPHER_KASUMI_F8:
1144 RTE_LOG(ERR, PMD, "Crypto: Unsupported Cipher alg %u",
1145 cipher_xform->algo);
1148 RTE_LOG(ERR, PMD, "Crypto: Undefined Cipher specified %u\n",
1149 cipher_xform->algo);
1152 session->dir = (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) ?
1155 priv->flc_desc[0].desc[0] = cipherdata.keylen;
1156 priv->flc_desc[0].desc[1] = authdata.keylen;
1157 err = rta_inline_query(IPSEC_AUTH_VAR_AES_DEC_BASE_DESC_LEN,
1159 (unsigned int *)priv->flc_desc[0].desc,
1160 &priv->flc_desc[0].desc[2], 2);
1163 PMD_DRV_LOG(ERR, "Crypto: Incorrect key lengths");
1166 if (priv->flc_desc[0].desc[2] & 1) {
1167 cipherdata.key_type = RTA_DATA_IMM;
1169 cipherdata.key = DPAA2_VADDR_TO_IOVA(cipherdata.key);
1170 cipherdata.key_type = RTA_DATA_PTR;
1172 if (priv->flc_desc[0].desc[2] & (1 << 1)) {
1173 authdata.key_type = RTA_DATA_IMM;
1175 authdata.key = DPAA2_VADDR_TO_IOVA(authdata.key);
1176 authdata.key_type = RTA_DATA_PTR;
1178 priv->flc_desc[0].desc[0] = 0;
1179 priv->flc_desc[0].desc[1] = 0;
1180 priv->flc_desc[0].desc[2] = 0;
1182 if (session->ctxt_type == DPAA2_SEC_CIPHER_HASH) {
1183 bufsize = cnstr_shdsc_authenc(priv->flc_desc[0].desc, 1,
1184 0, &cipherdata, &authdata,
1186 ctxt->auth_only_len,
1190 RTE_LOG(ERR, PMD, "Hash before cipher not supported");
1194 flc->word1_sdl = (uint8_t)bufsize;
1195 flc->word2_rflc_31_0 = lower_32_bits(
1196 (uint64_t)&(((struct dpaa2_sec_qp *)
1197 dev->data->queue_pairs[0])->rx_vq));
1198 flc->word3_rflc_63_32 = upper_32_bits(
1199 (uint64_t)&(((struct dpaa2_sec_qp *)
1200 dev->data->queue_pairs[0])->rx_vq));
1201 session->ctxt = priv;
1206 rte_free(session->cipher_key.data);
1207 rte_free(session->auth_key.data);
1213 dpaa2_sec_session_configure(struct rte_cryptodev *dev,
1214 struct rte_crypto_sym_xform *xform, void *sess)
1216 dpaa2_sec_session *session = sess;
1218 PMD_INIT_FUNC_TRACE();
1220 if (unlikely(sess == NULL)) {
1221 RTE_LOG(ERR, PMD, "invalid session struct");
1225 /* Default IV length = 0 */
1226 session->iv.length = 0;
1229 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL) {
1230 session->ctxt_type = DPAA2_SEC_CIPHER;
1231 dpaa2_sec_cipher_init(dev, xform, session);
1233 /* Authentication Only */
1234 } else if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
1235 xform->next == NULL) {
1236 session->ctxt_type = DPAA2_SEC_AUTH;
1237 dpaa2_sec_auth_init(dev, xform, session);
1239 /* Cipher then Authenticate */
1240 } else if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
1241 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
1242 session->ext_params.aead_ctxt.auth_cipher_text = true;
1243 dpaa2_sec_aead_init(dev, xform, session);
1245 /* Authenticate then Cipher */
1246 } else if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
1247 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) {
1248 session->ext_params.aead_ctxt.auth_cipher_text = false;
1249 dpaa2_sec_aead_init(dev, xform, session);
1251 RTE_LOG(ERR, PMD, "Invalid crypto type");
1258 /** Clear the memory of session so it doesn't leave key material behind */
1260 dpaa2_sec_session_clear(struct rte_cryptodev *dev __rte_unused, void *sess)
1262 PMD_INIT_FUNC_TRACE();
1263 dpaa2_sec_session *s = (dpaa2_sec_session *)sess;
1267 rte_free(s->cipher_key.data);
1268 rte_free(s->auth_key.data);
1269 memset(sess, 0, sizeof(dpaa2_sec_session));
1274 dpaa2_sec_dev_configure(struct rte_cryptodev *dev __rte_unused,
1275 struct rte_cryptodev_config *config __rte_unused)
1277 PMD_INIT_FUNC_TRACE();
1283 dpaa2_sec_dev_start(struct rte_cryptodev *dev)
1285 struct dpaa2_sec_dev_private *priv = dev->data->dev_private;
1286 struct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw;
1287 struct dpseci_attr attr;
1288 struct dpaa2_queue *dpaa2_q;
1289 struct dpaa2_sec_qp **qp = (struct dpaa2_sec_qp **)
1290 dev->data->queue_pairs;
1291 struct dpseci_rx_queue_attr rx_attr;
1292 struct dpseci_tx_queue_attr tx_attr;
1295 PMD_INIT_FUNC_TRACE();
1297 memset(&attr, 0, sizeof(struct dpseci_attr));
1299 ret = dpseci_enable(dpseci, CMD_PRI_LOW, priv->token);
1301 PMD_INIT_LOG(ERR, "DPSECI with HW_ID = %d ENABLE FAILED\n",
1303 goto get_attr_failure;
1305 ret = dpseci_get_attributes(dpseci, CMD_PRI_LOW, priv->token, &attr);
1308 "DPSEC ATTRIBUTE READ FAILED, disabling DPSEC\n");
1309 goto get_attr_failure;
1311 for (i = 0; i < attr.num_rx_queues && qp[i]; i++) {
1312 dpaa2_q = &qp[i]->rx_vq;
1313 dpseci_get_rx_queue(dpseci, CMD_PRI_LOW, priv->token, i,
1315 dpaa2_q->fqid = rx_attr.fqid;
1316 PMD_INIT_LOG(DEBUG, "rx_fqid: %d", dpaa2_q->fqid);
1318 for (i = 0; i < attr.num_tx_queues && qp[i]; i++) {
1319 dpaa2_q = &qp[i]->tx_vq;
1320 dpseci_get_tx_queue(dpseci, CMD_PRI_LOW, priv->token, i,
1322 dpaa2_q->fqid = tx_attr.fqid;
1323 PMD_INIT_LOG(DEBUG, "tx_fqid: %d", dpaa2_q->fqid);
1328 dpseci_disable(dpseci, CMD_PRI_LOW, priv->token);
1333 dpaa2_sec_dev_stop(struct rte_cryptodev *dev)
1335 struct dpaa2_sec_dev_private *priv = dev->data->dev_private;
1336 struct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw;
1339 PMD_INIT_FUNC_TRACE();
1341 ret = dpseci_disable(dpseci, CMD_PRI_LOW, priv->token);
1343 PMD_INIT_LOG(ERR, "Failure in disabling dpseci %d device",
1348 ret = dpseci_reset(dpseci, CMD_PRI_LOW, priv->token);
1350 PMD_INIT_LOG(ERR, "SEC Device cannot be reset:Error = %0x\n",
1357 dpaa2_sec_dev_close(struct rte_cryptodev *dev)
1359 struct dpaa2_sec_dev_private *priv = dev->data->dev_private;
1360 struct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw;
1363 PMD_INIT_FUNC_TRACE();
1365 /* Function is reverse of dpaa2_sec_dev_init.
1366 * It does the following:
1367 * 1. Detach a DPSECI from attached resources i.e. buffer pools, dpbp_id
1368 * 2. Close the DPSECI device
1369 * 3. Free the allocated resources.
1372 /*Close the device at underlying layer*/
1373 ret = dpseci_close(dpseci, CMD_PRI_LOW, priv->token);
1375 PMD_INIT_LOG(ERR, "Failure closing dpseci device with"
1376 " error code %d\n", ret);
1380 /*Free the allocated memory for ethernet private data and dpseci*/
1388 dpaa2_sec_dev_infos_get(struct rte_cryptodev *dev,
1389 struct rte_cryptodev_info *info)
1391 struct dpaa2_sec_dev_private *internals = dev->data->dev_private;
1393 PMD_INIT_FUNC_TRACE();
1395 info->max_nb_queue_pairs = internals->max_nb_queue_pairs;
1396 info->feature_flags = dev->feature_flags;
1397 info->capabilities = dpaa2_sec_capabilities;
1398 info->sym.max_nb_sessions = internals->max_nb_sessions;
1399 info->dev_type = RTE_CRYPTODEV_DPAA2_SEC_PMD;
1404 void dpaa2_sec_stats_get(struct rte_cryptodev *dev,
1405 struct rte_cryptodev_stats *stats)
1407 struct dpaa2_sec_dev_private *priv = dev->data->dev_private;
1408 struct fsl_mc_io *dpseci = (struct fsl_mc_io *)priv->hw;
1409 struct dpseci_sec_counters counters = {0};
1410 struct dpaa2_sec_qp **qp = (struct dpaa2_sec_qp **)
1411 dev->data->queue_pairs;
1414 PMD_INIT_FUNC_TRACE();
1415 if (stats == NULL) {
1416 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1419 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1420 if (qp[i] == NULL) {
1421 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1425 stats->enqueued_count += qp[i]->tx_vq.tx_pkts;
1426 stats->dequeued_count += qp[i]->rx_vq.rx_pkts;
1427 stats->enqueue_err_count += qp[i]->tx_vq.err_pkts;
1428 stats->dequeue_err_count += qp[i]->rx_vq.err_pkts;
1431 ret = dpseci_get_sec_counters(dpseci, CMD_PRI_LOW, priv->token,
1434 PMD_DRV_LOG(ERR, "dpseci_get_sec_counters failed\n");
1436 PMD_DRV_LOG(INFO, "dpseci hw stats:"
1437 "\n\tNumber of Requests Dequeued = %lu"
1438 "\n\tNumber of Outbound Encrypt Requests = %lu"
1439 "\n\tNumber of Inbound Decrypt Requests = %lu"
1440 "\n\tNumber of Outbound Bytes Encrypted = %lu"
1441 "\n\tNumber of Outbound Bytes Protected = %lu"
1442 "\n\tNumber of Inbound Bytes Decrypted = %lu"
1443 "\n\tNumber of Inbound Bytes Validated = %lu",
1444 counters.dequeued_requests,
1445 counters.ob_enc_requests,
1446 counters.ib_dec_requests,
1447 counters.ob_enc_bytes,
1448 counters.ob_prot_bytes,
1449 counters.ib_dec_bytes,
1450 counters.ib_valid_bytes);
1455 void dpaa2_sec_stats_reset(struct rte_cryptodev *dev)
1458 struct dpaa2_sec_qp **qp = (struct dpaa2_sec_qp **)
1459 (dev->data->queue_pairs);
1461 PMD_INIT_FUNC_TRACE();
1463 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1464 if (qp[i] == NULL) {
1465 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1468 qp[i]->tx_vq.rx_pkts = 0;
1469 qp[i]->tx_vq.tx_pkts = 0;
1470 qp[i]->tx_vq.err_pkts = 0;
1471 qp[i]->rx_vq.rx_pkts = 0;
1472 qp[i]->rx_vq.tx_pkts = 0;
1473 qp[i]->rx_vq.err_pkts = 0;
1477 static struct rte_cryptodev_ops crypto_ops = {
1478 .dev_configure = dpaa2_sec_dev_configure,
1479 .dev_start = dpaa2_sec_dev_start,
1480 .dev_stop = dpaa2_sec_dev_stop,
1481 .dev_close = dpaa2_sec_dev_close,
1482 .dev_infos_get = dpaa2_sec_dev_infos_get,
1483 .stats_get = dpaa2_sec_stats_get,
1484 .stats_reset = dpaa2_sec_stats_reset,
1485 .queue_pair_setup = dpaa2_sec_queue_pair_setup,
1486 .queue_pair_release = dpaa2_sec_queue_pair_release,
1487 .queue_pair_start = dpaa2_sec_queue_pair_start,
1488 .queue_pair_stop = dpaa2_sec_queue_pair_stop,
1489 .queue_pair_count = dpaa2_sec_queue_pair_count,
1490 .session_get_size = dpaa2_sec_session_get_size,
1491 .session_initialize = dpaa2_sec_session_initialize,
1492 .session_configure = dpaa2_sec_session_configure,
1493 .session_clear = dpaa2_sec_session_clear,
1497 dpaa2_sec_uninit(const struct rte_cryptodev *dev)
1499 PMD_INIT_LOG(INFO, "Closing DPAA2_SEC device %s on numa socket %u\n",
1500 dev->data->name, rte_socket_id());
1506 dpaa2_sec_dev_init(struct rte_cryptodev *cryptodev)
1508 struct dpaa2_sec_dev_private *internals;
1509 struct rte_device *dev = cryptodev->device;
1510 struct rte_dpaa2_device *dpaa2_dev;
1511 struct fsl_mc_io *dpseci;
1513 struct dpseci_attr attr;
1516 PMD_INIT_FUNC_TRACE();
1517 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
1518 if (dpaa2_dev == NULL) {
1519 PMD_INIT_LOG(ERR, "dpaa2_device not found\n");
1522 hw_id = dpaa2_dev->object_id;
1524 cryptodev->dev_type = RTE_CRYPTODEV_DPAA2_SEC_PMD;
1525 cryptodev->dev_ops = &crypto_ops;
1527 cryptodev->enqueue_burst = dpaa2_sec_enqueue_burst;
1528 cryptodev->dequeue_burst = dpaa2_sec_dequeue_burst;
1529 cryptodev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
1530 RTE_CRYPTODEV_FF_HW_ACCELERATED |
1531 RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING;
1533 internals = cryptodev->data->dev_private;
1534 internals->max_nb_sessions = RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS;
1537 * For secondary processes, we don't initialise any further as primary
1538 * has already done this work. Only check we don't need a different
1541 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1542 PMD_INIT_LOG(DEBUG, "Device already init by primary process");
1545 /*Open the rte device via MC and save the handle for further use*/
1546 dpseci = (struct fsl_mc_io *)rte_calloc(NULL, 1,
1547 sizeof(struct fsl_mc_io), 0);
1550 "Error in allocating the memory for dpsec object");
1553 dpseci->regs = rte_mcp_ptr_list[0];
1555 retcode = dpseci_open(dpseci, CMD_PRI_LOW, hw_id, &token);
1557 PMD_INIT_LOG(ERR, "Cannot open the dpsec device: Error = %x",
1561 retcode = dpseci_get_attributes(dpseci, CMD_PRI_LOW, token, &attr);
1564 "Cannot get dpsec device attributed: Error = %x",
1568 sprintf(cryptodev->data->name, "dpsec-%u", hw_id);
1570 internals->max_nb_queue_pairs = attr.num_tx_queues;
1571 cryptodev->data->nb_queue_pairs = internals->max_nb_queue_pairs;
1572 internals->hw = dpseci;
1573 internals->token = token;
1575 PMD_INIT_LOG(DEBUG, "driver %s: created\n", cryptodev->data->name);
1579 PMD_INIT_LOG(ERR, "driver %s: create failed\n", cryptodev->data->name);
1581 /* dpaa2_sec_uninit(crypto_dev_name); */
1586 cryptodev_dpaa2_sec_probe(struct rte_dpaa2_driver *dpaa2_drv __rte_unused,
1587 struct rte_dpaa2_device *dpaa2_dev)
1589 struct rte_cryptodev *cryptodev;
1590 char cryptodev_name[RTE_CRYPTODEV_NAME_MAX_LEN];
1594 sprintf(cryptodev_name, "dpsec-%d", dpaa2_dev->object_id);
1596 cryptodev = rte_cryptodev_pmd_allocate(cryptodev_name, rte_socket_id());
1597 if (cryptodev == NULL)
1600 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1601 cryptodev->data->dev_private = rte_zmalloc_socket(
1602 "cryptodev private structure",
1603 sizeof(struct dpaa2_sec_dev_private),
1604 RTE_CACHE_LINE_SIZE,
1607 if (cryptodev->data->dev_private == NULL)
1608 rte_panic("Cannot allocate memzone for private "
1612 dpaa2_dev->cryptodev = cryptodev;
1613 cryptodev->device = &dpaa2_dev->device;
1615 /* init user callbacks */
1616 TAILQ_INIT(&(cryptodev->link_intr_cbs));
1618 /* Invoke PMD device initialization function */
1619 retval = dpaa2_sec_dev_init(cryptodev);
1623 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1624 rte_free(cryptodev->data->dev_private);
1626 cryptodev->attached = RTE_CRYPTODEV_DETACHED;
1632 cryptodev_dpaa2_sec_remove(struct rte_dpaa2_device *dpaa2_dev)
1634 struct rte_cryptodev *cryptodev;
1637 cryptodev = dpaa2_dev->cryptodev;
1638 if (cryptodev == NULL)
1641 ret = dpaa2_sec_uninit(cryptodev);
1645 /* free crypto device */
1646 rte_cryptodev_pmd_release_device(cryptodev);
1648 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1649 rte_free(cryptodev->data->dev_private);
1651 cryptodev->device = NULL;
1652 cryptodev->data = NULL;
1657 static struct rte_dpaa2_driver rte_dpaa2_sec_driver = {
1658 .drv_type = DPAA2_MC_DPSECI_DEVID,
1660 .name = "DPAA2 SEC PMD"
1662 .probe = cryptodev_dpaa2_sec_probe,
1663 .remove = cryptodev_dpaa2_sec_remove,
1666 RTE_PMD_REGISTER_DPAA2(dpaa2_sec_pmd, rte_dpaa2_sec_driver);