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34 #ifndef _RTE_DPAA2_SEC_PMD_PRIVATE_H_
35 #define _RTE_DPAA2_SEC_PMD_PRIVATE_H_
37 #define CRYPTODEV_NAME_DPAA2_SEC_PMD crypto_dpaa2_sec
38 /**< NXP DPAA2 - SEC PMD device name */
41 #define MAX_DESC_SIZE 64
42 /** private data structure for each DPAA2_SEC device */
43 struct dpaa2_sec_dev_private {
44 void *mc_portal; /**< MC Portal for configuring this device */
45 void *hw; /**< Hardware handle for this device.Used by NADK framework */
46 struct rte_mempool *fle_pool; /* per device memory pool for FLE */
47 int32_t hw_id; /**< An unique ID of this device instance */
48 int32_t vfio_fd; /**< File descriptor received via VFIO */
49 uint16_t token; /**< Token required by DPxxx objects */
50 unsigned int max_nb_queue_pairs;
51 /**< Max number of queue pairs supported by device */
52 unsigned int max_nb_sessions;
53 /**< Max number of sessions supported by device */
57 struct dpaa2_queue rx_vq;
58 struct dpaa2_queue tx_vq;
70 /* SEC Flow Context Descriptor */
71 struct sec_flow_context {
73 uint16_t word0_sdid; /* 11-0 SDID */
74 uint16_t word0_res; /* 31-12 reserved */
77 uint8_t word1_sdl; /* 5-0 SDL */
80 uint8_t word1_bits_15_8; /* 11-8 CRID */
84 uint8_t word1_bits23_16; /* 16 EWS */
89 uint8_t word1_bits31_24; /* 24 RSC */
93 /* word 2 RFLC[31-0] */
94 uint32_t word2_rflc_31_0;
96 /* word 3 RFLC[63-32] */
97 uint32_t word3_rflc_63_32;
100 uint16_t word4_iicid; /* 15-0 IICID */
101 uint16_t word4_oicid; /* 31-16 OICID */
104 uint32_t word5_ofqid:24; /* 23-0 OFQID */
105 uint32_t word5_31_24:8;
112 uint32_t word6_oflc_31_0;
115 uint32_t word7_oflc_63_32;
117 /* Word 8-15 storage profiles */
118 uint16_t dl; /**< DataLength(correction) */
119 uint16_t reserved; /**< reserved */
120 uint16_t dhr; /**< DataHeadRoom(correction) */
121 uint16_t mode_bits; /**< mode bits */
122 uint16_t bpv0; /**< buffer pool0 valid */
123 uint16_t bpid0; /**< Bypass Memory Translation */
124 uint16_t bpv1; /**< buffer pool1 valid */
125 uint16_t bpid1; /**< Bypass Memory Translation */
126 uint64_t word_12_15[2]; /**< word 12-15 are reserved */
129 struct sec_flc_desc {
130 struct sec_flow_context flc;
131 uint32_t desc[MAX_DESC_SIZE];
135 struct rte_mempool *fle_pool; /* per device memory pool for FLE */
136 struct sec_flc_desc flc_desc[0];
139 enum dpaa2_sec_op_type {
140 DPAA2_SEC_NONE, /*!< No Cipher operations*/
141 DPAA2_SEC_CIPHER,/*!< CIPHER operations */
142 DPAA2_SEC_AUTH, /*!< Authentication Operations */
143 DPAA2_SEC_AEAD, /*!< AEAD (AES-GCM/CCM) type operations */
144 DPAA2_SEC_CIPHER_HASH, /*!< Authenticated Encryption with
147 DPAA2_SEC_HASH_CIPHER, /*!< Encryption with Authenticated
150 DPAA2_SEC_IPSEC, /*!< IPSEC protocol operations*/
151 DPAA2_SEC_PDCP, /*!< PDCP protocol operations*/
152 DPAA2_SEC_PKC, /*!< Public Key Cryptographic Operations */
156 struct dpaa2_sec_aead_ctxt {
157 uint16_t auth_only_len; /*!< Length of data for Auth only */
158 uint8_t auth_cipher_text; /**< Authenticate/cipher ordering */
161 typedef struct dpaa2_sec_session_entry {
164 uint8_t dir; /*!< Operation Direction */
165 enum rte_crypto_cipher_algorithm cipher_alg; /*!< Cipher Algorithm*/
166 enum rte_crypto_auth_algorithm auth_alg; /*!< Authentication Algorithm*/
169 uint8_t *data; /**< pointer to key data */
170 size_t length; /**< key length in bytes */
174 uint8_t *data; /**< pointer to key data */
175 size_t length; /**< key length in bytes */
178 uint8_t *data; /**< pointer to key data */
179 size_t length; /**< key length in bytes */
184 uint16_t length; /**< IV length in bytes */
185 uint16_t offset; /**< IV offset in bytes */
187 uint16_t digest_length;
190 struct dpaa2_sec_aead_ctxt aead_ctxt;
194 static const struct rte_cryptodev_capabilities dpaa2_sec_capabilities[] = {
196 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
198 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
200 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
217 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
219 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
221 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
238 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
240 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
242 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
259 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
261 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
263 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
280 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
282 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
284 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
301 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
303 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
305 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
322 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
324 .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
326 .algo = RTE_CRYPTO_AEAD_AES_GCM,
352 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
354 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
356 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
372 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
374 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
376 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
392 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
394 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
396 .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
412 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
414 #endif /* _RTE_DPAA2_SEC_PMD_PRIVATE_H_ */