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34 #ifndef _RTE_DPAA2_SEC_PMD_PRIVATE_H_
35 #define _RTE_DPAA2_SEC_PMD_PRIVATE_H_
38 #define MAX_DESC_SIZE 64
39 /** private data structure for each DPAA2_SEC device */
40 struct dpaa2_sec_dev_private {
41 void *mc_portal; /**< MC Portal for configuring this device */
42 void *hw; /**< Hardware handle for this device.Used by NADK framework */
43 int32_t hw_id; /**< An unique ID of this device instance */
44 int32_t vfio_fd; /**< File descriptor received via VFIO */
45 uint16_t token; /**< Token required by DPxxx objects */
46 unsigned int max_nb_queue_pairs;
47 /**< Max number of queue pairs supported by device */
48 unsigned int max_nb_sessions;
49 /**< Max number of sessions supported by device */
53 struct dpaa2_queue rx_vq;
54 struct dpaa2_queue tx_vq;
66 /* SEC Flow Context Descriptor */
67 struct sec_flow_context {
69 uint16_t word0_sdid; /* 11-0 SDID */
70 uint16_t word0_res; /* 31-12 reserved */
73 uint8_t word1_sdl; /* 5-0 SDL */
76 uint8_t word1_bits_15_8; /* 11-8 CRID */
80 uint8_t word1_bits23_16; /* 16 EWS */
85 uint8_t word1_bits31_24; /* 24 RSC */
89 /* word 2 RFLC[31-0] */
90 uint32_t word2_rflc_31_0;
92 /* word 3 RFLC[63-32] */
93 uint32_t word3_rflc_63_32;
96 uint16_t word4_iicid; /* 15-0 IICID */
97 uint16_t word4_oicid; /* 31-16 OICID */
100 uint32_t word5_ofqid:24; /* 23-0 OFQID */
101 uint32_t word5_31_24:8;
108 uint32_t word6_oflc_31_0;
111 uint32_t word7_oflc_63_32;
113 /* Word 8-15 storage profiles */
114 uint16_t dl; /**< DataLength(correction) */
115 uint16_t reserved; /**< reserved */
116 uint16_t dhr; /**< DataHeadRoom(correction) */
117 uint16_t mode_bits; /**< mode bits */
118 uint16_t bpv0; /**< buffer pool0 valid */
119 uint16_t bpid0; /**< Bypass Memory Translation */
120 uint16_t bpv1; /**< buffer pool1 valid */
121 uint16_t bpid1; /**< Bypass Memory Translation */
122 uint64_t word_12_15[2]; /**< word 12-15 are reserved */
125 struct sec_flc_desc {
126 struct sec_flow_context flc;
127 uint32_t desc[MAX_DESC_SIZE];
131 struct sec_flc_desc flc_desc[0];
134 enum dpaa2_sec_op_type {
135 DPAA2_SEC_NONE, /*!< No Cipher operations*/
136 DPAA2_SEC_CIPHER,/*!< CIPHER operations */
137 DPAA2_SEC_AUTH, /*!< Authentication Operations */
138 DPAA2_SEC_CIPHER_HASH, /*!< Authenticated Encryption with
141 DPAA2_SEC_HASH_CIPHER, /*!< Encryption with Authenticated
144 DPAA2_SEC_IPSEC, /*!< IPSEC protocol operations*/
145 DPAA2_SEC_PDCP, /*!< PDCP protocol operations*/
146 DPAA2_SEC_PKC, /*!< Public Key Cryptographic Operations */
150 struct dpaa2_sec_cipher_ctxt {
154 } iv; /**< Initialisation vector parameters */
155 uint8_t *init_counter; /*!< Set initial counter for CTR mode */
158 struct dpaa2_sec_auth_ctxt {
159 uint8_t trunc_len; /*!< Length for output ICV, should
160 * be 0 if no truncation required
164 struct dpaa2_sec_aead_ctxt {
168 } iv; /**< Initialisation vector parameters */
169 uint16_t auth_only_len; /*!< Length of data for Auth only */
170 uint8_t auth_cipher_text; /**< Authenticate/cipher ordering */
171 uint8_t trunc_len; /*!< Length for output ICV, should
172 * be 0 if no truncation required
176 typedef struct dpaa2_sec_session_entry {
179 uint8_t dir; /*!< Operation Direction */
180 enum rte_crypto_cipher_algorithm cipher_alg; /*!< Cipher Algorithm*/
181 enum rte_crypto_auth_algorithm auth_alg; /*!< Authentication Algorithm*/
183 uint8_t *data; /**< pointer to key data */
184 size_t length; /**< key length in bytes */
187 uint8_t *data; /**< pointer to key data */
188 size_t length; /**< key length in bytes */
192 struct dpaa2_sec_cipher_ctxt cipher_ctxt;
193 struct dpaa2_sec_auth_ctxt auth_ctxt;
194 struct dpaa2_sec_aead_ctxt aead_ctxt;
198 static const struct rte_cryptodev_capabilities dpaa2_sec_capabilities[] = {
200 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
202 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
204 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
221 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
223 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
225 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
242 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
244 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
246 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
263 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
265 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
267 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
284 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
286 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
288 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
305 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
307 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
309 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
326 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
328 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
330 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
346 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
348 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
350 .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
366 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
368 #endif /* _RTE_DPAA2_SEC_PMD_PRIVATE_H_ */