1 /* SPDX-License-Identifier: BSD-3-Clause
10 #define CRYPTODEV_NAME_DPAA_SEC_PMD crypto_dpaa_sec
11 /**< NXP DPAA - SEC PMD device name */
13 #define NUM_POOL_CHANNELS 4
14 #define DPAA_SEC_BURST 7
15 #define DPAA_SEC_ALG_UNSUPPORT (-1)
16 #define TDES_CBC_IV_LEN 8
17 #define AES_CBC_IV_LEN 16
18 #define AES_CTR_IV_LEN 16
19 #define AES_GCM_IV_LEN 12
21 /* Minimum job descriptor consists of a oneword job descriptor HEADER and
22 * a pointer to the shared descriptor.
24 #define MIN_JOB_DESC_SIZE (CAAM_CMD_SZ + CAAM_PTR_SZ)
25 /* CTX_POOL_NUM_BUFS is set as per the ipsec-secgw application */
26 #define CTX_POOL_NUM_BUFS 32000
27 #define CTX_POOL_BUF_SIZE sizeof(struct dpaa_sec_op_ctx)
28 #define CTX_POOL_CACHE_SIZE 512
29 #define RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS 2048
34 enum dpaa_sec_op_type {
35 DPAA_SEC_NONE, /*!< No Cipher operations*/
36 DPAA_SEC_CIPHER,/*!< CIPHER operations */
37 DPAA_SEC_AUTH, /*!< Authentication Operations */
38 DPAA_SEC_AEAD, /*!< Authenticated Encryption with associated data */
39 DPAA_SEC_IPSEC, /*!< IPSEC protocol operations*/
40 DPAA_SEC_PDCP, /*!< PDCP protocol operations*/
41 DPAA_SEC_PKC, /*!< Public Key Cryptographic Operations */
46 #define DPAA_SEC_MAX_DESC_SIZE 64
47 /* code or cmd block to caam */
53 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
55 unsigned int rsvd47_39:9;
59 unsigned int rsvd47_39:9;
68 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
69 unsigned int rsvd31_30:2;
72 unsigned int offset:2;
74 unsigned int add_buf:1;
76 uint16_t pool_buffer_size;
78 uint16_t pool_buffer_size;
80 unsigned int add_buf:1;
82 unsigned int offset:2;
85 unsigned int rsvd31_30:2;
91 uint32_t sh_desc[DPAA_SEC_MAX_DESC_SIZE];
94 typedef struct dpaa_sec_session_entry {
95 uint8_t dir; /*!< Operation Direction */
96 enum rte_crypto_cipher_algorithm cipher_alg; /*!< Cipher Algorithm*/
97 enum rte_crypto_auth_algorithm auth_alg; /*!< Authentication Algorithm*/
98 enum rte_crypto_aead_algorithm aead_alg; /*!< AEAD Algorithm*/
99 enum rte_security_session_protocol proto_alg; /*!< Security Algorithm*/
102 uint8_t *data; /**< pointer to key data */
103 size_t length; /**< key length in bytes */
107 uint8_t *data; /**< pointer to key data */
108 size_t length; /**< key length in bytes */
111 uint8_t *data; /**< pointer to key data */
112 size_t length; /**< key length in bytes */
119 } iv; /**< Initialisation vector parameters */
120 uint16_t auth_only_len; /*!< Length of data for Auth only */
121 uint32_t digest_length;
122 struct ipsec_encap_pdb encap_pdb;
124 struct ipsec_decap_pdb decap_pdb;
125 struct dpaa_sec_qp *qp;
127 struct sec_cdb cdb; /**< cmd block associated with qp */
128 struct rte_mempool *ctx_pool; /* session mempool for dpaa_sec_op_ctx */
132 struct dpaa_sec_dev_private *internals;
140 #define RTE_DPAA_MAX_NB_SEC_QPS 2
141 #define RTE_DPAA_MAX_RX_QUEUE RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS
142 #define DPAA_MAX_DEQUEUE_NUM_FRAMES 63
144 /* internal sec queue interface */
145 struct dpaa_sec_dev_private {
147 struct rte_mempool *ctx_pool; /* per dev mempool for dpaa_sec_op_ctx */
148 struct dpaa_sec_qp qps[RTE_DPAA_MAX_NB_SEC_QPS]; /* i/o queue for sec */
149 struct qman_fq inq[RTE_DPAA_MAX_RX_QUEUE];
150 unsigned char inq_attach[RTE_DPAA_MAX_RX_QUEUE];
151 unsigned int max_nb_queue_pairs;
152 unsigned int max_nb_sessions;
156 #define MAX_SG_ENTRIES 16
157 #define SG_CACHELINE_0 0
158 #define SG_CACHELINE_1 4
159 #define SG_CACHELINE_2 8
160 #define SG_CACHELINE_3 12
161 struct dpaa_sec_job {
162 /* sg[0] output, sg[1] input, others are possible sub frames */
163 struct qm_sg_entry sg[MAX_SG_ENTRIES];
166 #define DPAA_MAX_NB_MAX_DIGEST 32
167 struct dpaa_sec_op_ctx {
168 struct dpaa_sec_job job;
169 struct rte_crypto_op *op;
170 struct rte_mempool *ctx_pool; /* mempool pointer for dpaa_sec_op_ctx */
173 uint8_t digest[DPAA_MAX_NB_MAX_DIGEST];
176 static const struct rte_cryptodev_capabilities dpaa_sec_capabilities[] = {
178 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
180 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
182 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
199 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
201 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
203 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
220 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
222 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
224 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
241 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
243 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
245 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
262 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
264 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
266 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
283 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
285 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
287 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
304 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
306 .xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,
308 .algo = RTE_CRYPTO_AEAD_AES_GCM,
334 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
336 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
338 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
354 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
356 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
358 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
374 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
376 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
378 .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
394 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
397 static const struct rte_security_capability dpaa_sec_security_cap[] = {
398 { /* IPsec Lookaside Protocol offload ESP Transport Egress */
399 .action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL,
400 .protocol = RTE_SECURITY_PROTOCOL_IPSEC,
402 .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
403 .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,
404 .direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS,
407 .crypto_capabilities = dpaa_sec_capabilities
409 { /* IPsec Lookaside Protocol offload ESP Tunnel Ingress */
410 .action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL,
411 .protocol = RTE_SECURITY_PROTOCOL_IPSEC,
413 .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
414 .mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,
415 .direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS,
418 .crypto_capabilities = dpaa_sec_capabilities
421 .action = RTE_SECURITY_ACTION_TYPE_NONE
428 * @param buffer calculate chksum for buffer
429 * @param len buffer length
431 * @return checksum value in host cpu order
433 static inline uint16_t
434 calc_chksum(void *buffer, int len)
436 uint16_t *buf = (uint16_t *)buffer;
440 for (sum = 0; len > 1; len -= 2)
444 sum += *(unsigned char *)buf;
446 sum = (sum >> 16) + (sum & 0xFFFF);
453 #endif /* _DPAA_SEC_H_ */