1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2021 NVIDIA Corporation & Affiliates
5 #include <rte_malloc.h>
6 #include <rte_mempool.h>
9 #include <rte_bus_pci.h>
10 #include <rte_memory.h>
12 #include <mlx5_glue.h>
13 #include <mlx5_common.h>
14 #include <mlx5_devx_cmds.h>
15 #include <mlx5_common_os.h>
17 #include "mlx5_crypto_utils.h"
18 #include "mlx5_crypto.h"
20 #define MLX5_CRYPTO_DRIVER_NAME crypto_mlx5
21 #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5
22 #define MLX5_CRYPTO_MAX_QPS 1024
23 #define MLX5_CRYPTO_MAX_SEGS 56
25 #define MLX5_CRYPTO_FEATURE_FLAGS \
26 (RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | \
27 RTE_CRYPTODEV_FF_IN_PLACE_SGL | RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | \
28 RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | \
29 RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT | \
30 RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT | \
31 RTE_CRYPTODEV_FF_CIPHER_WRAPPED_KEY | \
32 RTE_CRYPTODEV_FF_CIPHER_MULTIPLE_DATA_UNITS)
34 TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list =
35 TAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list);
36 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
38 int mlx5_crypto_logtype;
40 uint8_t mlx5_crypto_driver_id;
42 const struct rte_cryptodev_capabilities mlx5_crypto_caps[] = {
44 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
46 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
48 .algo = RTE_CRYPTO_CIPHER_AES_XTS,
61 RTE_CRYPTO_CIPHER_DATA_UNIT_LEN_512_BYTES |
62 RTE_CRYPTO_CIPHER_DATA_UNIT_LEN_4096_BYTES,
68 static const char mlx5_crypto_drv_name[] = RTE_STR(MLX5_CRYPTO_DRIVER_NAME);
70 static const struct rte_driver mlx5_drv = {
71 .name = mlx5_crypto_drv_name,
72 .alias = mlx5_crypto_drv_name
75 static struct cryptodev_driver mlx5_cryptodev_driver;
77 struct mlx5_crypto_session {
78 uint32_t bs_bpt_eo_es;
79 /**< bsf_size, bsf_p_type, encryption_order and encryption standard,
80 * saved in big endian format.
83 /**< crypto_block_size_pointer and reserved 24 bits saved in big
86 uint32_t iv_offset:16;
87 /**< Starting point for Initialisation Vector. */
88 struct mlx5_crypto_dek *dek; /**< Pointer to dek struct. */
89 uint32_t dek_id; /**< DEK ID */
93 mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev,
94 struct rte_cryptodev_info *dev_info)
97 if (dev_info != NULL) {
98 dev_info->driver_id = mlx5_crypto_driver_id;
99 dev_info->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS;
100 dev_info->capabilities = mlx5_crypto_caps;
101 dev_info->max_nb_queue_pairs = MLX5_CRYPTO_MAX_QPS;
102 dev_info->min_mbuf_headroom_req = 0;
103 dev_info->min_mbuf_tailroom_req = 0;
104 dev_info->sym.max_nb_sessions = 0;
106 * If 0, the device does not have any limitation in number of
107 * sessions that can be used.
113 mlx5_crypto_dev_configure(struct rte_cryptodev *dev,
114 struct rte_cryptodev_config *config)
116 struct mlx5_crypto_priv *priv = dev->data->dev_private;
118 if (config == NULL) {
119 DRV_LOG(ERR, "Invalid crypto dev configure parameters.");
122 if ((config->ff_disable & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) != 0) {
124 "Disabled symmetric crypto feature is not supported.");
127 if (mlx5_crypto_dek_setup(priv) != 0) {
128 DRV_LOG(ERR, "Dek hash list creation has failed.");
131 priv->dev_config = *config;
132 DRV_LOG(DEBUG, "Device %u was configured.", dev->driver_id);
137 mlx5_crypto_dev_stop(struct rte_cryptodev *dev)
143 mlx5_crypto_dev_start(struct rte_cryptodev *dev)
145 struct mlx5_crypto_priv *priv = dev->data->dev_private;
147 return mlx5_dev_mempool_subscribe(priv->cdev);
151 mlx5_crypto_dev_close(struct rte_cryptodev *dev)
153 struct mlx5_crypto_priv *priv = dev->data->dev_private;
155 mlx5_crypto_dek_unset(priv);
156 DRV_LOG(DEBUG, "Device %u was closed.", dev->driver_id);
161 mlx5_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
163 return sizeof(struct mlx5_crypto_session);
167 mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev,
168 struct rte_crypto_sym_xform *xform,
169 struct rte_cryptodev_sym_session *session,
170 struct rte_mempool *mp)
172 struct mlx5_crypto_priv *priv = dev->data->dev_private;
173 struct mlx5_crypto_session *sess_private_data;
174 struct rte_crypto_cipher_xform *cipher;
175 uint8_t encryption_order;
178 if (unlikely(xform->next != NULL)) {
179 DRV_LOG(ERR, "Xform next is not supported.");
182 if (unlikely((xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER) ||
183 (xform->cipher.algo != RTE_CRYPTO_CIPHER_AES_XTS))) {
184 DRV_LOG(ERR, "Only AES-XTS algorithm is supported.");
187 ret = rte_mempool_get(mp, (void *)&sess_private_data);
190 "Failed to get session %p private data from mempool.",
194 cipher = &xform->cipher;
195 sess_private_data->dek = mlx5_crypto_dek_prepare(priv, cipher);
196 if (sess_private_data->dek == NULL) {
197 rte_mempool_put(mp, sess_private_data);
198 DRV_LOG(ERR, "Failed to prepare dek.");
201 if (cipher->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
202 encryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY;
204 encryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE;
205 sess_private_data->bs_bpt_eo_es = rte_cpu_to_be_32
206 (MLX5_BSF_SIZE_64B << MLX5_BSF_SIZE_OFFSET |
207 MLX5_BSF_P_TYPE_CRYPTO << MLX5_BSF_P_TYPE_OFFSET |
208 encryption_order << MLX5_ENCRYPTION_ORDER_OFFSET |
209 MLX5_ENCRYPTION_STANDARD_AES_XTS);
210 switch (xform->cipher.dataunit_len) {
212 sess_private_data->bsp_res = 0;
215 sess_private_data->bsp_res = rte_cpu_to_be_32
216 ((uint32_t)MLX5_BLOCK_SIZE_512B <<
217 MLX5_BLOCK_SIZE_OFFSET);
220 sess_private_data->bsp_res = rte_cpu_to_be_32
221 ((uint32_t)MLX5_BLOCK_SIZE_4096B <<
222 MLX5_BLOCK_SIZE_OFFSET);
225 DRV_LOG(ERR, "Cipher data unit length is not supported.");
228 sess_private_data->iv_offset = cipher->iv.offset;
229 sess_private_data->dek_id =
230 rte_cpu_to_be_32(sess_private_data->dek->obj->id &
232 set_sym_session_private_data(session, dev->driver_id,
234 DRV_LOG(DEBUG, "Session %p was configured.", sess_private_data);
239 mlx5_crypto_sym_session_clear(struct rte_cryptodev *dev,
240 struct rte_cryptodev_sym_session *sess)
242 struct mlx5_crypto_priv *priv = dev->data->dev_private;
243 struct mlx5_crypto_session *spriv = get_sym_session_private_data(sess,
246 if (unlikely(spriv == NULL)) {
247 DRV_LOG(ERR, "Failed to get session %p private data.", spriv);
250 mlx5_crypto_dek_destroy(priv, spriv->dek);
251 set_sym_session_private_data(sess, dev->driver_id, NULL);
252 rte_mempool_put(rte_mempool_from_obj(spriv), spriv);
253 DRV_LOG(DEBUG, "Session %p was cleared.", spriv);
257 mlx5_crypto_indirect_mkeys_release(struct mlx5_crypto_qp *qp, uint16_t n)
261 for (i = 0; i < n; i++)
263 claim_zero(mlx5_devx_cmd_destroy(qp->mkey[i]));
267 mlx5_crypto_qp_release(struct mlx5_crypto_qp *qp)
271 mlx5_devx_qp_destroy(&qp->qp_obj);
272 mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
273 mlx5_devx_cq_destroy(&qp->cq_obj);
278 mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
280 struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];
282 mlx5_crypto_indirect_mkeys_release(qp, qp->entries_n);
283 mlx5_crypto_qp_release(qp);
284 dev->data->queue_pairs[qp_id] = NULL;
288 static __rte_noinline uint32_t
289 mlx5_crypto_get_block_size(struct rte_crypto_op *op)
291 uint32_t bl = op->sym->cipher.data.length;
295 return RTE_BE32(MLX5_BLOCK_SIZE_1MB << MLX5_BLOCK_SIZE_OFFSET);
297 return RTE_BE32(MLX5_BLOCK_SIZE_4096B <<
298 MLX5_BLOCK_SIZE_OFFSET);
300 return RTE_BE32(MLX5_BLOCK_SIZE_512B << MLX5_BLOCK_SIZE_OFFSET);
302 DRV_LOG(ERR, "Unknown block size: %u.", bl);
307 static __rte_always_inline uint32_t
308 mlx5_crypto_klm_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp,
309 struct rte_mbuf *mbuf, struct mlx5_wqe_dseg *klm,
310 uint32_t offset, uint32_t *remain)
312 uint32_t data_len = (rte_pktmbuf_data_len(mbuf) - offset);
313 uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
315 if (data_len > *remain)
318 klm->bcount = rte_cpu_to_be_32(data_len);
319 klm->pbuf = rte_cpu_to_be_64(addr);
320 klm->lkey = mlx5_mr_mb2mr(priv->cdev, 0, &qp->mr_ctrl, mbuf);
325 static __rte_always_inline uint32_t
326 mlx5_crypto_klms_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp,
327 struct rte_crypto_op *op, struct rte_mbuf *mbuf,
328 struct mlx5_wqe_dseg *klm)
330 uint32_t remain_len = op->sym->cipher.data.length;
331 uint32_t nb_segs = mbuf->nb_segs;
334 /* First mbuf needs to take the cipher offset. */
335 if (unlikely(mlx5_crypto_klm_set(priv, qp, mbuf, klm,
336 op->sym->cipher.data.offset, &remain_len) == UINT32_MAX)) {
337 op->status = RTE_CRYPTO_OP_STATUS_ERROR;
343 if (unlikely(mbuf == NULL || nb_segs == 0)) {
344 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
347 if (unlikely(mlx5_crypto_klm_set(priv, qp, mbuf, ++klm, 0,
348 &remain_len) == UINT32_MAX)) {
349 op->status = RTE_CRYPTO_OP_STATUS_ERROR;
357 static __rte_always_inline int
358 mlx5_crypto_wqe_set(struct mlx5_crypto_priv *priv,
359 struct mlx5_crypto_qp *qp,
360 struct rte_crypto_op *op,
361 struct mlx5_umr_wqe *umr)
363 struct mlx5_crypto_session *sess = get_sym_session_private_data
364 (op->sym->session, mlx5_crypto_driver_id);
365 struct mlx5_wqe_cseg *cseg = &umr->ctr;
366 struct mlx5_wqe_mkey_cseg *mkc = &umr->mkc;
367 struct mlx5_wqe_dseg *klms = &umr->kseg[0];
368 struct mlx5_wqe_umr_bsf_seg *bsf = ((struct mlx5_wqe_umr_bsf_seg *)
369 RTE_PTR_ADD(umr, priv->umr_wqe_size)) - 1;
371 bool ipl = op->sym->m_dst == NULL || op->sym->m_dst == op->sym->m_src;
373 uint32_t klm_n = mlx5_crypto_klms_set(priv, qp, op,
374 ipl ? op->sym->m_src : op->sym->m_dst, klms);
376 if (unlikely(klm_n == 0))
378 bsf->bs_bpt_eo_es = sess->bs_bpt_eo_es;
379 if (unlikely(!sess->bsp_res)) {
380 bsf->bsp_res = mlx5_crypto_get_block_size(op);
381 if (unlikely(bsf->bsp_res == UINT32_MAX)) {
382 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
386 bsf->bsp_res = sess->bsp_res;
388 bsf->raw_data_size = rte_cpu_to_be_32(op->sym->cipher.data.length);
389 memcpy(bsf->xts_initial_tweak,
390 rte_crypto_op_ctod_offset(op, uint8_t *, sess->iv_offset), 16);
391 bsf->res_dp = sess->dek_id;
392 mkc->len = rte_cpu_to_be_64(op->sym->cipher.data.length);
393 cseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) | MLX5_OPCODE_UMR);
394 qp->db_pi += priv->umr_wqe_stride;
395 /* Set RDMA_WRITE WQE. */
396 cseg = RTE_PTR_ADD(cseg, priv->umr_wqe_size);
397 klms = RTE_PTR_ADD(cseg, sizeof(struct mlx5_rdma_write_wqe));
399 klm_n = mlx5_crypto_klms_set(priv, qp, op, op->sym->m_src,
401 if (unlikely(klm_n == 0))
404 memcpy(klms, &umr->kseg[0], sizeof(*klms) * klm_n);
407 cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) | ds);
408 cseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) |
409 MLX5_OPCODE_RDMA_WRITE);
410 ds = RTE_ALIGN(ds, 4);
411 qp->db_pi += ds >> 2;
412 /* Set NOP WQE if needed. */
413 if (priv->max_rdmar_ds > ds) {
415 ds = priv->max_rdmar_ds - ds;
416 cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) | ds);
417 cseg->opcode = rte_cpu_to_be_32((qp->db_pi << 8) |
419 qp->db_pi += ds >> 2; /* Here, DS is 4 aligned for sure. */
421 qp->wqe = (uint8_t *)cseg;
425 static __rte_always_inline void
426 mlx5_crypto_uar_write(uint64_t val, struct mlx5_crypto_priv *priv)
429 *priv->uar_addr = val;
430 #else /* !RTE_ARCH_64 */
431 rte_spinlock_lock(&priv->uar32_sl);
432 *(volatile uint32_t *)priv->uar_addr = val;
434 *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32;
435 rte_spinlock_unlock(&priv->uar32_sl);
440 mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
443 struct mlx5_crypto_qp *qp = queue_pair;
444 struct mlx5_crypto_priv *priv = qp->priv;
445 struct mlx5_umr_wqe *umr;
446 struct rte_crypto_op *op;
447 uint16_t mask = qp->entries_n - 1;
448 uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
455 if (unlikely(remain == 0))
460 umr = RTE_PTR_ADD(qp->qp_obj.umem_buf,
461 priv->wqe_set_size * idx);
462 if (unlikely(mlx5_crypto_wqe_set(priv, qp, op, umr) == 0)) {
463 qp->stats.enqueue_err_count++;
464 if (remain != nb_ops) {
465 qp->stats.enqueued_count -= remain;
473 qp->stats.enqueued_count += nb_ops;
475 qp->qp_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->db_pi);
477 mlx5_crypto_uar_write(*(volatile uint64_t *)qp->wqe, qp->priv);
482 static __rte_noinline void
483 mlx5_crypto_cqe_err_handle(struct mlx5_crypto_qp *qp, struct rte_crypto_op *op)
485 const uint32_t idx = qp->ci & (qp->entries_n - 1);
486 volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
487 &qp->cq_obj.cqes[idx];
489 op->status = RTE_CRYPTO_OP_STATUS_ERROR;
490 qp->stats.dequeue_err_count++;
491 DRV_LOG(ERR, "CQE ERR:%x.\n", rte_be_to_cpu_32(cqe->syndrome));
495 mlx5_crypto_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops,
498 struct mlx5_crypto_qp *qp = queue_pair;
499 volatile struct mlx5_cqe *restrict cqe;
500 struct rte_crypto_op *restrict op;
501 const unsigned int cq_size = qp->entries_n;
502 const unsigned int mask = cq_size - 1;
504 uint32_t next_idx = qp->ci & mask;
505 const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
509 if (unlikely(max == 0))
513 next_idx = (qp->ci + 1) & mask;
515 cqe = &qp->cq_obj.cqes[idx];
516 ret = check_cqe(cqe, cq_size, qp->ci);
518 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
519 if (unlikely(ret != MLX5_CQE_STATUS_HW_OWN))
520 mlx5_crypto_cqe_err_handle(qp, op);
523 op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
527 if (likely(i != 0)) {
529 qp->cq_obj.db_rec[0] = rte_cpu_to_be_32(qp->ci);
530 qp->stats.dequeued_count += i;
536 mlx5_crypto_qp_init(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp)
540 for (i = 0 ; i < qp->entries_n; i++) {
541 struct mlx5_wqe_cseg *cseg = RTE_PTR_ADD(qp->qp_obj.umem_buf,
542 i * priv->wqe_set_size);
543 struct mlx5_wqe_umr_cseg *ucseg = (struct mlx5_wqe_umr_cseg *)
545 struct mlx5_wqe_umr_bsf_seg *bsf =
546 (struct mlx5_wqe_umr_bsf_seg *)(RTE_PTR_ADD(cseg,
547 priv->umr_wqe_size)) - 1;
548 struct mlx5_wqe_rseg *rseg;
551 cseg->sq_ds = rte_cpu_to_be_32((qp->qp_obj.qp->id << 8) |
552 (priv->umr_wqe_size / MLX5_WSEG_SIZE));
553 cseg->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
554 MLX5_COMP_MODE_OFFSET);
555 cseg->misc = rte_cpu_to_be_32(qp->mkey[i]->id);
556 ucseg->if_cf_toe_cq_res = RTE_BE32(1u << MLX5_UMRC_IF_OFFSET);
557 ucseg->mkey_mask = RTE_BE64(1u << 0); /* Mkey length bit. */
558 ucseg->ko_to_bs = rte_cpu_to_be_32
559 ((RTE_ALIGN(priv->max_segs_num, 4u) <<
560 MLX5_UMRC_KO_OFFSET) | (4 << MLX5_UMRC_TO_BS_OFFSET));
561 bsf->keytag = priv->keytag;
562 /* Init RDMA WRITE WQE. */
563 cseg = RTE_PTR_ADD(cseg, priv->umr_wqe_size);
564 cseg->flags = RTE_BE32((MLX5_COMP_ALWAYS <<
565 MLX5_COMP_MODE_OFFSET) |
566 MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE);
567 rseg = (struct mlx5_wqe_rseg *)(cseg + 1);
568 rseg->rkey = rte_cpu_to_be_32(qp->mkey[i]->id);
573 mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv,
574 struct mlx5_crypto_qp *qp)
576 struct mlx5_umr_wqe *umr;
578 struct mlx5_devx_mkey_attr attr = {
579 .pd = priv->cdev->pdn,
583 .klm_num = RTE_ALIGN(priv->max_segs_num, 4),
586 for (umr = (struct mlx5_umr_wqe *)qp->qp_obj.umem_buf, i = 0;
587 i < qp->entries_n; i++, umr = RTE_PTR_ADD(umr, priv->wqe_set_size)) {
588 attr.klm_array = (struct mlx5_klm *)&umr->kseg[0];
589 qp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->cdev->ctx, &attr);
595 DRV_LOG(ERR, "Failed to allocate indirect mkey.");
596 mlx5_crypto_indirect_mkeys_release(qp, i);
601 mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
602 const struct rte_cryptodev_qp_conf *qp_conf,
605 struct mlx5_crypto_priv *priv = dev->data->dev_private;
606 struct mlx5_devx_qp_attr attr = {0};
607 struct mlx5_crypto_qp *qp;
608 uint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors);
610 uint32_t alloc_size = sizeof(*qp);
611 struct mlx5_devx_cq_attr cq_attr = {
612 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
615 if (dev->data->queue_pairs[qp_id] != NULL)
616 mlx5_crypto_queue_pair_release(dev, qp_id);
617 alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
618 alloc_size += (sizeof(struct rte_crypto_op *) +
619 sizeof(struct mlx5_devx_obj *)) *
620 RTE_BIT32(log_nb_desc);
621 qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
624 DRV_LOG(ERR, "Failed to allocate QP memory.");
628 if (mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq_obj, log_nb_desc,
629 &cq_attr, socket_id) != 0) {
630 DRV_LOG(ERR, "Failed to create CQ.");
633 attr.pd = priv->cdev->pdn;
634 attr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);
635 attr.cqn = qp->cq_obj.cq->id;
637 attr.sq_size = RTE_BIT32(log_nb_desc);
639 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
640 ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp_obj, log_nb_desc,
643 DRV_LOG(ERR, "Failed to create QP.");
646 if (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->cdev->mr_scache.dev_gen,
647 priv->dev_config.socket_id) != 0) {
648 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
654 * In Order to configure self loopback, when calling devx qp2rts the
655 * remote QP id that is used is the id of the same QP.
657 if (mlx5_devx_qp2rts(&qp->qp_obj, qp->qp_obj.qp->id))
659 qp->mkey = (struct mlx5_devx_obj **)RTE_ALIGN((uintptr_t)(qp + 1),
660 RTE_CACHE_LINE_SIZE);
661 qp->ops = (struct rte_crypto_op **)(qp->mkey + RTE_BIT32(log_nb_desc));
662 qp->entries_n = 1 << log_nb_desc;
663 if (mlx5_crypto_indirect_mkeys_prepare(priv, qp)) {
664 DRV_LOG(ERR, "Cannot allocate indirect memory regions.");
668 mlx5_crypto_qp_init(priv, qp);
670 dev->data->queue_pairs[qp_id] = qp;
673 mlx5_crypto_qp_release(qp);
678 mlx5_crypto_stats_get(struct rte_cryptodev *dev,
679 struct rte_cryptodev_stats *stats)
683 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
684 struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];
686 stats->enqueued_count += qp->stats.enqueued_count;
687 stats->dequeued_count += qp->stats.dequeued_count;
688 stats->enqueue_err_count += qp->stats.enqueue_err_count;
689 stats->dequeue_err_count += qp->stats.dequeue_err_count;
694 mlx5_crypto_stats_reset(struct rte_cryptodev *dev)
698 for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
699 struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];
701 memset(&qp->stats, 0, sizeof(qp->stats));
705 static struct rte_cryptodev_ops mlx5_crypto_ops = {
706 .dev_configure = mlx5_crypto_dev_configure,
707 .dev_start = mlx5_crypto_dev_start,
708 .dev_stop = mlx5_crypto_dev_stop,
709 .dev_close = mlx5_crypto_dev_close,
710 .dev_infos_get = mlx5_crypto_dev_infos_get,
711 .stats_get = mlx5_crypto_stats_get,
712 .stats_reset = mlx5_crypto_stats_reset,
713 .queue_pair_setup = mlx5_crypto_queue_pair_setup,
714 .queue_pair_release = mlx5_crypto_queue_pair_release,
715 .sym_session_get_size = mlx5_crypto_sym_session_get_size,
716 .sym_session_configure = mlx5_crypto_sym_session_configure,
717 .sym_session_clear = mlx5_crypto_sym_session_clear,
718 .sym_get_raw_dp_ctx_size = NULL,
719 .sym_configure_raw_dp_ctx = NULL,
723 mlx5_crypto_uar_release(struct mlx5_crypto_priv *priv)
725 if (priv->uar != NULL) {
726 mlx5_glue->devx_free_uar(priv->uar);
732 mlx5_crypto_uar_prepare(struct mlx5_crypto_priv *priv)
734 priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);
736 priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
737 if (priv->uar == NULL || priv->uar_addr == NULL) {
739 DRV_LOG(ERR, "Failed to allocate UAR.");
747 mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque)
749 struct mlx5_crypto_devarg_params *devarg_prms = opaque;
750 struct mlx5_devx_crypto_login_attr *attr = &devarg_prms->login_attr;
756 if (strcmp(key, "class") == 0)
758 if (strcmp(key, "wcs_file") == 0) {
759 file = fopen(val, "rb");
764 for (i = 0 ; i < MLX5_CRYPTO_CREDENTIAL_SIZE ; i++) {
765 ret = fscanf(file, "%02hhX", &attr->credential[i]);
769 "Failed to read credential from file.");
775 devarg_prms->login_devarg = true;
779 tmp = strtoul(val, NULL, 0);
781 DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer.", key, val);
784 if (strcmp(key, "max_segs_num") == 0) {
785 if (!tmp || tmp > MLX5_CRYPTO_MAX_SEGS) {
786 DRV_LOG(WARNING, "Invalid max_segs_num: %d, should"
788 (uint32_t)tmp, MLX5_CRYPTO_MAX_SEGS);
792 devarg_prms->max_segs_num = (uint32_t)tmp;
793 } else if (strcmp(key, "import_kek_id") == 0) {
794 attr->session_import_kek_ptr = (uint32_t)tmp;
795 } else if (strcmp(key, "credential_id") == 0) {
796 attr->credential_pointer = (uint32_t)tmp;
797 } else if (strcmp(key, "keytag") == 0) {
798 devarg_prms->keytag = tmp;
800 DRV_LOG(WARNING, "Invalid key %s.", key);
806 mlx5_crypto_parse_devargs(struct rte_devargs *devargs,
807 struct mlx5_crypto_devarg_params *devarg_prms)
809 struct mlx5_devx_crypto_login_attr *attr = &devarg_prms->login_attr;
810 struct rte_kvargs *kvlist;
812 /* Default values. */
813 attr->credential_pointer = 0;
814 attr->session_import_kek_ptr = 0;
815 devarg_prms->keytag = 0;
816 devarg_prms->max_segs_num = 8;
817 if (devargs == NULL) {
819 "No login devargs in order to enable crypto operations in the device.");
823 kvlist = rte_kvargs_parse(devargs->args, NULL);
824 if (kvlist == NULL) {
825 DRV_LOG(ERR, "Failed to parse devargs.");
829 if (rte_kvargs_process(kvlist, NULL, mlx5_crypto_args_check_handler,
831 DRV_LOG(ERR, "Devargs handler function Failed.");
832 rte_kvargs_free(kvlist);
836 rte_kvargs_free(kvlist);
837 if (devarg_prms->login_devarg == false) {
839 "No login credential devarg in order to enable crypto operations "
848 mlx5_crypto_dev_probe(struct mlx5_common_device *cdev)
850 struct rte_cryptodev *crypto_dev;
851 struct mlx5_devx_obj *login;
852 struct mlx5_crypto_priv *priv;
853 struct mlx5_crypto_devarg_params devarg_prms = { 0 };
854 struct rte_cryptodev_pmd_init_params init_params = {
856 .private_data_size = sizeof(struct mlx5_crypto_priv),
857 .socket_id = cdev->dev->numa_node,
858 .max_nb_queue_pairs =
859 RTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS,
861 const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);
862 uint16_t rdmw_wqe_size;
865 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
866 DRV_LOG(ERR, "Non-primary process type is not supported.");
870 if (!cdev->config.hca_attr.crypto || !cdev->config.hca_attr.aes_xts) {
871 DRV_LOG(ERR, "Not enough capabilities to support crypto "
872 "operations, maybe old FW/OFED version?");
876 ret = mlx5_crypto_parse_devargs(cdev->dev->devargs, &devarg_prms);
878 DRV_LOG(ERR, "Failed to parse devargs.");
881 login = mlx5_devx_cmd_create_crypto_login_obj(cdev->ctx,
882 &devarg_prms.login_attr);
884 DRV_LOG(ERR, "Failed to configure login.");
887 crypto_dev = rte_cryptodev_pmd_create(ibdev_name, cdev->dev,
889 if (crypto_dev == NULL) {
890 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name);
894 "Crypto device %s was created successfully.", ibdev_name);
895 crypto_dev->dev_ops = &mlx5_crypto_ops;
896 crypto_dev->dequeue_burst = mlx5_crypto_dequeue_burst;
897 crypto_dev->enqueue_burst = mlx5_crypto_enqueue_burst;
898 crypto_dev->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS;
899 crypto_dev->driver_id = mlx5_crypto_driver_id;
900 priv = crypto_dev->data->dev_private;
902 priv->login_obj = login;
903 priv->crypto_dev = crypto_dev;
904 if (mlx5_crypto_uar_prepare(priv) != 0) {
905 rte_cryptodev_pmd_destroy(priv->crypto_dev);
908 priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag);
909 priv->max_segs_num = devarg_prms.max_segs_num;
910 priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) +
911 sizeof(struct mlx5_umr_wqe) +
912 RTE_ALIGN(priv->max_segs_num, 4) *
913 sizeof(struct mlx5_wqe_dseg);
914 rdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) +
915 sizeof(struct mlx5_wqe_dseg) *
916 (priv->max_segs_num <= 2 ? 2 : 2 +
917 RTE_ALIGN(priv->max_segs_num - 2, 4));
918 priv->wqe_set_size = priv->umr_wqe_size + rdmw_wqe_size;
919 priv->umr_wqe_stride = priv->umr_wqe_size / MLX5_SEND_WQE_BB;
920 priv->max_rdmar_ds = rdmw_wqe_size / sizeof(struct mlx5_wqe_dseg);
921 pthread_mutex_lock(&priv_list_lock);
922 TAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next);
923 pthread_mutex_unlock(&priv_list_lock);
925 rte_cryptodev_pmd_probing_finish(crypto_dev);
931 mlx5_crypto_dev_remove(struct mlx5_common_device *cdev)
933 struct mlx5_crypto_priv *priv = NULL;
935 pthread_mutex_lock(&priv_list_lock);
936 TAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next)
937 if (priv->crypto_dev->device == cdev->dev)
940 TAILQ_REMOVE(&mlx5_crypto_priv_list, priv, next);
941 pthread_mutex_unlock(&priv_list_lock);
943 mlx5_crypto_uar_release(priv);
944 rte_cryptodev_pmd_destroy(priv->crypto_dev);
945 claim_zero(mlx5_devx_cmd_destroy(priv->login_obj));
950 static const struct rte_pci_id mlx5_crypto_pci_id_map[] = {
952 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
953 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
960 static struct mlx5_class_driver mlx5_crypto_driver = {
961 .drv_class = MLX5_CLASS_CRYPTO,
962 .name = RTE_STR(MLX5_CRYPTO_DRIVER_NAME),
963 .id_table = mlx5_crypto_pci_id_map,
964 .probe = mlx5_crypto_dev_probe,
965 .remove = mlx5_crypto_dev_remove,
968 RTE_INIT(rte_mlx5_crypto_init)
971 if (mlx5_glue != NULL)
972 mlx5_class_driver_register(&mlx5_crypto_driver);
975 RTE_PMD_REGISTER_CRYPTO_DRIVER(mlx5_cryptodev_driver, mlx5_drv,
976 mlx5_crypto_driver_id);
978 RTE_LOG_REGISTER_DEFAULT(mlx5_crypto_logtype, NOTICE)
979 RTE_PMD_EXPORT_NAME(MLX5_CRYPTO_DRIVER_NAME, __COUNTER__);
980 RTE_PMD_REGISTER_PCI_TABLE(MLX5_CRYPTO_DRIVER_NAME, mlx5_crypto_pci_id_map);
981 RTE_PMD_REGISTER_KMOD_DEP(MLX5_CRYPTO_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");