1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2021 NVIDIA Corporation & Affiliates
10 #include <rte_cryptodev.h>
11 #include <cryptodev_pmd.h>
13 #include <mlx5_common_utils.h>
14 #include <mlx5_common_devx.h>
15 #include <mlx5_common_mr.h>
17 #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)
18 #define MLX5_CRYPTO_KEY_LENGTH 80
20 struct mlx5_crypto_priv {
21 TAILQ_ENTRY(mlx5_crypto_priv) next;
22 struct mlx5_common_device *cdev; /* Backend mlx5 device. */
23 struct rte_cryptodev *crypto_dev;
24 void *uar; /* User Access Region. */
25 volatile uint64_t *uar_addr;
26 uint32_t max_segs_num; /* Maximum supported data segs. */
27 struct mlx5_hlist *dek_hlist; /* Dek hash list. */
28 struct rte_cryptodev_config dev_config;
29 struct mlx5_devx_obj *login_obj;
31 uint16_t wqe_set_size;
32 uint16_t umr_wqe_size;
33 uint16_t umr_wqe_stride;
34 uint16_t max_rdmar_ds;
36 rte_spinlock_t uar32_sl;
37 #endif /* RTE_ARCH_64 */
40 struct mlx5_crypto_qp {
41 struct mlx5_crypto_priv *priv;
42 struct mlx5_devx_cq cq_obj;
43 struct mlx5_devx_qp qp_obj;
44 struct rte_cryptodev_stats stats;
45 struct rte_crypto_op **ops;
46 struct mlx5_devx_obj **mkey; /* WQE's indirect mekys. */
47 struct mlx5_mr_ctrl mr_ctrl;
55 struct mlx5_crypto_dek {
56 struct mlx5_list_entry entry; /* Pointer to DEK hash list entry. */
57 struct mlx5_devx_obj *obj; /* Pointer to DEK DevX object. */
58 uint8_t data[MLX5_CRYPTO_KEY_LENGTH]; /* DEK key data. */
59 bool size_is_48; /* Whether the key\data size is 48 bytes or not. */
60 } __rte_cache_aligned;
62 struct mlx5_crypto_devarg_params {
64 struct mlx5_devx_crypto_login_attr login_attr;
66 uint32_t max_segs_num;
70 mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,
71 struct mlx5_crypto_dek *dek);
73 struct mlx5_crypto_dek *
74 mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,
75 struct rte_crypto_cipher_xform *cipher);
78 mlx5_crypto_dek_setup(struct mlx5_crypto_priv *priv);
81 mlx5_crypto_dek_unset(struct mlx5_crypto_priv *priv);
83 #endif /* MLX5_CRYPTO_H_ */