1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
8 #include <rte_cycles.h>
9 #include <rte_byteorder.h>
11 #include "nitrox_csr.h"
13 union nps_pkt_slc_cnts {
16 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
20 uint64_t mbox_int : 1;
30 uint64_t mbox_int : 1;
38 union nps_pkt_slc_int_levels {
41 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
55 union nps_pkt_slc_ctl {
58 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
72 union nps_pkt_in_instr_ctl {
75 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
87 union nps_pkt_in_instr_rsize {
90 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
100 union nps_pkt_in_instr_baoff_dbell {
103 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
113 union nps_pkt_in_done_cnts {
116 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
117 uint64_t slc_int : 1;
118 uint64_t uns_int : 1;
120 uint64_t mbox_int : 1;
128 uint64_t mbox_int : 1;
130 uint64_t uns_int : 1;
131 uint64_t slc_int : 1;
139 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
141 uint64_t host_queue_size : 32;
143 uint64_t host_queue_size : 32;
149 enum nitrox_vf_mode {
150 NITROX_MODE_PF = 0x0,
151 NITROX_MODE_VF16 = 0x1,
152 NITROX_MODE_VF32 = 0x2,
153 NITROX_MODE_VF64 = 0x3,
154 NITROX_MODE_VF128 = 0x4,
157 int vf_get_vf_config_mode(uint8_t *bar_addr);
158 int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode);
159 void setup_nps_pkt_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize,
161 void setup_nps_pkt_solicit_output_port(uint8_t *bar_addr, uint16_t port);
162 void nps_pkt_input_ring_disable(uint8_t *bar_addr, uint16_t ring);
163 void nps_pkt_solicited_port_disable(uint8_t *bar_addr, uint16_t port);
165 #endif /* _NITROX_HAL_H_ */