1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Cavium, Inc
5 #ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
6 #define _OTX_CRYPTODEV_HW_ACCESS_H_
10 #include <rte_memory.h>
12 #include "cpt_common.h"
14 #define CPT_INTR_POLL_INTERVAL_MS (50)
16 /* Default command queue length */
17 #define DEFAULT_CMD_QCHUNKS 2
25 struct command_chunk {
26 /** 128-byte aligned real_vaddr */
28 /** 128-byte aligned real_dma_addr */
33 * Command queue structure
35 struct command_queue {
36 /** Command queue host write idx */
38 /** Command queue chunk */
40 /** Command queue head; instructions are inserted here */
42 /** Command chunk list head */
43 struct command_chunk chead[DEFAULT_CMD_QCHUNKS];
47 * CPT VF device structure
51 struct cpt_instance instance;
52 /** Register start address */
54 /** Command queue information */
55 struct command_queue cqueue;
56 /** Pending queue information */
57 struct pending_queue pqueue;
58 /** Meta information per vf */
59 struct cptvf_meta_info meta_info;
61 /** Below fields are accessed only in control path */
63 /** Env specific pdev representing the pci dev */
65 /** Calculated queue size */
67 /** Device index (0...CPT_MAX_VQ_NUM)*/
69 /** VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */
71 /** VF group (0 - 8) */
73 /** Operating node: Bits (46:44) in BAR0 address */
76 /** VF-PF mailbox communication */
80 /** Flag if not acked */
85 } __rte_cache_aligned;
88 * CPT Registers map for 81xx
92 #define CPTX_VQX_CTL(a, b) (0x0000100ll + 0x1000000000ll * \
93 ((a) & 0x0) + 0x100000ll * (b))
94 #define CPTX_VQX_SADDR(a, b) (0x0000200ll + 0x1000000000ll * \
95 ((a) & 0x0) + 0x100000ll * (b))
96 #define CPTX_VQX_DONE_WAIT(a, b) (0x0000400ll + 0x1000000000ll * \
97 ((a) & 0x0) + 0x100000ll * (b))
98 #define CPTX_VQX_INPROG(a, b) (0x0000410ll + 0x1000000000ll * \
99 ((a) & 0x0) + 0x100000ll * (b))
100 #define CPTX_VQX_DONE(a, b) (0x0000420ll + 0x1000000000ll * \
101 ((a) & 0x1) + 0x100000ll * (b))
102 #define CPTX_VQX_DONE_ACK(a, b) (0x0000440ll + 0x1000000000ll * \
103 ((a) & 0x1) + 0x100000ll * (b))
104 #define CPTX_VQX_DONE_INT_W1S(a, b) (0x0000460ll + 0x1000000000ll * \
105 ((a) & 0x1) + 0x100000ll * (b))
106 #define CPTX_VQX_DONE_INT_W1C(a, b) (0x0000468ll + 0x1000000000ll * \
107 ((a) & 0x1) + 0x100000ll * (b))
108 #define CPTX_VQX_DONE_ENA_W1S(a, b) (0x0000470ll + 0x1000000000ll * \
109 ((a) & 0x1) + 0x100000ll * (b))
110 #define CPTX_VQX_DONE_ENA_W1C(a, b) (0x0000478ll + 0x1000000000ll * \
111 ((a) & 0x1) + 0x100000ll * (b))
112 #define CPTX_VQX_MISC_INT(a, b) (0x0000500ll + 0x1000000000ll * \
113 ((a) & 0x1) + 0x100000ll * (b))
114 #define CPTX_VQX_MISC_INT_W1S(a, b) (0x0000508ll + 0x1000000000ll * \
115 ((a) & 0x1) + 0x100000ll * (b))
116 #define CPTX_VQX_MISC_ENA_W1S(a, b) (0x0000510ll + 0x1000000000ll * \
117 ((a) & 0x1) + 0x100000ll * (b))
118 #define CPTX_VQX_MISC_ENA_W1C(a, b) (0x0000518ll + 0x1000000000ll * \
119 ((a) & 0x1) + 0x100000ll * (b))
120 #define CPTX_VQX_DOORBELL(a, b) (0x0000600ll + 0x1000000000ll * \
121 ((a) & 0x1) + 0x100000ll * (b))
122 #define CPTX_VFX_PF_MBOXX(a, b, c) (0x0001000ll + 0x1000000000ll * \
123 ((a) & 0x1) + 0x100000ll * (b) + \
126 /* VF HAL functions */
129 otx_cpt_poll_misc(struct cpt_vf *cptvf);
132 otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
134 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */