1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Cavium, Inc
5 #ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
6 #define _OTX_CRYPTODEV_HW_ACCESS_H_
11 #include <rte_memory.h>
13 #include "cpt_common.h"
15 #define CPT_INTR_POLL_INTERVAL_MS (50)
17 /* Default command queue length */
18 #define DEFAULT_CMD_QCHUNKS 2
20 #define CPT_CSR_REG_BASE(cpt) ((cpt)->reg_base)
22 /* Read hw register */
23 #define CPT_READ_CSR(__hw_addr, __offset) \
24 rte_read64_relaxed((uint8_t *)__hw_addr + __offset)
26 /* Write hw register */
27 #define CPT_WRITE_CSR(__hw_addr, __offset, __val) \
28 rte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset))
36 struct command_chunk {
37 /** 128-byte aligned real_vaddr */
39 /** 128-byte aligned real_dma_addr */
44 * Command queue structure
46 struct command_queue {
47 /** Command queue host write idx */
49 /** Command queue chunk */
51 /** Command queue head; instructions are inserted here */
53 /** Command chunk list head */
54 struct command_chunk chead[DEFAULT_CMD_QCHUNKS];
58 * CPT VF device structure
62 struct cpt_instance instance;
63 /** Register start address */
65 /** Command queue information */
66 struct command_queue cqueue;
67 /** Pending queue information */
68 struct pending_queue pqueue;
69 /** Meta information per vf */
70 struct cptvf_meta_info meta_info;
72 /** Below fields are accessed only in control path */
74 /** Env specific pdev representing the pci dev */
76 /** Calculated queue size */
78 /** Device index (0...CPT_MAX_VQ_NUM)*/
80 /** VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */
82 /** VF group (0 - 8) */
84 /** Operating node: Bits (46:44) in BAR0 address */
87 /** VF-PF mailbox communication */
91 /** Flag if not acked */
96 } __rte_cache_aligned;
99 * CPT Registers map for 81xx
103 #define CPTX_VQX_CTL(a, b) (0x0000100ll + 0x1000000000ll * \
104 ((a) & 0x0) + 0x100000ll * (b))
105 #define CPTX_VQX_SADDR(a, b) (0x0000200ll + 0x1000000000ll * \
106 ((a) & 0x0) + 0x100000ll * (b))
107 #define CPTX_VQX_DONE_WAIT(a, b) (0x0000400ll + 0x1000000000ll * \
108 ((a) & 0x0) + 0x100000ll * (b))
109 #define CPTX_VQX_INPROG(a, b) (0x0000410ll + 0x1000000000ll * \
110 ((a) & 0x0) + 0x100000ll * (b))
111 #define CPTX_VQX_DONE(a, b) (0x0000420ll + 0x1000000000ll * \
112 ((a) & 0x1) + 0x100000ll * (b))
113 #define CPTX_VQX_DONE_ACK(a, b) (0x0000440ll + 0x1000000000ll * \
114 ((a) & 0x1) + 0x100000ll * (b))
115 #define CPTX_VQX_DONE_INT_W1S(a, b) (0x0000460ll + 0x1000000000ll * \
116 ((a) & 0x1) + 0x100000ll * (b))
117 #define CPTX_VQX_DONE_INT_W1C(a, b) (0x0000468ll + 0x1000000000ll * \
118 ((a) & 0x1) + 0x100000ll * (b))
119 #define CPTX_VQX_DONE_ENA_W1S(a, b) (0x0000470ll + 0x1000000000ll * \
120 ((a) & 0x1) + 0x100000ll * (b))
121 #define CPTX_VQX_DONE_ENA_W1C(a, b) (0x0000478ll + 0x1000000000ll * \
122 ((a) & 0x1) + 0x100000ll * (b))
123 #define CPTX_VQX_MISC_INT(a, b) (0x0000500ll + 0x1000000000ll * \
124 ((a) & 0x1) + 0x100000ll * (b))
125 #define CPTX_VQX_MISC_INT_W1S(a, b) (0x0000508ll + 0x1000000000ll * \
126 ((a) & 0x1) + 0x100000ll * (b))
127 #define CPTX_VQX_MISC_ENA_W1S(a, b) (0x0000510ll + 0x1000000000ll * \
128 ((a) & 0x1) + 0x100000ll * (b))
129 #define CPTX_VQX_MISC_ENA_W1C(a, b) (0x0000518ll + 0x1000000000ll * \
130 ((a) & 0x1) + 0x100000ll * (b))
131 #define CPTX_VQX_DOORBELL(a, b) (0x0000600ll + 0x1000000000ll * \
132 ((a) & 0x1) + 0x100000ll * (b))
133 #define CPTX_VFX_PF_MBOXX(a, b, c) (0x0001000ll + 0x1000000000ll * \
134 ((a) & 0x1) + 0x100000ll * (b) + \
137 /* VF HAL functions */
140 otx_cpt_poll_misc(struct cpt_vf *cptvf);
143 otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
145 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */