1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Cavium, Inc
5 #ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
6 #define _OTX_CRYPTODEV_HW_ACCESS_H_
10 #include <rte_branch_prediction.h>
12 #include <rte_memory.h>
13 #include <rte_prefetch.h>
15 #include "cpt_common.h"
16 #include "cpt_hw_types.h"
17 #include "cpt_pmd_logs.h"
19 #define CPT_INTR_POLL_INTERVAL_MS (50)
21 /* Default command queue length */
22 #define DEFAULT_CMD_QCHUNKS 2
23 #define DEFAULT_CMD_QCHUNK_SIZE 1023
24 #define DEFAULT_CMD_QLEN \
25 (DEFAULT_CMD_QCHUNK_SIZE * DEFAULT_CMD_QCHUNKS)
27 #define CPT_CSR_REG_BASE(cpt) ((cpt)->reg_base)
29 /* Read hw register */
30 #define CPT_READ_CSR(__hw_addr, __offset) \
31 rte_read64_relaxed((uint8_t *)__hw_addr + __offset)
33 /* Write hw register */
34 #define CPT_WRITE_CSR(__hw_addr, __offset, __val) \
35 rte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset))
43 struct command_chunk {
44 /** 128-byte aligned real_vaddr */
46 /** 128-byte aligned real_dma_addr */
51 * Command queue structure
53 struct command_queue {
54 /** Command queue host write idx */
56 /** Command queue chunk */
58 /** Command queue head; instructions are inserted here */
60 /** Command chunk list head */
61 struct command_chunk chead[DEFAULT_CMD_QCHUNKS];
65 * CPT VF device structure
69 struct cpt_instance instance;
70 /** Register start address */
72 /** Command queue information */
73 struct command_queue cqueue;
74 /** Pending queue information */
75 struct pending_queue pqueue;
76 /** Meta information per vf */
77 struct cptvf_meta_info meta_info;
79 /** Below fields are accessed only in control path */
81 /** Env specific pdev representing the pci dev */
83 /** Calculated queue size */
85 /** Device index (0...CPT_MAX_VQ_NUM)*/
87 /** VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */
89 /** VF group (0 - 8) */
91 /** Operating node: Bits (46:44) in BAR0 address */
94 /** VF-PF mailbox communication */
98 /** Flag if not acked */
103 } __rte_cache_aligned;
106 * CPT Registers map for 81xx
110 #define CPTX_VQX_CTL(a, b) (0x0000100ll + 0x1000000000ll * \
111 ((a) & 0x0) + 0x100000ll * (b))
112 #define CPTX_VQX_SADDR(a, b) (0x0000200ll + 0x1000000000ll * \
113 ((a) & 0x0) + 0x100000ll * (b))
114 #define CPTX_VQX_DONE_WAIT(a, b) (0x0000400ll + 0x1000000000ll * \
115 ((a) & 0x0) + 0x100000ll * (b))
116 #define CPTX_VQX_INPROG(a, b) (0x0000410ll + 0x1000000000ll * \
117 ((a) & 0x0) + 0x100000ll * (b))
118 #define CPTX_VQX_DONE(a, b) (0x0000420ll + 0x1000000000ll * \
119 ((a) & 0x1) + 0x100000ll * (b))
120 #define CPTX_VQX_DONE_ACK(a, b) (0x0000440ll + 0x1000000000ll * \
121 ((a) & 0x1) + 0x100000ll * (b))
122 #define CPTX_VQX_DONE_INT_W1S(a, b) (0x0000460ll + 0x1000000000ll * \
123 ((a) & 0x1) + 0x100000ll * (b))
124 #define CPTX_VQX_DONE_INT_W1C(a, b) (0x0000468ll + 0x1000000000ll * \
125 ((a) & 0x1) + 0x100000ll * (b))
126 #define CPTX_VQX_DONE_ENA_W1S(a, b) (0x0000470ll + 0x1000000000ll * \
127 ((a) & 0x1) + 0x100000ll * (b))
128 #define CPTX_VQX_DONE_ENA_W1C(a, b) (0x0000478ll + 0x1000000000ll * \
129 ((a) & 0x1) + 0x100000ll * (b))
130 #define CPTX_VQX_MISC_INT(a, b) (0x0000500ll + 0x1000000000ll * \
131 ((a) & 0x1) + 0x100000ll * (b))
132 #define CPTX_VQX_MISC_INT_W1S(a, b) (0x0000508ll + 0x1000000000ll * \
133 ((a) & 0x1) + 0x100000ll * (b))
134 #define CPTX_VQX_MISC_ENA_W1S(a, b) (0x0000510ll + 0x1000000000ll * \
135 ((a) & 0x1) + 0x100000ll * (b))
136 #define CPTX_VQX_MISC_ENA_W1C(a, b) (0x0000518ll + 0x1000000000ll * \
137 ((a) & 0x1) + 0x100000ll * (b))
138 #define CPTX_VQX_DOORBELL(a, b) (0x0000600ll + 0x1000000000ll * \
139 ((a) & 0x1) + 0x100000ll * (b))
140 #define CPTX_VFX_PF_MBOXX(a, b, c) (0x0001000ll + 0x1000000000ll * \
141 ((a) & 0x1) + 0x100000ll * (b) + \
144 /* VF HAL functions */
147 otx_cpt_poll_misc(struct cpt_vf *cptvf);
150 otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
153 otx_cpt_deinit_device(void *dev);
156 otx_cpt_get_resource(void *dev, uint8_t group, struct cpt_instance **instance);
159 otx_cpt_put_resource(struct cpt_instance *instance);
162 otx_cpt_start_device(void *cptvf);
165 otx_cpt_stop_device(void *cptvf);
167 /* Write to VQX_DOORBELL register
169 static __rte_always_inline void
170 otx_cpt_write_vq_doorbell(struct cpt_vf *cptvf, uint32_t val)
172 cptx_vqx_doorbell_t vqx_dbell;
175 vqx_dbell.s.dbell_cnt = val * 8; /* Num of Instructions * 8 words */
176 CPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),
177 CPTX_VQX_DOORBELL(0, 0), vqx_dbell.u);
180 static __rte_always_inline uint32_t
181 otx_cpt_read_vq_doorbell(struct cpt_vf *cptvf)
183 cptx_vqx_doorbell_t vqx_dbell;
185 vqx_dbell.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),
186 CPTX_VQX_DOORBELL(0, 0));
187 return vqx_dbell.s.dbell_cnt;
190 static __rte_always_inline void
191 otx_cpt_ring_dbell(struct cpt_instance *instance, uint16_t count)
193 struct cpt_vf *cptvf = (struct cpt_vf *)instance;
194 /* Memory barrier to flush pending writes */
196 otx_cpt_write_vq_doorbell(cptvf, count);
199 static __rte_always_inline void *
200 get_cpt_inst(struct command_queue *cqueue)
202 CPT_LOG_DP_DEBUG("CPT queue idx %u\n", cqueue->idx);
203 return &cqueue->qhead[cqueue->idx * CPT_INST_SIZE];
206 static __rte_always_inline void
207 fill_cpt_inst(struct cpt_instance *instance, void *req)
209 struct command_queue *cqueue;
210 cpt_inst_s_t *cpt_ist_p;
211 struct cpt_vf *cptvf = (struct cpt_vf *)instance;
212 struct cpt_request_info *user_req = (struct cpt_request_info *)req;
213 cqueue = &cptvf->cqueue;
214 cpt_ist_p = get_cpt_inst(cqueue);
215 rte_prefetch_non_temporal(cpt_ist_p);
217 /* EI0, EI1, EI2, EI3 are already prepared */
221 cpt_ist_p->s8x.res_addr = user_req->comp_baddr;
225 cpt_ist_p->s8x.wq_ptr = 0;
228 cpt_ist_p->s8x.ei0 = user_req->ist.ei0;
230 cpt_ist_p->s8x.ei1 = user_req->ist.ei1;
232 cpt_ist_p->s8x.ei2 = user_req->ist.ei2;
234 cpt_ist_p->s8x.ei3 = user_req->ist.ei3;
237 static __rte_always_inline void
238 mark_cpt_inst(struct cpt_instance *instance)
240 struct cpt_vf *cptvf = (struct cpt_vf *)instance;
241 struct command_queue *queue = &cptvf->cqueue;
242 if (unlikely(++queue->idx >= DEFAULT_CMD_QCHUNK_SIZE)) {
243 uint32_t cchunk = queue->cchunk;
244 MOD_INC(cchunk, DEFAULT_CMD_QCHUNKS);
245 queue->qhead = queue->chead[cchunk].head;
247 queue->cchunk = cchunk;
251 static __rte_always_inline uint8_t
252 check_nb_command_id(struct cpt_request_info *user_req,
253 struct cpt_instance *instance)
255 /* Required for dequeue operation. Adding a dummy routine for now */
256 RTE_SET_USED(user_req);
257 RTE_SET_USED(instance);
261 #endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */