1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
5 #include <rte_bus_pci.h>
6 #include <rte_common.h>
7 #include <rte_crypto.h>
8 #include <rte_cryptodev.h>
9 #include <rte_cryptodev_pmd.h>
11 #include <rte_errno.h>
12 #include <rte_mempool.h>
15 #include "otx2_common.h"
16 #include "otx2_cryptodev.h"
17 #include "otx2_cryptodev_capabilities.h"
18 #include "otx2_cryptodev_mbox.h"
19 #include "otx2_cryptodev_ops.h"
20 #include "otx2_cryptodev_sec.h"
23 /* CPT common headers */
24 #include "cpt_common.h"
25 #include "cpt_pmd_logs.h"
27 uint8_t otx2_cryptodev_driver_id;
29 static struct rte_pci_id pci_id_cpt_table[] = {
31 RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
32 PCI_DEVID_OCTEONTX2_RVU_CPT_VF)
41 otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
42 struct rte_pci_device *pci_dev)
44 struct rte_cryptodev_pmd_init_params init_params = {
46 .socket_id = rte_socket_id(),
47 .private_data_size = sizeof(struct otx2_cpt_vf)
49 char name[RTE_CRYPTODEV_NAME_MAX_LEN];
50 struct rte_cryptodev *dev;
51 struct otx2_dev *otx2_dev;
52 struct otx2_cpt_vf *vf;
56 rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
58 dev = rte_cryptodev_pmd_create(name, &pci_dev->device, &init_params);
64 dev->dev_ops = &otx2_cpt_ops;
66 dev->driver_id = otx2_cryptodev_driver_id;
68 /* Get private data space allocated */
69 vf = dev->data->dev_private;
71 otx2_dev = &vf->otx2_dev;
73 /* Initialize the base otx2_dev object */
74 ret = otx2_dev_init(pci_dev, otx2_dev);
76 CPT_LOG_ERR("Could not initialize otx2_dev");
80 /* Get number of queues available on the device */
81 ret = otx2_cpt_available_queues_get(dev, &nb_queues);
83 CPT_LOG_ERR("Could not determine the number of queues available");
87 /* Don't exceed the limits set per VF */
88 nb_queues = RTE_MIN(nb_queues, OTX2_CPT_MAX_QUEUES_PER_VF);
91 CPT_LOG_ERR("No free queues available on the device");
95 vf->max_queues = nb_queues;
97 CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues);
99 ret = otx2_cpt_hardware_caps_get(dev, vf->hw_caps);
101 CPT_LOG_ERR("Could not determine hardware capabilities");
105 otx2_crypto_capabilities_init(vf->hw_caps);
106 otx2_crypto_sec_capabilities_init(vf->hw_caps);
108 /* Create security ctx */
109 ret = otx2_crypto_sec_ctx_create(dev);
113 dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
114 RTE_CRYPTODEV_FF_HW_ACCELERATED |
115 RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
116 RTE_CRYPTODEV_FF_IN_PLACE_SGL |
117 RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
118 RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |
119 RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
120 RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT |
121 RTE_CRYPTODEV_FF_SYM_SESSIONLESS |
122 RTE_CRYPTODEV_FF_SECURITY;
127 otx2_dev_fini(pci_dev, otx2_dev);
129 rte_cryptodev_pmd_destroy(dev);
131 CPT_LOG_ERR("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
132 pci_dev->id.vendor_id, pci_dev->id.device_id);
137 otx2_cpt_pci_remove(struct rte_pci_device *pci_dev)
139 char name[RTE_CRYPTODEV_NAME_MAX_LEN];
140 struct rte_cryptodev *dev;
145 rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
147 dev = rte_cryptodev_pmd_get_named_dev(name);
151 /* Destroy security ctx */
152 otx2_crypto_sec_ctx_destroy(dev);
154 return rte_cryptodev_pmd_destroy(dev);
157 static struct rte_pci_driver otx2_cryptodev_pmd = {
158 .id_table = pci_id_cpt_table,
159 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
160 .probe = otx2_cpt_pci_probe,
161 .remove = otx2_cpt_pci_remove,
164 static struct cryptodev_driver otx2_cryptodev_drv;
166 RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX2_PMD, otx2_cryptodev_pmd);
167 RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX2_PMD, pci_id_cpt_table);
168 RTE_PMD_REGISTER_KMOD_DEP(CRYPTODEV_NAME_OCTEONTX2_PMD, "vfio-pci");
169 RTE_PMD_REGISTER_CRYPTO_DRIVER(otx2_cryptodev_drv, otx2_cryptodev_pmd.driver,
170 otx2_cryptodev_driver_id);
171 RTE_LOG_REGISTER(otx2_cpt_logtype, pmd.crypto.octeontx2, NOTICE);