1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
5 #ifndef _OTX2_CRYPTODEV_H_
6 #define _OTX2_CRYPTODEV_H_
8 #include "cpt_common.h"
9 #include "cpt_hw_types.h"
13 /* Marvell OCTEON TX2 Crypto PMD device name */
14 #define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2
16 #define OTX2_CPT_MAX_LFS 128
17 #define OTX2_CPT_MAX_QUEUES_PER_VF 64
18 #define OTX2_CPT_MAX_BLKS 2
19 #define OTX2_CPT_PMD_VERSION 3
20 #define OTX2_CPT_REVISION_ID_3 3
26 struct otx2_dev otx2_dev;
29 /**< Max queues supported */
31 /**< Number of crypto queues attached */
32 uint16_t lf_msixoff[OTX2_CPT_MAX_LFS];
34 uint8_t lf_blkaddr[OTX2_CPT_MAX_LFS];
35 /**< CPT0/1 BLKADDR of LFs */
38 uint8_t err_intr_registered:1;
39 /**< Are error interrupts registered? */
40 union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
41 /**< CPT device capabilities */
44 struct cpt_meta_info {
45 uint64_t deq_op_info[5];
46 uint64_t comp_code_sz;
47 union cpt_res_s cpt_res __rte_aligned(16);
48 struct cpt_request_info cpt_req;
51 #define CPT_LOGTYPE otx2_cpt_logtype
53 extern int otx2_cpt_logtype;
56 * Crypto device driver ID
58 extern uint8_t otx2_cryptodev_driver_id;
60 uint64_t otx2_cpt_default_ff_get(void);
61 void otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);
63 #endif /* _OTX2_CRYPTODEV_H_ */