1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
5 #ifndef _OTX2_CRYPTODEV_H_
6 #define _OTX2_CRYPTODEV_H_
8 #include "cpt_common.h"
9 #include "cpt_hw_types.h"
13 /* Marvell OCTEON TX2 Crypto PMD device name */
14 #define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2
16 #define OTX2_CPT_MAX_LFS 64
17 #define OTX2_CPT_MAX_QUEUES_PER_VF 64
23 struct otx2_dev otx2_dev;
26 /**< Max queues supported */
28 /**< Number of crypto queues attached */
29 uint16_t lf_msixoff[OTX2_CPT_MAX_LFS];
31 uint8_t err_intr_registered:1;
32 /**< Are error interrupts registered? */
33 union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
34 /**< CPT device capabilities */
37 struct cpt_meta_info {
38 uint64_t deq_op_info[4];
39 uint64_t comp_code_sz;
40 union cpt_res_s cpt_res __rte_aligned(16);
41 struct cpt_request_info cpt_req;
44 #define CPT_LOGTYPE otx2_cpt_logtype
46 extern int otx2_cpt_logtype;
49 * Crypto device driver ID
51 extern uint8_t otx2_cryptodev_driver_id;
53 #endif /* _OTX2_CRYPTODEV_H_ */