1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
5 #ifndef _OTX2_CRYPTODEV_H_
6 #define _OTX2_CRYPTODEV_H_
8 #include "cpt_common.h"
9 #include "cpt_hw_types.h"
13 /* Marvell OCTEON TX2 Crypto PMD device name */
14 #define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2
16 #define OTX2_CPT_MAX_LFS 64
17 #define OTX2_CPT_MAX_QUEUES_PER_VF 64
18 #define OTX2_CPT_PMD_VERSION 3
24 struct otx2_dev otx2_dev;
27 /**< Max queues supported */
29 /**< Number of crypto queues attached */
30 uint16_t lf_msixoff[OTX2_CPT_MAX_LFS];
32 uint8_t err_intr_registered:1;
33 /**< Are error interrupts registered? */
34 union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
35 /**< CPT device capabilities */
38 struct cpt_meta_info {
39 uint64_t deq_op_info[4];
40 uint64_t comp_code_sz;
41 union cpt_res_s cpt_res __rte_aligned(16);
42 struct cpt_request_info cpt_req;
45 #define CPT_LOGTYPE otx2_cpt_logtype
47 extern int otx2_cpt_logtype;
50 * Crypto device driver ID
52 extern uint8_t otx2_cryptodev_driver_id;
54 #endif /* _OTX2_CRYPTODEV_H_ */