1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
5 #ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_
6 #define _OTX2_CRYPTODEV_HW_ACCESS_H_
10 #include <rte_cryptodev.h>
11 #include <rte_memory.h>
13 #include "cpt_common.h"
14 #include "cpt_hw_types.h"
18 /* CPT instruction queue length */
19 #define OTX2_CPT_IQ_LEN 8200
21 #define OTX2_CPT_DEFAULT_CMD_QLEN OTX2_CPT_IQ_LEN
23 /* Mask which selects all engine groups */
24 #define OTX2_CPT_ENG_GRPS_MASK 0xFF
26 /* Register offsets */
28 /* LMT LF registers */
29 #define OTX2_LMT_LF_LMTLINE(a) (0x0ull | (uint64_t)(a) << 3)
31 /* CPT LF registers */
32 #define OTX2_CPT_LF_CTL 0x10ull
33 #define OTX2_CPT_LF_INPROG 0x40ull
34 #define OTX2_CPT_LF_MISC_INT 0xb0ull
35 #define OTX2_CPT_LF_MISC_INT_ENA_W1S 0xd0ull
36 #define OTX2_CPT_LF_MISC_INT_ENA_W1C 0xe0ull
37 #define OTX2_CPT_LF_Q_BASE 0xf0ull
38 #define OTX2_CPT_LF_Q_SIZE 0x100ull
39 #define OTX2_CPT_LF_Q_GRP_PTR 0x120ull
40 #define OTX2_CPT_LF_NQ(a) (0x400ull | (uint64_t)(a) << 3)
42 #define OTX2_CPT_AF_LF_CTL(a) (0x27000ull | (uint64_t)(a) << 3)
44 #define OTX2_CPT_LF_BAR2(vf, q_id) \
45 ((vf)->otx2_dev.bar2 + \
46 ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12)))
48 #define OTX2_CPT_QUEUE_HI_PRIO 0x1
50 union otx2_cpt_lf_ctl {
55 uint64_t fc_up_crossing : 1;
56 uint64_t reserved_3_3 : 1;
57 uint64_t fc_hyst_bits : 4;
58 uint64_t reserved_8_63 : 56;
62 union otx2_cpt_lf_inprog {
65 uint64_t inflight : 9;
66 uint64_t reserved_9_15 : 7;
69 uint64_t reserved_18_30 : 13;
70 uint64_t grb_partial : 1;
73 uint64_t reserved_48_63 : 16;
77 union otx2_cpt_lf_q_base {
82 uint64_t reserved_2_6 : 5;
84 uint64_t reserved_53_63 : 11;
88 union otx2_cpt_lf_q_size {
91 uint64_t size_div40 : 15;
92 uint64_t reserved_15_63 : 49;
96 union otx2_cpt_af_lf_ctl {
100 uint64_t reserved_1_8 : 8;
101 uint64_t pf_func_inst : 1;
102 uint64_t cont_err : 1;
103 uint64_t reserved_11_15 : 5;
104 uint64_t nixtx_en : 1;
105 uint64_t reserved_17_47 : 31;
107 uint64_t reserved_56_63 : 8;
111 union otx2_cpt_lf_q_grp_ptr {
114 uint64_t dq_ptr : 15;
115 uint64_t reserved_31_15 : 17;
116 uint64_t nq_ptr : 15;
117 uint64_t reserved_47_62 : 16;
124 /**< Queue pair id */
126 /**< Base address where BAR is mapped */
128 /**< Address of LMTLINE */
129 rte_iova_t lf_nq_reg;
130 /**< LF enqueue register address */
131 struct pending_queue pend_q;
132 /**< Pending queue */
133 struct rte_mempool *sess_mp;
134 /**< Session mempool */
135 struct rte_mempool *sess_mp_priv;
136 /**< Session private data mempool */
137 struct cpt_qp_meta_info meta_info;
138 /**< Metabuf info required to support operations on the queue pair */
139 rte_iova_t iq_dma_addr;
140 /**< Instruction queue address */
143 void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);
145 int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev);
147 int otx2_cpt_iq_enable(const struct rte_cryptodev *dev,
148 const struct otx2_cpt_qp *qp, uint8_t grp_mask,
149 uint8_t pri, uint32_t size_div40);
151 void otx2_cpt_iq_disable(struct otx2_cpt_qp *qp);
153 #endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */