1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
7 #include <rte_cryptodev_pmd.h>
9 #include <rte_ethdev.h>
10 #include <rte_event_crypto_adapter.h>
12 #include "otx2_cryptodev.h"
13 #include "otx2_cryptodev_capabilities.h"
14 #include "otx2_cryptodev_hw_access.h"
15 #include "otx2_cryptodev_mbox.h"
16 #include "otx2_cryptodev_ops.h"
17 #include "otx2_cryptodev_ops_helper.h"
18 #include "otx2_ipsec_anti_replay.h"
19 #include "otx2_ipsec_po_ops.h"
20 #include "otx2_mbox.h"
21 #include "otx2_sec_idev.h"
22 #include "otx2_security.h"
24 #include "cpt_hw_types.h"
25 #include "cpt_pmd_logs.h"
26 #include "cpt_pmd_ops_helper.h"
27 #include "cpt_ucode.h"
28 #include "cpt_ucode_asym.h"
30 #define METABUF_POOL_CACHE_SIZE 512
32 static uint64_t otx2_fpm_iova[CPT_EC_ID_PMAX];
34 /* Forward declarations */
37 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
40 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
42 snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
46 otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
47 struct otx2_cpt_qp *qp, uint8_t qp_id,
50 char mempool_name[RTE_MEMPOOL_NAMESIZE];
51 struct cpt_qp_meta_info *meta_info;
52 struct rte_mempool *pool;
58 if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
60 /* Get meta len for scatter gather mode */
61 sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
63 /* Extra 32B saved for future considerations */
64 sg_mlen += 4 * sizeof(uint64_t);
66 /* Get meta len for linear buffer (direct) mode */
67 lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
69 /* Extra 32B saved for future considerations */
70 lb_mlen += 4 * sizeof(uint64_t);
73 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
75 /* Get meta len required for asymmetric operations */
76 asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
80 * Check max requirement for meta buffer to
81 * support crypto op of any type (sym/asym).
83 max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
85 /* Allocate mempool */
87 snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
88 dev->data->dev_id, qp_id);
90 pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,
91 METABUF_POOL_CACHE_SIZE, 0,
95 CPT_LOG_ERR("Could not create mempool for metabuf");
99 ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
102 CPT_LOG_ERR("Could not set mempool ops");
106 ret = rte_mempool_populate_default(pool);
108 CPT_LOG_ERR("Could not populate metabuf pool");
112 meta_info = &qp->meta_info;
114 meta_info->pool = pool;
115 meta_info->lb_mlen = lb_mlen;
116 meta_info->sg_mlen = sg_mlen;
121 rte_mempool_free(pool);
126 otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
128 struct cpt_qp_meta_info *meta_info = &qp->meta_info;
130 rte_mempool_free(meta_info->pool);
132 meta_info->pool = NULL;
133 meta_info->lb_mlen = 0;
134 meta_info->sg_mlen = 0;
138 otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
140 static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
141 uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
144 for (i = 0; i < nb_ethport; i++) {
145 port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
146 if (otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))
153 ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
157 /* Publish inline Tx QP to eth dev security */
158 ret = otx2_sec_idev_tx_cpt_qp_add(port_id, qp);
165 static struct otx2_cpt_qp *
166 otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
169 struct otx2_cpt_vf *vf = dev->data->dev_private;
170 uint64_t pg_sz = sysconf(_SC_PAGESIZE);
171 const struct rte_memzone *lf_mem;
172 uint32_t len, iq_len, size_div40;
173 char name[RTE_MEMZONE_NAMESIZE];
174 uint64_t used_len, iova;
175 struct otx2_cpt_qp *qp;
180 /* Allocate queue pair */
181 qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
184 CPT_LOG_ERR("Could not allocate queue pair");
188 iq_len = OTX2_CPT_IQ_LEN;
191 * Queue size must be a multiple of 40 and effective queue size to
192 * software is (size_div40 - 1) * 40
194 size_div40 = (iq_len + 40 - 1) / 40 + 1;
196 /* For pending queue */
197 len = iq_len * sizeof(uintptr_t);
199 /* Space for instruction group memory */
200 len += size_div40 * 16;
202 /* So that instruction queues start as pg size aligned */
203 len = RTE_ALIGN(len, pg_sz);
205 /* For instruction queues */
206 len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
208 /* Wastage after instruction queues */
209 len = RTE_ALIGN(len, pg_sz);
211 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
214 lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
215 RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
216 RTE_CACHE_LINE_SIZE);
217 if (lf_mem == NULL) {
218 CPT_LOG_ERR("Could not allocate reserved memzone");
227 ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
229 CPT_LOG_ERR("Could not create mempool for metabuf");
233 /* Initialize pending queue */
234 qp->pend_q.req_queue = (uintptr_t *)va;
235 qp->pend_q.enq_tail = 0;
236 qp->pend_q.deq_head = 0;
237 qp->pend_q.pending_count = 0;
239 used_len = iq_len * sizeof(uintptr_t);
240 used_len += size_div40 * 16;
241 used_len = RTE_ALIGN(used_len, pg_sz);
244 qp->iq_dma_addr = iova;
246 qp->blkaddr = vf->lf_blkaddr[qp_id];
247 qp->base = OTX2_CPT_LF_BAR2(vf, qp->blkaddr, qp_id);
249 lmtline = vf->otx2_dev.bar2 +
250 (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
251 OTX2_LMT_LF_LMTLINE(0);
253 qp->lmtline = (void *)lmtline;
255 qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
257 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
258 if (ret && (ret != -ENOENT)) {
259 CPT_LOG_ERR("Could not delete inline configuration");
260 goto mempool_destroy;
263 otx2_cpt_iq_disable(qp);
265 ret = otx2_cpt_qp_inline_cfg(dev, qp);
267 CPT_LOG_ERR("Could not configure queue for inline IPsec");
268 goto mempool_destroy;
271 ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
274 CPT_LOG_ERR("Could not enable instruction queue");
275 goto mempool_destroy;
281 otx2_cpt_metabuf_mempool_destroy(qp);
283 rte_memzone_free(lf_mem);
290 otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
292 const struct rte_memzone *lf_mem;
293 char name[RTE_MEMZONE_NAMESIZE];
296 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
297 if (ret && (ret != -ENOENT)) {
298 CPT_LOG_ERR("Could not delete inline configuration");
302 otx2_cpt_iq_disable(qp);
304 otx2_cpt_metabuf_mempool_destroy(qp);
306 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
309 lf_mem = rte_memzone_lookup(name);
311 ret = rte_memzone_free(lf_mem);
321 sym_xform_verify(struct rte_crypto_sym_xform *xform)
324 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
325 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
326 xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT &&
327 (xform->auth.algo != RTE_CRYPTO_AUTH_SHA1_HMAC ||
328 xform->next->cipher.algo != RTE_CRYPTO_CIPHER_AES_CBC))
331 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
332 xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT &&
333 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
334 (xform->cipher.algo != RTE_CRYPTO_CIPHER_AES_CBC ||
335 xform->next->auth.algo != RTE_CRYPTO_AUTH_SHA1_HMAC))
338 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
339 xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&
340 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
341 xform->next->auth.algo == RTE_CRYPTO_AUTH_SHA1)
344 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
345 xform->auth.algo == RTE_CRYPTO_AUTH_SHA1 &&
346 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
347 xform->next->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC)
351 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
352 xform->auth.algo == RTE_CRYPTO_AUTH_NULL &&
353 xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY)
360 sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
361 struct rte_cryptodev_sym_session *sess,
362 struct rte_mempool *pool)
364 struct rte_crypto_sym_xform *temp_xform = xform;
365 struct cpt_sess_misc *misc;
366 vq_cmd_word3_t vq_cmd_w3;
370 ret = sym_xform_verify(xform);
374 if (unlikely(rte_mempool_get(pool, &priv))) {
375 CPT_LOG_ERR("Could not allocate session private data");
379 memset(priv, 0, sizeof(struct cpt_sess_misc) +
380 offsetof(struct cpt_ctx, mc_ctx));
384 for ( ; xform != NULL; xform = xform->next) {
385 switch (xform->type) {
386 case RTE_CRYPTO_SYM_XFORM_AEAD:
387 ret = fill_sess_aead(xform, misc);
389 case RTE_CRYPTO_SYM_XFORM_CIPHER:
390 ret = fill_sess_cipher(xform, misc);
392 case RTE_CRYPTO_SYM_XFORM_AUTH:
393 if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
394 ret = fill_sess_gmac(xform, misc);
396 ret = fill_sess_auth(xform, misc);
406 if ((GET_SESS_FC_TYPE(misc) == HASH_HMAC) &&
407 cpt_mac_len_verify(&temp_xform->auth)) {
408 CPT_LOG_ERR("MAC length is not supported");
413 set_sym_session_private_data(sess, driver_id, misc);
415 misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
416 sizeof(struct cpt_sess_misc);
419 vq_cmd_w3.s.cptr = misc->ctx_dma_addr + offsetof(struct cpt_ctx,
423 * IE engines support IPsec operations
424 * SE engines support IPsec operations, Chacha-Poly and
425 * Air-Crypto operations
427 if (misc->zsk_flag || misc->chacha_poly)
428 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE;
430 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE_IE;
432 misc->cpt_inst_w7 = vq_cmd_w3.u64;
437 rte_mempool_put(pool, priv);
442 static __rte_always_inline int32_t __rte_hot
443 otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,
444 struct cpt_request_info *req,
446 struct rte_crypto_op *op,
447 uint64_t cpt_inst_w7)
449 union rte_event_crypto_metadata *m_data;
450 union cpt_inst_s inst;
453 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
454 m_data = rte_cryptodev_sym_session_get_user_data(
456 if (m_data == NULL) {
457 rte_pktmbuf_free(op->sym->m_src);
458 rte_crypto_op_free(op);
462 } else if (op->sess_type == RTE_CRYPTO_OP_SESSIONLESS &&
463 op->private_data_offset) {
464 m_data = (union rte_event_crypto_metadata *)
466 op->private_data_offset);
472 inst.s9x.res_addr = req->comp_baddr;
476 inst.s9x.ei0 = req->ist.ei0;
477 inst.s9x.ei1 = req->ist.ei1;
478 inst.s9x.ei2 = req->ist.ei2;
479 inst.s9x.ei3 = cpt_inst_w7;
481 inst.u[2] = (((RTE_EVENT_TYPE_CRYPTODEV << 28) |
482 m_data->response_info.flow_id) |
483 ((uint64_t)m_data->response_info.sched_type << 32) |
484 ((uint64_t)m_data->response_info.queue_id << 34));
485 inst.u[3] = 1 | (((uint64_t)req >> 3) << 3);
489 /* Copy CPT command to LMTLINE */
490 memcpy(lmtline, &inst, sizeof(inst));
493 * Make sure compiler does not reorder memcpy and ldeor.
494 * LMTST transactions are always flushed from the write
495 * buffer immediately, a DMB is not required to push out
499 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
500 } while (lmt_status == 0);
505 static __rte_always_inline int32_t __rte_hot
506 otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
507 struct pending_queue *pend_q,
508 struct cpt_request_info *req,
509 struct rte_crypto_op *op,
510 uint64_t cpt_inst_w7)
512 void *lmtline = qp->lmtline;
513 union cpt_inst_s inst;
517 return otx2_ca_enqueue_req(qp, req, lmtline, op, cpt_inst_w7);
519 if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
523 inst.s9x.res_addr = req->comp_baddr;
527 inst.s9x.ei0 = req->ist.ei0;
528 inst.s9x.ei1 = req->ist.ei1;
529 inst.s9x.ei2 = req->ist.ei2;
530 inst.s9x.ei3 = cpt_inst_w7;
532 req->time_out = rte_get_timer_cycles() +
533 DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
536 /* Copy CPT command to LMTLINE */
537 memcpy(lmtline, &inst, sizeof(inst));
540 * Make sure compiler does not reorder memcpy and ldeor.
541 * LMTST transactions are always flushed from the write
542 * buffer immediately, a DMB is not required to push out
546 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
547 } while (lmt_status == 0);
549 pend_q->req_queue[pend_q->enq_tail] = (uintptr_t)req;
551 /* We will use soft queue length here to limit requests */
552 MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
553 pend_q->pending_count += 1;
558 static __rte_always_inline int32_t __rte_hot
559 otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
560 struct rte_crypto_op *op,
561 struct pending_queue *pend_q)
563 struct cpt_qp_meta_info *minfo = &qp->meta_info;
564 struct rte_crypto_asym_op *asym_op = op->asym;
565 struct asym_op_params params = {0};
566 struct cpt_asym_sess_misc *sess;
571 if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
572 CPT_LOG_ERR("Could not allocate meta buffer for request");
576 sess = get_asym_session_private_data(asym_op->session,
577 otx2_cryptodev_driver_id);
579 /* Store IO address of the mdata to meta_buf */
580 params.meta_buf = rte_mempool_virt2iova(mdata);
583 cop[0] = (uintptr_t)mdata;
584 cop[1] = (uintptr_t)op;
585 cop[2] = cop[3] = 0ULL;
587 params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
588 params.req->op = cop;
590 /* Adjust meta_buf to point to end of cpt_request_info structure */
591 params.meta_buf += (4 * sizeof(uintptr_t)) +
592 sizeof(struct cpt_request_info);
593 switch (sess->xfrm_type) {
594 case RTE_CRYPTO_ASYM_XFORM_MODEX:
595 ret = cpt_modex_prep(¶ms, &sess->mod_ctx);
599 case RTE_CRYPTO_ASYM_XFORM_RSA:
600 ret = cpt_enqueue_rsa_op(op, ¶ms, sess);
604 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
605 ret = cpt_enqueue_ecdsa_op(op, ¶ms, sess, otx2_fpm_iova);
609 case RTE_CRYPTO_ASYM_XFORM_ECPM:
610 ret = cpt_ecpm_prep(&asym_op->ecpm, ¶ms,
611 sess->ec_ctx.curveid);
616 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
621 ret = otx2_cpt_enqueue_req(qp, pend_q, params.req, op,
625 CPT_LOG_DP_ERR("Could not enqueue crypto req");
632 free_op_meta(mdata, minfo->pool);
637 static __rte_always_inline int __rte_hot
638 otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
639 struct pending_queue *pend_q)
641 struct rte_crypto_sym_op *sym_op = op->sym;
642 struct cpt_request_info *req;
643 struct cpt_sess_misc *sess;
648 sess = get_sym_session_private_data(sym_op->session,
649 otx2_cryptodev_driver_id);
651 cpt_op = sess->cpt_op;
653 if (cpt_op & CPT_OP_CIPHER_MASK)
654 ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
657 ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
661 CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
662 op, (unsigned int)cpt_op, ret);
666 ret = otx2_cpt_enqueue_req(qp, pend_q, req, op, sess->cpt_inst_w7);
669 /* Free buffer allocated by fill params routines */
670 free_op_meta(mdata, qp->meta_info.pool);
676 static __rte_always_inline int __rte_hot
677 otx2_cpt_enqueue_sec(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
678 struct pending_queue *pend_q)
680 uint32_t winsz, esn_low = 0, esn_hi = 0, seql = 0, seqh = 0;
681 struct rte_mbuf *m_src = op->sym->m_src;
682 struct otx2_sec_session_ipsec_lp *sess;
683 struct otx2_ipsec_po_sa_ctl *ctl_wrd;
684 struct otx2_ipsec_po_in_sa *sa;
685 struct otx2_sec_session *priv;
686 struct cpt_request_info *req;
687 uint64_t seq_in_sa, seq = 0;
691 priv = get_sec_session_private_data(op->sym->sec_session);
692 sess = &priv->ipsec.lp;
696 esn = ctl_wrd->esn_en;
697 winsz = sa->replay_win_sz;
699 if (ctl_wrd->direction == OTX2_IPSEC_PO_SA_DIRECTION_OUTBOUND)
700 ret = process_outb_sa(op, sess, &qp->meta_info, (void **)&req);
703 esn_low = rte_be_to_cpu_32(sa->esn_low);
704 esn_hi = rte_be_to_cpu_32(sa->esn_hi);
705 seql = *rte_pktmbuf_mtod_offset(m_src, uint32_t *,
706 sizeof(struct rte_ipv4_hdr) + 4);
707 seql = rte_be_to_cpu_32(seql);
710 seq = (uint64_t)seql;
712 seqh = anti_replay_get_seqh(winsz, seql, esn_hi,
714 seq = ((uint64_t)seqh << 32) | seql;
717 if (unlikely(seq == 0))
718 return IPSEC_ANTI_REPLAY_FAILED;
720 ret = anti_replay_check(sa->replay, seq, winsz);
722 otx2_err("Anti replay check failed");
723 return IPSEC_ANTI_REPLAY_FAILED;
727 ret = process_inb_sa(op, sess, &qp->meta_info, (void **)&req);
731 otx2_err("Crypto req : op %p, ret 0x%x", op, ret);
735 ret = otx2_cpt_enqueue_req(qp, pend_q, req, op, sess->cpt_inst_w7);
738 seq_in_sa = ((uint64_t)esn_hi << 32) | esn_low;
739 if (seq > seq_in_sa) {
740 sa->esn_low = rte_cpu_to_be_32(seql);
741 sa->esn_hi = rte_cpu_to_be_32(seqh);
748 static __rte_always_inline int __rte_hot
749 otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
750 struct pending_queue *pend_q)
752 const int driver_id = otx2_cryptodev_driver_id;
753 struct rte_crypto_sym_op *sym_op = op->sym;
754 struct rte_cryptodev_sym_session *sess;
757 /* Create temporary session */
758 sess = rte_cryptodev_sym_session_create(qp->sess_mp);
762 ret = sym_session_configure(driver_id, sym_op->xform, sess,
767 sym_op->session = sess;
769 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
777 sym_session_clear(driver_id, sess);
779 rte_mempool_put(qp->sess_mp, sess);
784 otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
786 uint16_t nb_allowed, count = 0;
787 struct otx2_cpt_qp *qp = qptr;
788 struct pending_queue *pend_q;
789 struct rte_crypto_op *op;
792 pend_q = &qp->pend_q;
794 nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
795 if (nb_ops > nb_allowed)
798 for (count = 0; count < nb_ops; count++) {
800 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
801 if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)
802 ret = otx2_cpt_enqueue_sec(qp, op, pend_q);
803 else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
804 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
806 ret = otx2_cpt_enqueue_sym_sessless(qp, op,
808 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
809 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
810 ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
823 static __rte_always_inline void
824 otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
825 struct rte_crypto_rsa_xform *rsa_ctx)
827 struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
829 switch (rsa->op_type) {
830 case RTE_CRYPTO_ASYM_OP_ENCRYPT:
831 rsa->cipher.length = rsa_ctx->n.length;
832 memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
834 case RTE_CRYPTO_ASYM_OP_DECRYPT:
835 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
836 rsa->message.length = rsa_ctx->n.length;
837 memcpy(rsa->message.data, req->rptr,
838 rsa->message.length);
840 /* Get length of decrypted output */
841 rsa->message.length = rte_cpu_to_be_16
842 (*((uint16_t *)req->rptr));
844 * Offset output data pointer by length field
845 * (2 bytes) and copy decrypted data.
847 memcpy(rsa->message.data, req->rptr + 2,
848 rsa->message.length);
851 case RTE_CRYPTO_ASYM_OP_SIGN:
852 rsa->sign.length = rsa_ctx->n.length;
853 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
855 case RTE_CRYPTO_ASYM_OP_VERIFY:
856 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
857 rsa->sign.length = rsa_ctx->n.length;
858 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
860 /* Get length of signed output */
861 rsa->sign.length = rte_cpu_to_be_16
862 (*((uint16_t *)req->rptr));
864 * Offset output data pointer by length field
865 * (2 bytes) and copy signed data.
867 memcpy(rsa->sign.data, req->rptr + 2,
870 if (memcmp(rsa->sign.data, rsa->message.data,
871 rsa->message.length)) {
872 CPT_LOG_DP_ERR("RSA verification failed");
873 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
877 CPT_LOG_DP_DEBUG("Invalid RSA operation type");
878 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
883 static __rte_always_inline void
884 otx2_cpt_asym_dequeue_ecdsa_op(struct rte_crypto_ecdsa_op_param *ecdsa,
885 struct cpt_request_info *req,
886 struct cpt_asym_ec_ctx *ec)
888 int prime_len = ec_grp[ec->curveid].prime.length;
890 if (ecdsa->op_type == RTE_CRYPTO_ASYM_OP_VERIFY)
893 /* Separate out sign r and s components */
894 memcpy(ecdsa->r.data, req->rptr, prime_len);
895 memcpy(ecdsa->s.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
897 ecdsa->r.length = prime_len;
898 ecdsa->s.length = prime_len;
901 static __rte_always_inline void
902 otx2_cpt_asym_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param *ecpm,
903 struct cpt_request_info *req,
904 struct cpt_asym_ec_ctx *ec)
906 int prime_len = ec_grp[ec->curveid].prime.length;
908 memcpy(ecpm->r.x.data, req->rptr, prime_len);
909 memcpy(ecpm->r.y.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
911 ecpm->r.x.length = prime_len;
912 ecpm->r.y.length = prime_len;
916 otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
917 struct cpt_request_info *req)
919 struct rte_crypto_asym_op *op = cop->asym;
920 struct cpt_asym_sess_misc *sess;
922 sess = get_asym_session_private_data(op->session,
923 otx2_cryptodev_driver_id);
925 switch (sess->xfrm_type) {
926 case RTE_CRYPTO_ASYM_XFORM_RSA:
927 otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
929 case RTE_CRYPTO_ASYM_XFORM_MODEX:
930 op->modex.result.length = sess->mod_ctx.modulus.length;
931 memcpy(op->modex.result.data, req->rptr,
932 op->modex.result.length);
934 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
935 otx2_cpt_asym_dequeue_ecdsa_op(&op->ecdsa, req, &sess->ec_ctx);
937 case RTE_CRYPTO_ASYM_XFORM_ECPM:
938 otx2_cpt_asym_dequeue_ecpm_op(&op->ecpm, req, &sess->ec_ctx);
941 CPT_LOG_DP_DEBUG("Invalid crypto xform type");
942 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
948 otx2_cpt_sec_post_process(struct rte_crypto_op *cop, uintptr_t *rsp)
950 struct cpt_request_info *req = (struct cpt_request_info *)rsp[2];
951 vq_cmd_word0_t *word0 = (vq_cmd_word0_t *)&req->ist.ei0;
952 struct rte_crypto_sym_op *sym_op = cop->sym;
953 struct rte_mbuf *m = sym_op->m_src;
954 struct rte_ipv6_hdr *ip6;
955 struct rte_ipv4_hdr *ip;
960 mdata_len = (int)rsp[3];
961 rte_pktmbuf_trim(m, mdata_len);
963 if (word0->s.opcode.major == OTX2_IPSEC_PO_PROCESS_IPSEC_INB) {
964 data = rte_pktmbuf_mtod(m, char *);
966 if (rsp[4] == OTX2_IPSEC_PO_TRANSPORT ||
967 rsp[4] == OTX2_IPSEC_PO_TUNNEL_IPV4) {
968 ip = (struct rte_ipv4_hdr *)(data +
969 OTX2_IPSEC_PO_INB_RPTR_HDR);
970 m_len = rte_be_to_cpu_16(ip->total_length);
971 } else if (rsp[4] == OTX2_IPSEC_PO_TUNNEL_IPV6) {
972 ip6 = (struct rte_ipv6_hdr *)(data +
973 OTX2_IPSEC_PO_INB_RPTR_HDR);
974 m_len = rte_be_to_cpu_16(ip6->payload_len) +
975 sizeof(struct rte_ipv6_hdr);
980 m->data_off += OTX2_IPSEC_PO_INB_RPTR_HDR;
985 otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
986 uintptr_t *rsp, uint8_t cc)
990 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
991 if (cop->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
992 if (likely(cc == OTX2_IPSEC_PO_CC_SUCCESS)) {
993 otx2_cpt_sec_post_process(cop, rsp);
994 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
996 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
1001 if (likely(cc == NO_ERR)) {
1002 /* Verify authentication data if required */
1003 if (unlikely(rsp[2]))
1004 compl_auth_verify(cop, (uint8_t *)rsp[2],
1007 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1009 if (cc == ERR_GC_ICV_MISCOMPARE)
1010 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
1012 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
1015 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1016 sym_session_clear(otx2_cryptodev_driver_id,
1018 sz = rte_cryptodev_sym_get_existing_header_session_size(
1020 memset(cop->sym->session, 0, sz);
1021 rte_mempool_put(qp->sess_mp, cop->sym->session);
1022 cop->sym->session = NULL;
1026 if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
1027 if (likely(cc == NO_ERR)) {
1028 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1030 * Pass cpt_req_info stored in metabuf during
1033 rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
1034 otx2_cpt_asym_post_process(cop,
1035 (struct cpt_request_info *)rsp);
1037 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
1042 otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
1044 int i, nb_pending, nb_completed;
1045 struct otx2_cpt_qp *qp = qptr;
1046 struct pending_queue *pend_q;
1047 struct cpt_request_info *req;
1048 struct rte_crypto_op *cop;
1053 pend_q = &qp->pend_q;
1055 nb_pending = pend_q->pending_count;
1057 if (nb_ops > nb_pending)
1058 nb_ops = nb_pending;
1060 for (i = 0; i < nb_ops; i++) {
1061 req = (struct cpt_request_info *)
1062 pend_q->req_queue[pend_q->deq_head];
1064 cc[i] = otx2_cpt_compcode_get(req);
1066 if (unlikely(cc[i] == ERR_REQ_PENDING))
1071 MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
1072 pend_q->pending_count -= 1;
1077 for (i = 0; i < nb_completed; i++) {
1078 rsp = (void *)ops[i];
1080 metabuf = (void *)rsp[0];
1081 cop = (void *)rsp[1];
1085 otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
1087 free_op_meta(metabuf, qp->meta_info.pool);
1090 return nb_completed;
1094 otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)
1096 dev->enqueue_burst = otx2_cpt_enqueue_burst;
1097 dev->dequeue_burst = otx2_cpt_dequeue_burst;
1105 otx2_cpt_dev_config(struct rte_cryptodev *dev,
1106 struct rte_cryptodev_config *conf)
1108 struct otx2_cpt_vf *vf = dev->data->dev_private;
1111 if (conf->nb_queue_pairs > vf->max_queues) {
1112 CPT_LOG_ERR("Invalid number of queue pairs requested");
1116 dev->feature_flags &= ~conf->ff_disable;
1118 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
1119 /* Initialize shared FPM table */
1120 ret = cpt_fpm_init(otx2_fpm_iova);
1125 /* Unregister error interrupts */
1126 if (vf->err_intr_registered)
1127 otx2_cpt_err_intr_unregister(dev);
1130 if (vf->nb_queues) {
1131 ret = otx2_cpt_queues_detach(dev);
1133 CPT_LOG_ERR("Could not detach CPT queues");
1139 ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
1141 CPT_LOG_ERR("Could not attach CPT queues");
1145 ret = otx2_cpt_msix_offsets_get(dev);
1147 CPT_LOG_ERR("Could not get MSI-X offsets");
1151 /* Register error interrupts */
1152 ret = otx2_cpt_err_intr_register(dev);
1154 CPT_LOG_ERR("Could not register error interrupts");
1158 ret = otx2_cpt_inline_init(dev);
1160 CPT_LOG_ERR("Could not enable inline IPsec");
1161 goto intr_unregister;
1164 otx2_cpt_set_enqdeq_fns(dev);
1169 otx2_cpt_err_intr_unregister(dev);
1171 otx2_cpt_queues_detach(dev);
1176 otx2_cpt_dev_start(struct rte_cryptodev *dev)
1180 CPT_PMD_INIT_FUNC_TRACE();
1186 otx2_cpt_dev_stop(struct rte_cryptodev *dev)
1188 CPT_PMD_INIT_FUNC_TRACE();
1190 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
1195 otx2_cpt_dev_close(struct rte_cryptodev *dev)
1197 struct otx2_cpt_vf *vf = dev->data->dev_private;
1200 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1201 ret = otx2_cpt_queue_pair_release(dev, i);
1206 /* Unregister error interrupts */
1207 if (vf->err_intr_registered)
1208 otx2_cpt_err_intr_unregister(dev);
1211 if (vf->nb_queues) {
1212 ret = otx2_cpt_queues_detach(dev);
1214 CPT_LOG_ERR("Could not detach CPT queues");
1221 otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
1222 struct rte_cryptodev_info *info)
1224 struct otx2_cpt_vf *vf = dev->data->dev_private;
1227 info->max_nb_queue_pairs = vf->max_queues;
1228 info->feature_flags = dev->feature_flags;
1229 info->capabilities = otx2_cpt_capabilities_get();
1230 info->sym.max_nb_sessions = 0;
1231 info->driver_id = otx2_cryptodev_driver_id;
1232 info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
1233 info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
1238 otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
1239 const struct rte_cryptodev_qp_conf *conf,
1240 int socket_id __rte_unused)
1242 uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
1243 struct rte_pci_device *pci_dev;
1244 struct otx2_cpt_qp *qp;
1246 CPT_PMD_INIT_FUNC_TRACE();
1248 if (dev->data->queue_pairs[qp_id] != NULL)
1249 otx2_cpt_queue_pair_release(dev, qp_id);
1251 if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
1252 CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
1253 conf->nb_descriptors);
1257 pci_dev = RTE_DEV_TO_PCI(dev->device);
1259 if (pci_dev->mem_resource[2].addr == NULL) {
1260 CPT_LOG_ERR("Invalid PCI mem address");
1264 qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
1266 CPT_LOG_ERR("Could not create queue pair %d", qp_id);
1270 qp->sess_mp = conf->mp_session;
1271 qp->sess_mp_priv = conf->mp_session_private;
1272 dev->data->queue_pairs[qp_id] = qp;
1278 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
1280 struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
1283 CPT_PMD_INIT_FUNC_TRACE();
1288 CPT_LOG_INFO("Releasing queue pair %d", qp_id);
1290 ret = otx2_cpt_qp_destroy(dev, qp);
1292 CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
1296 dev->data->queue_pairs[qp_id] = NULL;
1302 otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
1304 return cpt_get_session_size();
1308 otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
1309 struct rte_crypto_sym_xform *xform,
1310 struct rte_cryptodev_sym_session *sess,
1311 struct rte_mempool *pool)
1313 CPT_PMD_INIT_FUNC_TRACE();
1315 return sym_session_configure(dev->driver_id, xform, sess, pool);
1319 otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
1320 struct rte_cryptodev_sym_session *sess)
1322 CPT_PMD_INIT_FUNC_TRACE();
1324 return sym_session_clear(dev->driver_id, sess);
1328 otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
1330 return sizeof(struct cpt_asym_sess_misc);
1334 otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
1335 struct rte_crypto_asym_xform *xform,
1336 struct rte_cryptodev_asym_session *sess,
1337 struct rte_mempool *pool)
1339 struct cpt_asym_sess_misc *priv;
1340 vq_cmd_word3_t vq_cmd_w3;
1343 CPT_PMD_INIT_FUNC_TRACE();
1345 if (rte_mempool_get(pool, (void **)&priv)) {
1346 CPT_LOG_ERR("Could not allocate session_private_data");
1350 memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
1352 ret = cpt_fill_asym_session_parameters(priv, xform);
1354 CPT_LOG_ERR("Could not configure session parameters");
1356 /* Return session to mempool */
1357 rte_mempool_put(pool, priv);
1362 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_AE;
1363 priv->cpt_inst_w7 = vq_cmd_w3.u64;
1365 set_asym_session_private_data(sess, dev->driver_id, priv);
1371 otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
1372 struct rte_cryptodev_asym_session *sess)
1374 struct cpt_asym_sess_misc *priv;
1375 struct rte_mempool *sess_mp;
1377 CPT_PMD_INIT_FUNC_TRACE();
1379 priv = get_asym_session_private_data(sess, dev->driver_id);
1383 /* Free resources allocated in session_cfg */
1384 cpt_free_asym_session_parameters(priv);
1386 /* Reset and free object back to pool */
1387 memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
1388 sess_mp = rte_mempool_from_obj(priv);
1389 set_asym_session_private_data(sess, dev->driver_id, NULL);
1390 rte_mempool_put(sess_mp, priv);
1393 struct rte_cryptodev_ops otx2_cpt_ops = {
1394 /* Device control ops */
1395 .dev_configure = otx2_cpt_dev_config,
1396 .dev_start = otx2_cpt_dev_start,
1397 .dev_stop = otx2_cpt_dev_stop,
1398 .dev_close = otx2_cpt_dev_close,
1399 .dev_infos_get = otx2_cpt_dev_info_get,
1402 .stats_reset = NULL,
1403 .queue_pair_setup = otx2_cpt_queue_pair_setup,
1404 .queue_pair_release = otx2_cpt_queue_pair_release,
1406 /* Symmetric crypto ops */
1407 .sym_session_get_size = otx2_cpt_sym_session_get_size,
1408 .sym_session_configure = otx2_cpt_sym_session_configure,
1409 .sym_session_clear = otx2_cpt_sym_session_clear,
1411 /* Asymmetric crypto ops */
1412 .asym_session_get_size = otx2_cpt_asym_session_size_get,
1413 .asym_session_configure = otx2_cpt_asym_session_cfg,
1414 .asym_session_clear = otx2_cpt_asym_session_clear,