1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
7 #include <rte_cryptodev_pmd.h>
9 #include <rte_ethdev.h>
10 #include <rte_event_crypto_adapter.h>
12 #include "otx2_cryptodev.h"
13 #include "otx2_cryptodev_capabilities.h"
14 #include "otx2_cryptodev_hw_access.h"
15 #include "otx2_cryptodev_mbox.h"
16 #include "otx2_cryptodev_ops.h"
17 #include "otx2_cryptodev_ops_helper.h"
18 #include "otx2_ipsec_anti_replay.h"
19 #include "otx2_ipsec_po_ops.h"
20 #include "otx2_mbox.h"
21 #include "otx2_sec_idev.h"
22 #include "otx2_security.h"
24 #include "cpt_hw_types.h"
25 #include "cpt_pmd_logs.h"
26 #include "cpt_pmd_ops_helper.h"
27 #include "cpt_ucode.h"
28 #include "cpt_ucode_asym.h"
30 #define METABUF_POOL_CACHE_SIZE 512
32 static uint64_t otx2_fpm_iova[CPT_EC_ID_PMAX];
34 /* Forward declarations */
37 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
40 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
42 snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
46 otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
47 struct otx2_cpt_qp *qp, uint8_t qp_id,
48 unsigned int nb_elements)
50 char mempool_name[RTE_MEMPOOL_NAMESIZE];
51 struct cpt_qp_meta_info *meta_info;
52 int ret, max_mlen, mb_pool_sz;
53 struct rte_mempool *pool;
58 if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
60 /* Get meta len for scatter gather mode */
61 sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
63 /* Extra 32B saved for future considerations */
64 sg_mlen += 4 * sizeof(uint64_t);
66 /* Get meta len for linear buffer (direct) mode */
67 lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
69 /* Extra 32B saved for future considerations */
70 lb_mlen += 4 * sizeof(uint64_t);
73 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
75 /* Get meta len required for asymmetric operations */
76 asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
80 * Check max requirement for meta buffer to
81 * support crypto op of any type (sym/asym).
83 max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
85 /* Allocate mempool */
87 snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
88 dev->data->dev_id, qp_id);
90 mb_pool_sz = RTE_MAX(nb_elements, (METABUF_POOL_CACHE_SIZE * rte_lcore_count()));
92 pool = rte_mempool_create_empty(mempool_name, mb_pool_sz, max_mlen,
93 METABUF_POOL_CACHE_SIZE, 0,
97 CPT_LOG_ERR("Could not create mempool for metabuf");
101 ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
104 CPT_LOG_ERR("Could not set mempool ops");
108 ret = rte_mempool_populate_default(pool);
110 CPT_LOG_ERR("Could not populate metabuf pool");
114 meta_info = &qp->meta_info;
116 meta_info->pool = pool;
117 meta_info->lb_mlen = lb_mlen;
118 meta_info->sg_mlen = sg_mlen;
123 rte_mempool_free(pool);
128 otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
130 struct cpt_qp_meta_info *meta_info = &qp->meta_info;
132 rte_mempool_free(meta_info->pool);
134 meta_info->pool = NULL;
135 meta_info->lb_mlen = 0;
136 meta_info->sg_mlen = 0;
140 otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
142 static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
143 uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
146 for (i = 0; i < nb_ethport; i++) {
147 port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
148 if (otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))
155 ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
159 /* Publish inline Tx QP to eth dev security */
160 ret = otx2_sec_idev_tx_cpt_qp_add(port_id, qp);
167 static struct otx2_cpt_qp *
168 otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
171 struct otx2_cpt_vf *vf = dev->data->dev_private;
172 uint64_t pg_sz = sysconf(_SC_PAGESIZE);
173 const struct rte_memzone *lf_mem;
174 uint32_t len, iq_len, size_div40;
175 char name[RTE_MEMZONE_NAMESIZE];
176 uint64_t used_len, iova;
177 struct otx2_cpt_qp *qp;
182 /* Allocate queue pair */
183 qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
186 CPT_LOG_ERR("Could not allocate queue pair");
190 iq_len = OTX2_CPT_IQ_LEN;
193 * Queue size must be a multiple of 40 and effective queue size to
194 * software is (size_div40 - 1) * 40
196 size_div40 = (iq_len + 40 - 1) / 40 + 1;
198 /* For pending queue */
199 len = iq_len * sizeof(uintptr_t);
201 /* Space for instruction group memory */
202 len += size_div40 * 16;
204 /* So that instruction queues start as pg size aligned */
205 len = RTE_ALIGN(len, pg_sz);
207 /* For instruction queues */
208 len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
210 /* Wastage after instruction queues */
211 len = RTE_ALIGN(len, pg_sz);
213 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
216 lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
217 RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
218 RTE_CACHE_LINE_SIZE);
219 if (lf_mem == NULL) {
220 CPT_LOG_ERR("Could not allocate reserved memzone");
229 ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
231 CPT_LOG_ERR("Could not create mempool for metabuf");
235 /* Initialize pending queue */
236 qp->pend_q.req_queue = (uintptr_t *)va;
237 qp->pend_q.enq_tail = 0;
238 qp->pend_q.deq_head = 0;
239 qp->pend_q.pending_count = 0;
241 used_len = iq_len * sizeof(uintptr_t);
242 used_len += size_div40 * 16;
243 used_len = RTE_ALIGN(used_len, pg_sz);
246 qp->iq_dma_addr = iova;
248 qp->blkaddr = vf->lf_blkaddr[qp_id];
249 qp->base = OTX2_CPT_LF_BAR2(vf, qp->blkaddr, qp_id);
251 lmtline = vf->otx2_dev.bar2 +
252 (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
253 OTX2_LMT_LF_LMTLINE(0);
255 qp->lmtline = (void *)lmtline;
257 qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
259 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
260 if (ret && (ret != -ENOENT)) {
261 CPT_LOG_ERR("Could not delete inline configuration");
262 goto mempool_destroy;
265 otx2_cpt_iq_disable(qp);
267 ret = otx2_cpt_qp_inline_cfg(dev, qp);
269 CPT_LOG_ERR("Could not configure queue for inline IPsec");
270 goto mempool_destroy;
273 ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
276 CPT_LOG_ERR("Could not enable instruction queue");
277 goto mempool_destroy;
283 otx2_cpt_metabuf_mempool_destroy(qp);
285 rte_memzone_free(lf_mem);
292 otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
294 const struct rte_memzone *lf_mem;
295 char name[RTE_MEMZONE_NAMESIZE];
298 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
299 if (ret && (ret != -ENOENT)) {
300 CPT_LOG_ERR("Could not delete inline configuration");
304 otx2_cpt_iq_disable(qp);
306 otx2_cpt_metabuf_mempool_destroy(qp);
308 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
311 lf_mem = rte_memzone_lookup(name);
313 ret = rte_memzone_free(lf_mem);
323 sym_xform_verify(struct rte_crypto_sym_xform *xform)
326 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
327 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
328 xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT &&
329 (xform->auth.algo != RTE_CRYPTO_AUTH_SHA1_HMAC ||
330 xform->next->cipher.algo != RTE_CRYPTO_CIPHER_AES_CBC))
333 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
334 xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT &&
335 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
336 (xform->cipher.algo != RTE_CRYPTO_CIPHER_AES_CBC ||
337 xform->next->auth.algo != RTE_CRYPTO_AUTH_SHA1_HMAC))
340 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
341 xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&
342 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
343 xform->next->auth.algo == RTE_CRYPTO_AUTH_SHA1)
346 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
347 xform->auth.algo == RTE_CRYPTO_AUTH_SHA1 &&
348 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
349 xform->next->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC)
353 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
354 xform->auth.algo == RTE_CRYPTO_AUTH_NULL &&
355 xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY)
362 sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
363 struct rte_cryptodev_sym_session *sess,
364 struct rte_mempool *pool)
366 struct rte_crypto_sym_xform *temp_xform = xform;
367 struct cpt_sess_misc *misc;
368 vq_cmd_word3_t vq_cmd_w3;
372 ret = sym_xform_verify(xform);
376 if (unlikely(rte_mempool_get(pool, &priv))) {
377 CPT_LOG_ERR("Could not allocate session private data");
381 memset(priv, 0, sizeof(struct cpt_sess_misc) +
382 offsetof(struct cpt_ctx, mc_ctx));
386 for ( ; xform != NULL; xform = xform->next) {
387 switch (xform->type) {
388 case RTE_CRYPTO_SYM_XFORM_AEAD:
389 ret = fill_sess_aead(xform, misc);
391 case RTE_CRYPTO_SYM_XFORM_CIPHER:
392 ret = fill_sess_cipher(xform, misc);
394 case RTE_CRYPTO_SYM_XFORM_AUTH:
395 if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
396 ret = fill_sess_gmac(xform, misc);
398 ret = fill_sess_auth(xform, misc);
408 if ((GET_SESS_FC_TYPE(misc) == HASH_HMAC) &&
409 cpt_mac_len_verify(&temp_xform->auth)) {
410 CPT_LOG_ERR("MAC length is not supported");
411 struct cpt_ctx *ctx = SESS_PRIV(misc);
412 if (ctx->auth_key != NULL) {
413 rte_free(ctx->auth_key);
414 ctx->auth_key = NULL;
420 set_sym_session_private_data(sess, driver_id, misc);
422 misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
423 sizeof(struct cpt_sess_misc);
426 vq_cmd_w3.s.cptr = misc->ctx_dma_addr + offsetof(struct cpt_ctx,
430 * IE engines support IPsec operations
431 * SE engines support IPsec operations, Chacha-Poly and
432 * Air-Crypto operations
434 if (misc->zsk_flag || misc->chacha_poly)
435 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE;
437 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE_IE;
439 misc->cpt_inst_w7 = vq_cmd_w3.u64;
444 rte_mempool_put(pool, priv);
449 static __rte_always_inline int32_t __rte_hot
450 otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,
451 struct cpt_request_info *req,
453 struct rte_crypto_op *op,
454 uint64_t cpt_inst_w7)
456 union rte_event_crypto_metadata *m_data;
457 union cpt_inst_s inst;
460 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
461 m_data = rte_cryptodev_sym_session_get_user_data(
463 if (m_data == NULL) {
464 rte_pktmbuf_free(op->sym->m_src);
465 rte_crypto_op_free(op);
469 } else if (op->sess_type == RTE_CRYPTO_OP_SESSIONLESS &&
470 op->private_data_offset) {
471 m_data = (union rte_event_crypto_metadata *)
473 op->private_data_offset);
479 inst.s9x.res_addr = req->comp_baddr;
483 inst.s9x.ei0 = req->ist.ei0;
484 inst.s9x.ei1 = req->ist.ei1;
485 inst.s9x.ei2 = req->ist.ei2;
486 inst.s9x.ei3 = cpt_inst_w7;
488 inst.u[2] = (((RTE_EVENT_TYPE_CRYPTODEV << 28) |
489 m_data->response_info.flow_id) |
490 ((uint64_t)m_data->response_info.sched_type << 32) |
491 ((uint64_t)m_data->response_info.queue_id << 34));
492 inst.u[3] = 1 | (((uint64_t)req >> 3) << 3);
496 /* Copy CPT command to LMTLINE */
497 memcpy(lmtline, &inst, sizeof(inst));
500 * Make sure compiler does not reorder memcpy and ldeor.
501 * LMTST transactions are always flushed from the write
502 * buffer immediately, a DMB is not required to push out
506 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
507 } while (lmt_status == 0);
512 static __rte_always_inline int32_t __rte_hot
513 otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
514 struct pending_queue *pend_q,
515 struct cpt_request_info *req,
516 struct rte_crypto_op *op,
517 uint64_t cpt_inst_w7)
519 void *lmtline = qp->lmtline;
520 union cpt_inst_s inst;
524 return otx2_ca_enqueue_req(qp, req, lmtline, op, cpt_inst_w7);
526 if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
530 inst.s9x.res_addr = req->comp_baddr;
534 inst.s9x.ei0 = req->ist.ei0;
535 inst.s9x.ei1 = req->ist.ei1;
536 inst.s9x.ei2 = req->ist.ei2;
537 inst.s9x.ei3 = cpt_inst_w7;
539 req->time_out = rte_get_timer_cycles() +
540 DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
543 /* Copy CPT command to LMTLINE */
544 memcpy(lmtline, &inst, sizeof(inst));
547 * Make sure compiler does not reorder memcpy and ldeor.
548 * LMTST transactions are always flushed from the write
549 * buffer immediately, a DMB is not required to push out
553 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
554 } while (lmt_status == 0);
556 pend_q->req_queue[pend_q->enq_tail] = (uintptr_t)req;
558 /* We will use soft queue length here to limit requests */
559 MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
560 pend_q->pending_count += 1;
565 static __rte_always_inline int32_t __rte_hot
566 otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
567 struct rte_crypto_op *op,
568 struct pending_queue *pend_q)
570 struct cpt_qp_meta_info *minfo = &qp->meta_info;
571 struct rte_crypto_asym_op *asym_op = op->asym;
572 struct asym_op_params params = {0};
573 struct cpt_asym_sess_misc *sess;
578 if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
579 CPT_LOG_ERR("Could not allocate meta buffer for request");
583 sess = get_asym_session_private_data(asym_op->session,
584 otx2_cryptodev_driver_id);
586 /* Store IO address of the mdata to meta_buf */
587 params.meta_buf = rte_mempool_virt2iova(mdata);
590 cop[0] = (uintptr_t)mdata;
591 cop[1] = (uintptr_t)op;
592 cop[2] = cop[3] = 0ULL;
594 params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
595 params.req->op = cop;
597 /* Adjust meta_buf to point to end of cpt_request_info structure */
598 params.meta_buf += (4 * sizeof(uintptr_t)) +
599 sizeof(struct cpt_request_info);
600 switch (sess->xfrm_type) {
601 case RTE_CRYPTO_ASYM_XFORM_MODEX:
602 ret = cpt_modex_prep(¶ms, &sess->mod_ctx);
606 case RTE_CRYPTO_ASYM_XFORM_RSA:
607 ret = cpt_enqueue_rsa_op(op, ¶ms, sess);
611 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
612 ret = cpt_enqueue_ecdsa_op(op, ¶ms, sess, otx2_fpm_iova);
616 case RTE_CRYPTO_ASYM_XFORM_ECPM:
617 ret = cpt_ecpm_prep(&asym_op->ecpm, ¶ms,
618 sess->ec_ctx.curveid);
623 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
628 ret = otx2_cpt_enqueue_req(qp, pend_q, params.req, op,
632 CPT_LOG_DP_ERR("Could not enqueue crypto req");
639 free_op_meta(mdata, minfo->pool);
644 static __rte_always_inline int __rte_hot
645 otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
646 struct pending_queue *pend_q)
648 struct rte_crypto_sym_op *sym_op = op->sym;
649 struct cpt_request_info *req;
650 struct cpt_sess_misc *sess;
655 sess = get_sym_session_private_data(sym_op->session,
656 otx2_cryptodev_driver_id);
658 cpt_op = sess->cpt_op;
660 if (cpt_op & CPT_OP_CIPHER_MASK)
661 ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
664 ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
668 CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
669 op, (unsigned int)cpt_op, ret);
673 ret = otx2_cpt_enqueue_req(qp, pend_q, req, op, sess->cpt_inst_w7);
676 /* Free buffer allocated by fill params routines */
677 free_op_meta(mdata, qp->meta_info.pool);
683 static __rte_always_inline int __rte_hot
684 otx2_cpt_enqueue_sec(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
685 struct pending_queue *pend_q)
687 uint32_t winsz, esn_low = 0, esn_hi = 0, seql = 0, seqh = 0;
688 struct rte_mbuf *m_src = op->sym->m_src;
689 struct otx2_sec_session_ipsec_lp *sess;
690 struct otx2_ipsec_po_sa_ctl *ctl_wrd;
691 struct otx2_ipsec_po_in_sa *sa;
692 struct otx2_sec_session *priv;
693 struct cpt_request_info *req;
694 uint64_t seq_in_sa, seq = 0;
698 priv = get_sec_session_private_data(op->sym->sec_session);
699 sess = &priv->ipsec.lp;
703 esn = ctl_wrd->esn_en;
704 winsz = sa->replay_win_sz;
706 if (ctl_wrd->direction == OTX2_IPSEC_PO_SA_DIRECTION_OUTBOUND)
707 ret = process_outb_sa(op, sess, &qp->meta_info, (void **)&req);
710 esn_low = rte_be_to_cpu_32(sa->esn_low);
711 esn_hi = rte_be_to_cpu_32(sa->esn_hi);
712 seql = *rte_pktmbuf_mtod_offset(m_src, uint32_t *,
713 sizeof(struct rte_ipv4_hdr) + 4);
714 seql = rte_be_to_cpu_32(seql);
717 seq = (uint64_t)seql;
719 seqh = anti_replay_get_seqh(winsz, seql, esn_hi,
721 seq = ((uint64_t)seqh << 32) | seql;
724 if (unlikely(seq == 0))
725 return IPSEC_ANTI_REPLAY_FAILED;
727 ret = anti_replay_check(sa->replay, seq, winsz);
729 otx2_err("Anti replay check failed");
730 return IPSEC_ANTI_REPLAY_FAILED;
734 ret = process_inb_sa(op, sess, &qp->meta_info, (void **)&req);
738 otx2_err("Crypto req : op %p, ret 0x%x", op, ret);
742 ret = otx2_cpt_enqueue_req(qp, pend_q, req, op, sess->cpt_inst_w7);
745 seq_in_sa = ((uint64_t)esn_hi << 32) | esn_low;
746 if (seq > seq_in_sa) {
747 sa->esn_low = rte_cpu_to_be_32(seql);
748 sa->esn_hi = rte_cpu_to_be_32(seqh);
755 static __rte_always_inline int __rte_hot
756 otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
757 struct pending_queue *pend_q)
759 const int driver_id = otx2_cryptodev_driver_id;
760 struct rte_crypto_sym_op *sym_op = op->sym;
761 struct rte_cryptodev_sym_session *sess;
764 /* Create temporary session */
765 sess = rte_cryptodev_sym_session_create(qp->sess_mp);
769 ret = sym_session_configure(driver_id, sym_op->xform, sess,
774 sym_op->session = sess;
776 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
784 sym_session_clear(driver_id, sess);
786 rte_mempool_put(qp->sess_mp, sess);
791 otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
793 uint16_t nb_allowed, count = 0;
794 struct otx2_cpt_qp *qp = qptr;
795 struct pending_queue *pend_q;
796 struct rte_crypto_op *op;
799 pend_q = &qp->pend_q;
801 nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
802 if (nb_ops > nb_allowed)
805 for (count = 0; count < nb_ops; count++) {
807 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
808 if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)
809 ret = otx2_cpt_enqueue_sec(qp, op, pend_q);
810 else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
811 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
813 ret = otx2_cpt_enqueue_sym_sessless(qp, op,
815 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
816 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
817 ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
830 static __rte_always_inline void
831 otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
832 struct rte_crypto_rsa_xform *rsa_ctx)
834 struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
836 switch (rsa->op_type) {
837 case RTE_CRYPTO_ASYM_OP_ENCRYPT:
838 rsa->cipher.length = rsa_ctx->n.length;
839 memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
841 case RTE_CRYPTO_ASYM_OP_DECRYPT:
842 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
843 rsa->message.length = rsa_ctx->n.length;
844 memcpy(rsa->message.data, req->rptr,
845 rsa->message.length);
847 /* Get length of decrypted output */
848 rsa->message.length = rte_cpu_to_be_16
849 (*((uint16_t *)req->rptr));
851 * Offset output data pointer by length field
852 * (2 bytes) and copy decrypted data.
854 memcpy(rsa->message.data, req->rptr + 2,
855 rsa->message.length);
858 case RTE_CRYPTO_ASYM_OP_SIGN:
859 rsa->sign.length = rsa_ctx->n.length;
860 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
862 case RTE_CRYPTO_ASYM_OP_VERIFY:
863 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
864 rsa->sign.length = rsa_ctx->n.length;
865 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
867 /* Get length of signed output */
868 rsa->sign.length = rte_cpu_to_be_16
869 (*((uint16_t *)req->rptr));
871 * Offset output data pointer by length field
872 * (2 bytes) and copy signed data.
874 memcpy(rsa->sign.data, req->rptr + 2,
877 if (memcmp(rsa->sign.data, rsa->message.data,
878 rsa->message.length)) {
879 CPT_LOG_DP_ERR("RSA verification failed");
880 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
884 CPT_LOG_DP_DEBUG("Invalid RSA operation type");
885 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
890 static __rte_always_inline void
891 otx2_cpt_asym_dequeue_ecdsa_op(struct rte_crypto_ecdsa_op_param *ecdsa,
892 struct cpt_request_info *req,
893 struct cpt_asym_ec_ctx *ec)
895 int prime_len = ec_grp[ec->curveid].prime.length;
897 if (ecdsa->op_type == RTE_CRYPTO_ASYM_OP_VERIFY)
900 /* Separate out sign r and s components */
901 memcpy(ecdsa->r.data, req->rptr, prime_len);
902 memcpy(ecdsa->s.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
904 ecdsa->r.length = prime_len;
905 ecdsa->s.length = prime_len;
908 static __rte_always_inline void
909 otx2_cpt_asym_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param *ecpm,
910 struct cpt_request_info *req,
911 struct cpt_asym_ec_ctx *ec)
913 int prime_len = ec_grp[ec->curveid].prime.length;
915 memcpy(ecpm->r.x.data, req->rptr, prime_len);
916 memcpy(ecpm->r.y.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
918 ecpm->r.x.length = prime_len;
919 ecpm->r.y.length = prime_len;
923 otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
924 struct cpt_request_info *req)
926 struct rte_crypto_asym_op *op = cop->asym;
927 struct cpt_asym_sess_misc *sess;
929 sess = get_asym_session_private_data(op->session,
930 otx2_cryptodev_driver_id);
932 switch (sess->xfrm_type) {
933 case RTE_CRYPTO_ASYM_XFORM_RSA:
934 otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
936 case RTE_CRYPTO_ASYM_XFORM_MODEX:
937 op->modex.result.length = sess->mod_ctx.modulus.length;
938 memcpy(op->modex.result.data, req->rptr,
939 op->modex.result.length);
941 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
942 otx2_cpt_asym_dequeue_ecdsa_op(&op->ecdsa, req, &sess->ec_ctx);
944 case RTE_CRYPTO_ASYM_XFORM_ECPM:
945 otx2_cpt_asym_dequeue_ecpm_op(&op->ecpm, req, &sess->ec_ctx);
948 CPT_LOG_DP_DEBUG("Invalid crypto xform type");
949 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
955 otx2_cpt_sec_post_process(struct rte_crypto_op *cop, uintptr_t *rsp)
957 struct cpt_request_info *req = (struct cpt_request_info *)rsp[2];
958 vq_cmd_word0_t *word0 = (vq_cmd_word0_t *)&req->ist.ei0;
959 struct rte_crypto_sym_op *sym_op = cop->sym;
960 struct rte_mbuf *m = sym_op->m_src;
961 struct rte_ipv6_hdr *ip6;
962 struct rte_ipv4_hdr *ip;
967 mdata_len = (int)rsp[3];
968 rte_pktmbuf_trim(m, mdata_len);
970 if (word0->s.opcode.major == OTX2_IPSEC_PO_PROCESS_IPSEC_INB) {
971 data = rte_pktmbuf_mtod(m, char *);
973 if (rsp[4] == OTX2_IPSEC_PO_TRANSPORT ||
974 rsp[4] == OTX2_IPSEC_PO_TUNNEL_IPV4) {
975 ip = (struct rte_ipv4_hdr *)(data +
976 OTX2_IPSEC_PO_INB_RPTR_HDR);
977 m_len = rte_be_to_cpu_16(ip->total_length);
978 } else if (rsp[4] == OTX2_IPSEC_PO_TUNNEL_IPV6) {
979 ip6 = (struct rte_ipv6_hdr *)(data +
980 OTX2_IPSEC_PO_INB_RPTR_HDR);
981 m_len = rte_be_to_cpu_16(ip6->payload_len) +
982 sizeof(struct rte_ipv6_hdr);
987 m->data_off += OTX2_IPSEC_PO_INB_RPTR_HDR;
992 otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
993 uintptr_t *rsp, uint8_t cc)
997 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
998 if (cop->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
999 if (likely(cc == OTX2_IPSEC_PO_CC_SUCCESS)) {
1000 otx2_cpt_sec_post_process(cop, rsp);
1001 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1003 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
1008 if (likely(cc == NO_ERR)) {
1009 /* Verify authentication data if required */
1010 if (unlikely(rsp[2]))
1011 compl_auth_verify(cop, (uint8_t *)rsp[2],
1014 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1016 if (cc == ERR_GC_ICV_MISCOMPARE)
1017 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
1019 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
1022 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
1023 sym_session_clear(otx2_cryptodev_driver_id,
1025 sz = rte_cryptodev_sym_get_existing_header_session_size(
1027 memset(cop->sym->session, 0, sz);
1028 rte_mempool_put(qp->sess_mp, cop->sym->session);
1029 cop->sym->session = NULL;
1033 if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
1034 if (likely(cc == NO_ERR)) {
1035 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1037 * Pass cpt_req_info stored in metabuf during
1040 rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
1041 otx2_cpt_asym_post_process(cop,
1042 (struct cpt_request_info *)rsp);
1044 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
1049 otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
1051 int i, nb_pending, nb_completed;
1052 struct otx2_cpt_qp *qp = qptr;
1053 struct pending_queue *pend_q;
1054 struct cpt_request_info *req;
1055 struct rte_crypto_op *cop;
1060 pend_q = &qp->pend_q;
1062 nb_pending = pend_q->pending_count;
1064 if (nb_ops > nb_pending)
1065 nb_ops = nb_pending;
1067 for (i = 0; i < nb_ops; i++) {
1068 req = (struct cpt_request_info *)
1069 pend_q->req_queue[pend_q->deq_head];
1071 cc[i] = otx2_cpt_compcode_get(req);
1073 if (unlikely(cc[i] == ERR_REQ_PENDING))
1078 MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
1079 pend_q->pending_count -= 1;
1084 for (i = 0; i < nb_completed; i++) {
1085 rsp = (void *)ops[i];
1087 metabuf = (void *)rsp[0];
1088 cop = (void *)rsp[1];
1092 otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
1094 free_op_meta(metabuf, qp->meta_info.pool);
1097 return nb_completed;
1101 otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)
1103 dev->enqueue_burst = otx2_cpt_enqueue_burst;
1104 dev->dequeue_burst = otx2_cpt_dequeue_burst;
1112 otx2_cpt_dev_config(struct rte_cryptodev *dev,
1113 struct rte_cryptodev_config *conf)
1115 struct otx2_cpt_vf *vf = dev->data->dev_private;
1118 if (conf->nb_queue_pairs > vf->max_queues) {
1119 CPT_LOG_ERR("Invalid number of queue pairs requested");
1123 dev->feature_flags = otx2_cpt_default_ff_get() & ~conf->ff_disable;
1125 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
1126 /* Initialize shared FPM table */
1127 ret = cpt_fpm_init(otx2_fpm_iova);
1132 /* Unregister error interrupts */
1133 if (vf->err_intr_registered)
1134 otx2_cpt_err_intr_unregister(dev);
1137 if (vf->nb_queues) {
1138 ret = otx2_cpt_queues_detach(dev);
1140 CPT_LOG_ERR("Could not detach CPT queues");
1146 ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
1148 CPT_LOG_ERR("Could not attach CPT queues");
1152 ret = otx2_cpt_msix_offsets_get(dev);
1154 CPT_LOG_ERR("Could not get MSI-X offsets");
1158 /* Register error interrupts */
1159 ret = otx2_cpt_err_intr_register(dev);
1161 CPT_LOG_ERR("Could not register error interrupts");
1165 ret = otx2_cpt_inline_init(dev);
1167 CPT_LOG_ERR("Could not enable inline IPsec");
1168 goto intr_unregister;
1171 otx2_cpt_set_enqdeq_fns(dev);
1176 otx2_cpt_err_intr_unregister(dev);
1178 otx2_cpt_queues_detach(dev);
1183 otx2_cpt_dev_start(struct rte_cryptodev *dev)
1187 CPT_PMD_INIT_FUNC_TRACE();
1193 otx2_cpt_dev_stop(struct rte_cryptodev *dev)
1195 CPT_PMD_INIT_FUNC_TRACE();
1197 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
1202 otx2_cpt_dev_close(struct rte_cryptodev *dev)
1204 struct otx2_cpt_vf *vf = dev->data->dev_private;
1207 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1208 ret = otx2_cpt_queue_pair_release(dev, i);
1213 /* Unregister error interrupts */
1214 if (vf->err_intr_registered)
1215 otx2_cpt_err_intr_unregister(dev);
1218 if (vf->nb_queues) {
1219 ret = otx2_cpt_queues_detach(dev);
1221 CPT_LOG_ERR("Could not detach CPT queues");
1228 otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
1229 struct rte_cryptodev_info *info)
1231 struct otx2_cpt_vf *vf = dev->data->dev_private;
1234 info->max_nb_queue_pairs = vf->max_queues;
1235 info->feature_flags = otx2_cpt_default_ff_get();
1236 info->capabilities = otx2_cpt_capabilities_get();
1237 info->sym.max_nb_sessions = 0;
1238 info->driver_id = otx2_cryptodev_driver_id;
1239 info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
1240 info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
1245 otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
1246 const struct rte_cryptodev_qp_conf *conf,
1247 int socket_id __rte_unused)
1249 uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
1250 struct rte_pci_device *pci_dev;
1251 struct otx2_cpt_qp *qp;
1253 CPT_PMD_INIT_FUNC_TRACE();
1255 if (dev->data->queue_pairs[qp_id] != NULL)
1256 otx2_cpt_queue_pair_release(dev, qp_id);
1258 if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
1259 CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
1260 conf->nb_descriptors);
1264 pci_dev = RTE_DEV_TO_PCI(dev->device);
1266 if (pci_dev->mem_resource[2].addr == NULL) {
1267 CPT_LOG_ERR("Invalid PCI mem address");
1271 qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
1273 CPT_LOG_ERR("Could not create queue pair %d", qp_id);
1277 qp->sess_mp = conf->mp_session;
1278 qp->sess_mp_priv = conf->mp_session_private;
1279 dev->data->queue_pairs[qp_id] = qp;
1285 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
1287 struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
1290 CPT_PMD_INIT_FUNC_TRACE();
1295 CPT_LOG_INFO("Releasing queue pair %d", qp_id);
1297 ret = otx2_cpt_qp_destroy(dev, qp);
1299 CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
1303 dev->data->queue_pairs[qp_id] = NULL;
1309 otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
1311 return cpt_get_session_size();
1315 otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
1316 struct rte_crypto_sym_xform *xform,
1317 struct rte_cryptodev_sym_session *sess,
1318 struct rte_mempool *pool)
1320 CPT_PMD_INIT_FUNC_TRACE();
1322 return sym_session_configure(dev->driver_id, xform, sess, pool);
1326 otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
1327 struct rte_cryptodev_sym_session *sess)
1329 CPT_PMD_INIT_FUNC_TRACE();
1331 return sym_session_clear(dev->driver_id, sess);
1335 otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
1337 return sizeof(struct cpt_asym_sess_misc);
1341 otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
1342 struct rte_crypto_asym_xform *xform,
1343 struct rte_cryptodev_asym_session *sess,
1344 struct rte_mempool *pool)
1346 struct cpt_asym_sess_misc *priv;
1347 vq_cmd_word3_t vq_cmd_w3;
1350 CPT_PMD_INIT_FUNC_TRACE();
1352 if (rte_mempool_get(pool, (void **)&priv)) {
1353 CPT_LOG_ERR("Could not allocate session_private_data");
1357 memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
1359 ret = cpt_fill_asym_session_parameters(priv, xform);
1361 CPT_LOG_ERR("Could not configure session parameters");
1363 /* Return session to mempool */
1364 rte_mempool_put(pool, priv);
1369 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_AE;
1370 priv->cpt_inst_w7 = vq_cmd_w3.u64;
1372 set_asym_session_private_data(sess, dev->driver_id, priv);
1378 otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
1379 struct rte_cryptodev_asym_session *sess)
1381 struct cpt_asym_sess_misc *priv;
1382 struct rte_mempool *sess_mp;
1384 CPT_PMD_INIT_FUNC_TRACE();
1386 priv = get_asym_session_private_data(sess, dev->driver_id);
1390 /* Free resources allocated in session_cfg */
1391 cpt_free_asym_session_parameters(priv);
1393 /* Reset and free object back to pool */
1394 memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
1395 sess_mp = rte_mempool_from_obj(priv);
1396 set_asym_session_private_data(sess, dev->driver_id, NULL);
1397 rte_mempool_put(sess_mp, priv);
1400 struct rte_cryptodev_ops otx2_cpt_ops = {
1401 /* Device control ops */
1402 .dev_configure = otx2_cpt_dev_config,
1403 .dev_start = otx2_cpt_dev_start,
1404 .dev_stop = otx2_cpt_dev_stop,
1405 .dev_close = otx2_cpt_dev_close,
1406 .dev_infos_get = otx2_cpt_dev_info_get,
1409 .stats_reset = NULL,
1410 .queue_pair_setup = otx2_cpt_queue_pair_setup,
1411 .queue_pair_release = otx2_cpt_queue_pair_release,
1413 /* Symmetric crypto ops */
1414 .sym_session_get_size = otx2_cpt_sym_session_get_size,
1415 .sym_session_configure = otx2_cpt_sym_session_configure,
1416 .sym_session_clear = otx2_cpt_sym_session_clear,
1418 /* Asymmetric crypto ops */
1419 .asym_session_get_size = otx2_cpt_asym_session_size_get,
1420 .asym_session_configure = otx2_cpt_asym_session_cfg,
1421 .asym_session_clear = otx2_cpt_asym_session_clear,